[deliverable/linux.git] / arch / x86 / events / intel / uncore.h

#include <linux/slab.h>
#include <linux/pci.h>
#include <asm/apicdef.h>

#include <linux/perf_event.h>
#include "../perf_event.h"

#define UNCORE_PMU_NAME_LEN		32
#define UNCORE_PMU_HRTIMER_INTERVAL	(60LL * NSEC_PER_SEC)
#define UNCORE_SNB_IMC_HRTIMER_INTERVAL (5ULL * NSEC_PER_SEC)

#define UNCORE_FIXED_EVENT		0xff
#define UNCORE_PMC_IDX_MAX_GENERIC	8
#define UNCORE_PMC_IDX_FIXED		UNCORE_PMC_IDX_MAX_GENERIC
#define UNCORE_PMC_IDX_MAX		(UNCORE_PMC_IDX_FIXED + 1)

#define UNCORE_PCI_DEV_FULL_DATA(dev, func, type, idx)	\
		((dev << 24) | (func << 16) | (type << 8) | idx)
#define UNCORE_PCI_DEV_DATA(type, idx)	((type << 8) | idx)
#define UNCORE_PCI_DEV_DEV(data)	((data >> 24) & 0xff)
#define UNCORE_PCI_DEV_FUNC(data)	((data >> 16) & 0xff)
#define UNCORE_PCI_DEV_TYPE(data)	((data >> 8) & 0xff)
#define UNCORE_PCI_DEV_IDX(data)	(data & 0xff)
#define UNCORE_EXTRA_PCI_DEV		0xff
#define UNCORE_EXTRA_PCI_DEV_MAX	3

#define UNCORE_EVENT_CONSTRAINT(c, n) EVENT_CONSTRAINT(c, n, 0xff)

struct pci_extra_dev {
	struct pci_dev *dev[UNCORE_EXTRA_PCI_DEV_MAX];
};

struct intel_uncore_ops;
struct intel_uncore_pmu;
struct intel_uncore_box;
struct uncore_event_desc;

struct intel_uncore_type {
	const char *name;
	int num_counters;
	int num_boxes;
	int perf_ctr_bits;
	int fixed_ctr_bits;
	unsigned perf_ctr;
	unsigned event_ctl;
	unsigned event_mask;
	unsigned fixed_ctr;
	unsigned fixed_ctl;
	unsigned box_ctl;
	unsigned msr_offset;
	unsigned num_shared_regs:8;
	unsigned single_fixed:1;
	unsigned pair_ctr_ctl:1;
	unsigned *msr_offsets;
	struct event_constraint unconstrainted;
	struct event_constraint *constraints;
	struct intel_uncore_pmu *pmus;
	struct intel_uncore_ops *ops;
	struct uncore_event_desc *event_descs;
	const struct attribute_group *attr_groups[4];
	struct pmu *pmu; /* for custom pmu ops */
};

#define pmu_group attr_groups[0]
#define format_group attr_groups[1]
#define events_group attr_groups[2]

struct intel_uncore_ops {
	void (*init_box)(struct intel_uncore_box *);
	void (*exit_box)(struct intel_uncore_box *);
	void (*disable_box)(struct intel_uncore_box *);
	void (*enable_box)(struct intel_uncore_box *);
	void (*disable_event)(struct intel_uncore_box *, struct perf_event *);
	void (*enable_event)(struct intel_uncore_box *, struct perf_event *);
	u64 (*read_counter)(struct intel_uncore_box *, struct perf_event *);
	int (*hw_config)(struct intel_uncore_box *, struct perf_event *);
	struct event_constraint *(*get_constraint)(struct intel_uncore_box *,
						   struct perf_event *);
	void (*put_constraint)(struct intel_uncore_box *, struct perf_event *);
};

struct intel_uncore_pmu {
	struct pmu			pmu;
	char				name[UNCORE_PMU_NAME_LEN];
	int				pmu_idx;
	int				func_id;
	bool				registered;
	atomic_t			activeboxes;
	struct intel_uncore_type	*type;
	struct intel_uncore_box		**boxes;
};

struct intel_uncore_extra_reg {
	raw_spinlock_t lock;
	u64 config, config1, config2;
	atomic_t ref;
};

struct intel_uncore_box {
	int pci_phys_id;
	int pkgid;
	int n_active;	/* number of active events */
	int n_events;
	int cpu;	/* cpu to collect events */
	unsigned long flags;
	atomic_t refcnt;
	struct perf_event *events[UNCORE_PMC_IDX_MAX];
	struct perf_event *event_list[UNCORE_PMC_IDX_MAX];
	struct event_constraint *event_constraint[UNCORE_PMC_IDX_MAX];
	unsigned long active_mask[BITS_TO_LONGS(UNCORE_PMC_IDX_MAX)];
	u64 tags[UNCORE_PMC_IDX_MAX];
	struct pci_dev *pci_dev;
	struct intel_uncore_pmu *pmu;
	u64 hrtimer_duration; /* hrtimer timeout for this box */
	struct hrtimer hrtimer;
	struct list_head list;
	struct list_head active_list;
	void *io_addr;
	struct intel_uncore_extra_reg shared_regs[0];
};

#define UNCORE_BOX_FLAG_INITIATED	0

struct uncore_event_desc {
	struct kobj_attribute attr;
	const char *config;
};

struct pci2phy_map {
	struct list_head list;
	int segment;
	int pbus_to_physid[256];
};

struct pci2phy_map *__find_pci2phy_map(int segment);

ssize_t uncore_event_show(struct kobject *kobj,
			  struct kobj_attribute *attr, char *buf);

#define INTEL_UNCORE_EVENT_DESC(_name, _config)			\
{								\
	.attr	= __ATTR(_name, 0444, uncore_event_show, NULL),	\
	.config	= _config,					\
}

#define DEFINE_UNCORE_FORMAT_ATTR(_var, _name, _format)			\
static ssize_t __uncore_##_var##_show(struct kobject *kobj,		\
				struct kobj_attribute *attr,		\
				char *page)				\
{									\
	BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE);			\
	return sprintf(page, _format "\n");				\
}									\
static struct kobj_attribute format_attr_##_var =			\
	__ATTR(_name, 0444, __uncore_##_var##_show, NULL)

static inline unsigned uncore_pci_box_ctl(struct intel_uncore_box *box)
{
	return box->pmu->type->box_ctl;
}

static inline unsigned uncore_pci_fixed_ctl(struct intel_uncore_box *box)
{
	return box->pmu->type->fixed_ctl;
}

static inline unsigned uncore_pci_fixed_ctr(struct intel_uncore_box *box)
{
	return box->pmu->type->fixed_ctr;
}

static inline
unsigned uncore_pci_event_ctl(struct intel_uncore_box *box, int idx)
{
	return idx * 4 + box->pmu->type->event_ctl;
}

static inline
unsigned uncore_pci_perf_ctr(struct intel_uncore_box *box, int idx)
{
	return idx * 8 + box->pmu->type->perf_ctr;
}

static inline unsigned uncore_msr_box_offset(struct intel_uncore_box *box)
{
	struct intel_uncore_pmu *pmu = box->pmu;
	return pmu->type->msr_offsets ?
		pmu->type->msr_offsets[pmu->pmu_idx] :
		pmu->type->msr_offset * pmu->pmu_idx;
}

static inline unsigned uncore_msr_box_ctl(struct intel_uncore_box *box)
{
	if (!box->pmu->type->box_ctl)
		return 0;
	return box->pmu->type->box_ctl + uncore_msr_box_offset(box);
}

static inline unsigned uncore_msr_fixed_ctl(struct intel_uncore_box *box)
{
	if (!box->pmu->type->fixed_ctl)
		return 0;
	return box->pmu->type->fixed_ctl + uncore_msr_box_offset(box);
}

static inline unsigned uncore_msr_fixed_ctr(struct intel_uncore_box *box)
{
	return box->pmu->type->fixed_ctr + uncore_msr_box_offset(box);
}

static inline
unsigned uncore_msr_event_ctl(struct intel_uncore_box *box, int idx)
{
	return box->pmu->type->event_ctl +
		(box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
		uncore_msr_box_offset(box);
}

static inline
unsigned uncore_msr_perf_ctr(struct intel_uncore_box *box, int idx)
{
	return box->pmu->type->perf_ctr +
		(box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
		uncore_msr_box_offset(box);
}

static inline
unsigned uncore_fixed_ctl(struct intel_uncore_box *box)
{
	if (box->pci_dev)
		return uncore_pci_fixed_ctl(box);
	else
		return uncore_msr_fixed_ctl(box);
}

static inline
unsigned uncore_fixed_ctr(struct intel_uncore_box *box)
{
	if (box->pci_dev)
		return uncore_pci_fixed_ctr(box);
	else
		return uncore_msr_fixed_ctr(box);
}

static inline
unsigned uncore_event_ctl(struct intel_uncore_box *box, int idx)
{
	if (box->pci_dev)
		return uncore_pci_event_ctl(box, idx);
	else
		return uncore_msr_event_ctl(box, idx);
}

static inline
unsigned uncore_perf_ctr(struct intel_uncore_box *box, int idx)
{
	if (box->pci_dev)
		return uncore_pci_perf_ctr(box, idx);
	else
		return uncore_msr_perf_ctr(box, idx);
}

static inline int uncore_perf_ctr_bits(struct intel_uncore_box *box)
{
	return box->pmu->type->perf_ctr_bits;
}

static inline int uncore_fixed_ctr_bits(struct intel_uncore_box *box)
{
	return box->pmu->type->fixed_ctr_bits;
}

static inline int uncore_num_counters(struct intel_uncore_box *box)
{
	return box->pmu->type->num_counters;
}

static inline void uncore_disable_box(struct intel_uncore_box *box)
{
	if (box->pmu->type->ops->disable_box)
		box->pmu->type->ops->disable_box(box);
}

static inline void uncore_enable_box(struct intel_uncore_box *box)
{
	if (box->pmu->type->ops->enable_box)
		box->pmu->type->ops->enable_box(box);
}

static inline void uncore_disable_event(struct intel_uncore_box *box,
				struct perf_event *event)
{
	box->pmu->type->ops->disable_event(box, event);
}

static inline void uncore_enable_event(struct intel_uncore_box *box,
				struct perf_event *event)
{
	box->pmu->type->ops->enable_event(box, event);
}

static inline u64 uncore_read_counter(struct intel_uncore_box *box,
				struct perf_event *event)
{
	return box->pmu->type->ops->read_counter(box, event);
}

static inline void uncore_box_init(struct intel_uncore_box *box)
{
	if (!test_and_set_bit(UNCORE_BOX_FLAG_INITIATED, &box->flags)) {
		if (box->pmu->type->ops->init_box)
			box->pmu->type->ops->init_box(box);
	}
}

static inline void uncore_box_exit(struct intel_uncore_box *box)
{
	if (test_and_clear_bit(UNCORE_BOX_FLAG_INITIATED, &box->flags)) {
		if (box->pmu->type->ops->exit_box)
			box->pmu->type->ops->exit_box(box);
	}
}

static inline bool uncore_box_is_fake(struct intel_uncore_box *box)
{
	return (box->pkgid < 0);
}

static inline struct intel_uncore_pmu *uncore_event_to_pmu(struct perf_event *event)
{
	return container_of(event->pmu, struct intel_uncore_pmu, pmu);
}

static inline struct intel_uncore_box *uncore_event_to_box(struct perf_event *event)
{
	return event->pmu_private;
}

struct intel_uncore_box *uncore_pmu_to_box(struct intel_uncore_pmu *pmu, int cpu);
u64 uncore_msr_read_counter(struct intel_uncore_box *box, struct perf_event *event);
void uncore_pmu_start_hrtimer(struct intel_uncore_box *box);
void uncore_pmu_cancel_hrtimer(struct intel_uncore_box *box);
void uncore_pmu_event_read(struct perf_event *event);
void uncore_perf_event_update(struct intel_uncore_box *box, struct perf_event *event);
struct event_constraint *
uncore_get_constraint(struct intel_uncore_box *box, struct perf_event *event);
void uncore_put_constraint(struct intel_uncore_box *box, struct perf_event *event);
u64 uncore_shared_reg_config(struct intel_uncore_box *box, int idx);

extern struct intel_uncore_type **uncore_msr_uncores;
extern struct intel_uncore_type **uncore_pci_uncores;
extern struct pci_driver *uncore_pci_driver;
extern raw_spinlock_t pci2phy_map_lock;
extern struct list_head pci2phy_map_head;
extern struct pci_extra_dev *uncore_extra_pci_dev;
extern struct event_constraint uncore_constraint_empty;

/* perf_event_intel_uncore_snb.c */
int snb_uncore_pci_init(void);
int ivb_uncore_pci_init(void);
int hsw_uncore_pci_init(void);
int bdw_uncore_pci_init(void);
int skl_uncore_pci_init(void);
void snb_uncore_cpu_init(void);
void nhm_uncore_cpu_init(void);
void skl_uncore_cpu_init(void);
int snb_pci2phy_map_init(int devid);

/* perf_event_intel_uncore_snbep.c */
int snbep_uncore_pci_init(void);
void snbep_uncore_cpu_init(void);
int ivbep_uncore_pci_init(void);
void ivbep_uncore_cpu_init(void);
int hswep_uncore_pci_init(void);
void hswep_uncore_cpu_init(void);
int bdx_uncore_pci_init(void);
void bdx_uncore_cpu_init(void);
int knl_uncore_pci_init(void);
void knl_uncore_cpu_init(void);

/* perf_event_intel_uncore_nhmex.c */
void nhmex_uncore_cpu_init(void);
Commit	Line	Data
087bfbb0	1	#include <linux/slab.h>
14371cce	2	#include <linux/pci.h>
6f6e1516 IM	3	#include <asm/apicdef.h>
6f6e1516 IM	4
087bfbb0	5	#include <linux/perf_event.h>
27f6d22b	6	#include "../perf_event.h"
087bfbb0 YZ	7
087bfbb0 YZ	8	#define UNCORE_PMU_NAME_LEN 32
7740dfc0	9	#define UNCORE_PMU_HRTIMER_INTERVAL (60LL * NSEC_PER_SEC)
ced2efb0	10	#define UNCORE_SNB_IMC_HRTIMER_INTERVAL (5ULL * NSEC_PER_SEC)
087bfbb0	11
eca26c99	12	#define UNCORE_FIXED_EVENT 0xff
087bfbb0 YZ	13	#define UNCORE_PMC_IDX_MAX_GENERIC 8
	14	#define UNCORE_PMC_IDX_FIXED UNCORE_PMC_IDX_MAX_GENERIC
	15	#define UNCORE_PMC_IDX_MAX (UNCORE_PMC_IDX_FIXED + 1)
	16
a54fa079 KL	17	#define UNCORE_PCI_DEV_FULL_DATA(dev, func, type, idx) \
a54fa079 KL	18	((dev << 24) \| (func << 16) \| (type << 8) \| idx)
899396cf	19	#define UNCORE_PCI_DEV_DATA(type, idx) ((type << 8) \| idx)
a54fa079 KL	20	#define UNCORE_PCI_DEV_DEV(data) ((data >> 24) & 0xff)
a54fa079 KL	21	#define UNCORE_PCI_DEV_FUNC(data) ((data >> 16) & 0xff)
899396cf YZ	22	#define UNCORE_PCI_DEV_TYPE(data) ((data >> 8) & 0xff)
	23	#define UNCORE_PCI_DEV_IDX(data) (data & 0xff)
	24	#define UNCORE_EXTRA_PCI_DEV 0xff
5306c31c	25	#define UNCORE_EXTRA_PCI_DEV_MAX 3
899396cf	26
087bfbb0 YZ	27	#define UNCORE_EVENT_CONSTRAINT(c, n) EVENT_CONSTRAINT(c, n, 0xff)
087bfbb0 YZ	28
cf6d445f TG	29	struct pci_extra_dev {
	30	struct pci_dev *dev[UNCORE_EXTRA_PCI_DEV_MAX];
	31	};
	32
087bfbb0 YZ	33	struct intel_uncore_ops;
	34	struct intel_uncore_pmu;
	35	struct intel_uncore_box;
	36	struct uncore_event_desc;
	37
	38	struct intel_uncore_type {
	39	const char *name;
	40	int num_counters;
	41	int num_boxes;
	42	int perf_ctr_bits;
	43	int fixed_ctr_bits;
087bfbb0 YZ	44	unsigned perf_ctr;
	45	unsigned event_ctl;
	46	unsigned event_mask;
	47	unsigned fixed_ctr;
	48	unsigned fixed_ctl;
	49	unsigned box_ctl;
	50	unsigned msr_offset;
6a67943a YZ	51	unsigned num_shared_regs:8;
6a67943a YZ	52	unsigned single_fixed:1;
254298c7	53	unsigned pair_ctr_ctl:1;
cb37af77	54	unsigned *msr_offsets;
087bfbb0 YZ	55	struct event_constraint unconstrainted;
	56	struct event_constraint *constraints;
	57	struct intel_uncore_pmu *pmus;
	58	struct intel_uncore_ops *ops;
	59	struct uncore_event_desc *event_descs;
314d9f63	60	const struct attribute_group *attr_groups[4];
d64b25b6	61	struct pmu pmu; / for custom pmu ops */
087bfbb0 YZ	62	};
087bfbb0 YZ	63
314d9f63 YZ	64	#define pmu_group attr_groups[0]
	65	#define format_group attr_groups[1]
	66	#define events_group attr_groups[2]
087bfbb0 YZ	67
	68	struct intel_uncore_ops {
	69	void (init_box)(struct intel_uncore_box );
a46195f1	70	void (exit_box)(struct intel_uncore_box );
087bfbb0 YZ	71	void (disable_box)(struct intel_uncore_box );
	72	void (enable_box)(struct intel_uncore_box );
	73	void (disable_event)(struct intel_uncore_box , struct perf_event *);
	74	void (enable_event)(struct intel_uncore_box , struct perf_event *);
	75	u64 (read_counter)(struct intel_uncore_box , struct perf_event *);
6a67943a YZ	76	int (hw_config)(struct intel_uncore_box , struct perf_event *);
	77	struct event_constraint (get_constraint)(struct intel_uncore_box *,
	78	struct perf_event *);
	79	void (put_constraint)(struct intel_uncore_box , struct perf_event *);
087bfbb0 YZ	80	};
	81
	82	struct intel_uncore_pmu {
4f089678 TG	83	struct pmu pmu;
	84	char name[UNCORE_PMU_NAME_LEN];
	85	int pmu_idx;
	86	int func_id;
	87	bool registered;
cf6d445f	88	atomic_t activeboxes;
4f089678	89	struct intel_uncore_type *type;
cf6d445f	90	struct intel_uncore_box **boxes;
087bfbb0 YZ	91	};
087bfbb0 YZ	92
6a67943a YZ	93	struct intel_uncore_extra_reg {
6a67943a YZ	94	raw_spinlock_t lock;
254298c7	95	u64 config, config1, config2;
6a67943a YZ	96	atomic_t ref;
	97	};
	98
087bfbb0	99	struct intel_uncore_box {
cf6d445f TG	100	int pci_phys_id;
cf6d445f TG	101	int pkgid;
087bfbb0 YZ	102	int n_active; /* number of active events */
	103	int n_events;
	104	int cpu; /* cpu to collect events */
	105	unsigned long flags;
	106	atomic_t refcnt;
	107	struct perf_event *events[UNCORE_PMC_IDX_MAX];
	108	struct perf_event *event_list[UNCORE_PMC_IDX_MAX];
b371b594	109	struct event_constraint *event_constraint[UNCORE_PMC_IDX_MAX];
087bfbb0 YZ	110	unsigned long active_mask[BITS_TO_LONGS(UNCORE_PMC_IDX_MAX)];
087bfbb0 YZ	111	u64 tags[UNCORE_PMC_IDX_MAX];
14371cce	112	struct pci_dev *pci_dev;
087bfbb0	113	struct intel_uncore_pmu *pmu;
79859cce	114	u64 hrtimer_duration; /* hrtimer timeout for this box */
087bfbb0 YZ	115	struct hrtimer hrtimer;
087bfbb0 YZ	116	struct list_head list;
ced2efb0	117	struct list_head active_list;
b9e1ab6d	118	void *io_addr;
6a67943a	119	struct intel_uncore_extra_reg shared_regs[0];
087bfbb0 YZ	120	};
	121
	122	#define UNCORE_BOX_FLAG_INITIATED 0
	123
	124	struct uncore_event_desc {
	125	struct kobj_attribute attr;
	126	const char *config;
	127	};
	128
712df65c TI	129	struct pci2phy_map {
	130	struct list_head list;
	131	int segment;
	132	int pbus_to_physid[256];
	133	};
	134
712df65c TI	135	struct pci2phy_map *__find_pci2phy_map(int segment);
712df65c TI	136
514b2346 YZ	137	ssize_t uncore_event_show(struct kobject *kobj,
	138	struct kobj_attribute attr, char buf);
	139
087bfbb0 YZ	140	#define INTEL_UNCORE_EVENT_DESC(_name, _config) \
	141	{ \
	142	.attr = __ATTR(_name, 0444, uncore_event_show, NULL), \
	143	.config = _config, \
	144	}
	145
	146	#define DEFINE_UNCORE_FORMAT_ATTR(_var, _name, _format) \
	147	static ssize_t __uncore_##_var##_show(struct kobject *kobj, \
	148	struct kobj_attribute *attr, \
	149	char *page) \
	150	{ \
	151	BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE); \
	152	return sprintf(page, _format "\n"); \
	153	} \
	154	static struct kobj_attribute format_attr_##_var = \
	155	__ATTR(_name, 0444, __uncore_##_var##_show, NULL)
	156
14371cce YZ	157	static inline unsigned uncore_pci_box_ctl(struct intel_uncore_box *box)
	158	{
	159	return box->pmu->type->box_ctl;
	160	}
	161
	162	static inline unsigned uncore_pci_fixed_ctl(struct intel_uncore_box *box)
	163	{
	164	return box->pmu->type->fixed_ctl;
	165	}
	166
	167	static inline unsigned uncore_pci_fixed_ctr(struct intel_uncore_box *box)
	168	{
	169	return box->pmu->type->fixed_ctr;
	170	}
	171
	172	static inline
	173	unsigned uncore_pci_event_ctl(struct intel_uncore_box *box, int idx)
	174	{
	175	return idx * 4 + box->pmu->type->event_ctl;
	176	}
	177
	178	static inline
	179	unsigned uncore_pci_perf_ctr(struct intel_uncore_box *box, int idx)
	180	{
	181	return idx * 8 + box->pmu->type->perf_ctr;
	182	}
	183
cb37af77 YZ	184	static inline unsigned uncore_msr_box_offset(struct intel_uncore_box *box)
	185	{
	186	struct intel_uncore_pmu *pmu = box->pmu;
	187	return pmu->type->msr_offsets ?
	188	pmu->type->msr_offsets[pmu->pmu_idx] :
	189	pmu->type->msr_offset * pmu->pmu_idx;
	190	}
	191
	192	static inline unsigned uncore_msr_box_ctl(struct intel_uncore_box *box)
087bfbb0 YZ	193	{
	194	if (!box->pmu->type->box_ctl)
	195	return 0;
cb37af77	196	return box->pmu->type->box_ctl + uncore_msr_box_offset(box);
087bfbb0 YZ	197	}
087bfbb0 YZ	198
cb37af77	199	static inline unsigned uncore_msr_fixed_ctl(struct intel_uncore_box *box)
087bfbb0 YZ	200	{
	201	if (!box->pmu->type->fixed_ctl)
	202	return 0;
cb37af77	203	return box->pmu->type->fixed_ctl + uncore_msr_box_offset(box);
087bfbb0 YZ	204	}
087bfbb0 YZ	205
cb37af77	206	static inline unsigned uncore_msr_fixed_ctr(struct intel_uncore_box *box)
087bfbb0	207	{
cb37af77	208	return box->pmu->type->fixed_ctr + uncore_msr_box_offset(box);
087bfbb0 YZ	209	}
	210
	211	static inline
	212	unsigned uncore_msr_event_ctl(struct intel_uncore_box *box, int idx)
	213	{
254298c7 YZ	214	return box->pmu->type->event_ctl +
254298c7 YZ	215	(box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
cb37af77	216	uncore_msr_box_offset(box);
087bfbb0 YZ	217	}
	218
	219	static inline
	220	unsigned uncore_msr_perf_ctr(struct intel_uncore_box *box, int idx)
	221	{
254298c7 YZ	222	return box->pmu->type->perf_ctr +
254298c7 YZ	223	(box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
cb37af77	224	uncore_msr_box_offset(box);
087bfbb0 YZ	225	}
087bfbb0 YZ	226
14371cce YZ	227	static inline
	228	unsigned uncore_fixed_ctl(struct intel_uncore_box *box)
	229	{
	230	if (box->pci_dev)
	231	return uncore_pci_fixed_ctl(box);
	232	else
	233	return uncore_msr_fixed_ctl(box);
	234	}
	235
	236	static inline
	237	unsigned uncore_fixed_ctr(struct intel_uncore_box *box)
	238	{
	239	if (box->pci_dev)
	240	return uncore_pci_fixed_ctr(box);
	241	else
	242	return uncore_msr_fixed_ctr(box);
	243	}
	244
	245	static inline
	246	unsigned uncore_event_ctl(struct intel_uncore_box *box, int idx)
	247	{
	248	if (box->pci_dev)
	249	return uncore_pci_event_ctl(box, idx);
	250	else
	251	return uncore_msr_event_ctl(box, idx);
	252	}
	253
	254	static inline
	255	unsigned uncore_perf_ctr(struct intel_uncore_box *box, int idx)
	256	{
	257	if (box->pci_dev)
	258	return uncore_pci_perf_ctr(box, idx);
	259	else
	260	return uncore_msr_perf_ctr(box, idx);
	261	}
	262
087bfbb0 YZ	263	static inline int uncore_perf_ctr_bits(struct intel_uncore_box *box)
	264	{
	265	return box->pmu->type->perf_ctr_bits;
	266	}
	267
	268	static inline int uncore_fixed_ctr_bits(struct intel_uncore_box *box)
	269	{
	270	return box->pmu->type->fixed_ctr_bits;
	271	}
	272
	273	static inline int uncore_num_counters(struct intel_uncore_box *box)
	274	{
	275	return box->pmu->type->num_counters;
	276	}
	277
	278	static inline void uncore_disable_box(struct intel_uncore_box *box)
	279	{
	280	if (box->pmu->type->ops->disable_box)
	281	box->pmu->type->ops->disable_box(box);
	282	}
	283
	284	static inline void uncore_enable_box(struct intel_uncore_box *box)
	285	{
	286	if (box->pmu->type->ops->enable_box)
	287	box->pmu->type->ops->enable_box(box);
	288	}
	289
	290	static inline void uncore_disable_event(struct intel_uncore_box *box,
	291	struct perf_event *event)
	292	{
	293	box->pmu->type->ops->disable_event(box, event);
	294	}
	295
	296	static inline void uncore_enable_event(struct intel_uncore_box *box,
	297	struct perf_event *event)
	298	{
	299	box->pmu->type->ops->enable_event(box, event);
	300	}
	301
	302	static inline u64 uncore_read_counter(struct intel_uncore_box *box,
	303	struct perf_event *event)
	304	{
	305	return box->pmu->type->ops->read_counter(box, event);
	306	}
	307
15c12479 IM	308	static inline void uncore_box_init(struct intel_uncore_box *box)
	309	{
	310	if (!test_and_set_bit(UNCORE_BOX_FLAG_INITIATED, &box->flags)) {
	311	if (box->pmu->type->ops->init_box)
	312	box->pmu->type->ops->init_box(box);
	313	}
	314	}
	315
a46195f1 TG	316	static inline void uncore_box_exit(struct intel_uncore_box *box)
	317	{
	318	if (test_and_clear_bit(UNCORE_BOX_FLAG_INITIATED, &box->flags)) {
	319	if (box->pmu->type->ops->exit_box)
	320	box->pmu->type->ops->exit_box(box);
	321	}
	322	}
	323
254298c7 YZ	324	static inline bool uncore_box_is_fake(struct intel_uncore_box *box)
254298c7 YZ	325	{
cf6d445f	326	return (box->pkgid < 0);
254298c7	327	}
514b2346	328
1f2569fa TG	329	static inline struct intel_uncore_pmu uncore_event_to_pmu(struct perf_event event)
	330	{
	331	return container_of(event->pmu, struct intel_uncore_pmu, pmu);
	332	}
	333
	334	static inline struct intel_uncore_box uncore_event_to_box(struct perf_event event)
	335	{
	336	return event->pmu_private;
	337	}
	338
514b2346	339	struct intel_uncore_box uncore_pmu_to_box(struct intel_uncore_pmu pmu, int cpu);
514b2346 YZ	340	u64 uncore_msr_read_counter(struct intel_uncore_box box, struct perf_event event);
	341	void uncore_pmu_start_hrtimer(struct intel_uncore_box *box);
	342	void uncore_pmu_cancel_hrtimer(struct intel_uncore_box *box);
	343	void uncore_pmu_event_read(struct perf_event *event);
	344	void uncore_perf_event_update(struct intel_uncore_box box, struct perf_event event);
	345	struct event_constraint *
	346	uncore_get_constraint(struct intel_uncore_box box, struct perf_event event);
	347	void uncore_put_constraint(struct intel_uncore_box box, struct perf_event event);
	348	u64 uncore_shared_reg_config(struct intel_uncore_box *box, int idx);
	349
	350	extern struct intel_uncore_type **uncore_msr_uncores;
	351	extern struct intel_uncore_type **uncore_pci_uncores;
	352	extern struct pci_driver *uncore_pci_driver;
712df65c TI	353	extern raw_spinlock_t pci2phy_map_lock;
712df65c TI	354	extern struct list_head pci2phy_map_head;
cf6d445f	355	extern struct pci_extra_dev *uncore_extra_pci_dev;
514b2346	356	extern struct event_constraint uncore_constraint_empty;
92807ffd YZ	357
	358	/* perf_event_intel_uncore_snb.c */
	359	int snb_uncore_pci_init(void);
	360	int ivb_uncore_pci_init(void);
	361	int hsw_uncore_pci_init(void);
a41f3c8c	362	int bdw_uncore_pci_init(void);
0e1eb0a1	363	int skl_uncore_pci_init(void);
92807ffd YZ	364	void snb_uncore_cpu_init(void);
92807ffd YZ	365	void nhm_uncore_cpu_init(void);
46866b59	366	void skl_uncore_cpu_init(void);
77af0037	367	int snb_pci2phy_map_init(int devid);
8268fdfc YZ	368
	369	/* perf_event_intel_uncore_snbep.c */
	370	int snbep_uncore_pci_init(void);
	371	void snbep_uncore_cpu_init(void);
ddcd0973 PZ	372	int ivbep_uncore_pci_init(void);
ddcd0973 PZ	373	void ivbep_uncore_cpu_init(void);
e735b9db YZ	374	int hswep_uncore_pci_init(void);
e735b9db YZ	375	void hswep_uncore_cpu_init(void);
070e9887 KL	376	int bdx_uncore_pci_init(void);
070e9887 KL	377	void bdx_uncore_cpu_init(void);
77af0037 HC	378	int knl_uncore_pci_init(void);
77af0037 HC	379	void knl_uncore_cpu_init(void);
c1e46580 YZ	380
	381	/* perf_event_intel_uncore_nhmex.c */
	382	void nhmex_uncore_cpu_init(void);