[deliverable/linux.git] / arch / x86 / include / asm / acpi.h

#ifndef _ASM_X86_ACPI_H
#define _ASM_X86_ACPI_H

/*
 *  Copyright (C) 2001 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
 *  Copyright (C) 2001 Patrick Mochel <mochel@osdl.org>
 *
 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 */
#include <acpi/pdc_intel.h>

#include <asm/numa.h>
#include <asm/fixmap.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/mpspec.h>
#include <asm/realmode.h>

#ifdef CONFIG_ACPI
extern int acpi_lapic;
extern int acpi_ioapic;
extern int acpi_noirq;
extern int acpi_strict;
extern int acpi_disabled;
extern int acpi_pci_disabled;
extern int acpi_skip_timer_override;
extern int acpi_use_timer_override;
extern int acpi_fix_pin2_polarity;
extern int acpi_disable_cmcff;

extern u8 acpi_sci_flags;
extern int acpi_sci_override_gsi;
void acpi_pic_sci_set_trigger(unsigned int, u16);

extern int (*__acpi_register_gsi)(struct device *dev, u32 gsi,
				  int trigger, int polarity);
extern void (*__acpi_unregister_gsi)(u32 gsi);

static inline void disable_acpi(void)
{
	acpi_disabled = 1;
	acpi_pci_disabled = 1;
	acpi_noirq = 1;
}

extern int acpi_gsi_to_irq(u32 gsi, unsigned int *irq);

static inline void acpi_noirq_set(void) { acpi_noirq = 1; }
static inline void acpi_disable_pci(void)
{
	acpi_pci_disabled = 1;
	acpi_noirq_set();
}

/* Low-level suspend routine. */
extern int (*acpi_suspend_lowlevel)(void);

/* Physical address to resume after wakeup */
#define acpi_wakeup_address ((unsigned long)(real_mode_header->wakeup_start))

/*
 * Check if the CPU can handle C2 and deeper
 */
static inline unsigned int acpi_processor_cstate_check(unsigned int max_cstate)
{
	/*
	 * Early models (<=5) of AMD Opterons are not supposed to go into
	 * C2 state.
	 *
	 * Steppings 0x0A and later are good
	 */
	if (boot_cpu_data.x86 == 0x0F &&
	    boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
	    boot_cpu_data.x86_model <= 0x05 &&
	    boot_cpu_data.x86_mask < 0x0A)
		return 1;
	else if (amd_e400_c1e_detected)
		return 1;
	else
		return max_cstate;
}

static inline bool arch_has_acpi_pdc(void)
{
	struct cpuinfo_x86 *c = &cpu_data(0);
	return (c->x86_vendor == X86_VENDOR_INTEL ||
		c->x86_vendor == X86_VENDOR_CENTAUR);
}

static inline void arch_acpi_set_pdc_bits(u32 *buf)
{
	struct cpuinfo_x86 *c = &cpu_data(0);

	buf[2] |= ACPI_PDC_C_CAPABILITY_SMP;

	if (cpu_has(c, X86_FEATURE_EST))
		buf[2] |= ACPI_PDC_EST_CAPABILITY_SWSMP;

	if (cpu_has(c, X86_FEATURE_ACPI))
		buf[2] |= ACPI_PDC_T_FFH;

	/*
	 * If mwait/monitor is unsupported, C2/C3_FFH will be disabled
	 */
	if (!cpu_has(c, X86_FEATURE_MWAIT))
		buf[2] &= ~(ACPI_PDC_C_C2C3_FFH);
}

static inline bool acpi_has_cpu_in_madt(void)
{
	return !!acpi_lapic;
}

#else /* !CONFIG_ACPI */

#define acpi_lapic 0
#define acpi_ioapic 0
#define acpi_disable_cmcff 0
static inline void acpi_noirq_set(void) { }
static inline void acpi_disable_pci(void) { }
static inline void disable_acpi(void) { }

#endif /* !CONFIG_ACPI */

#define ARCH_HAS_POWER_INIT	1

#ifdef CONFIG_ACPI_NUMA
extern int acpi_numa;
extern int x86_acpi_numa_init(void);
#endif /* CONFIG_ACPI_NUMA */

#define acpi_unlazy_tlb(x)	leave_mm(x)

#endif /* _ASM_X86_ACPI_H */
Commit	Line	Data
1965aae3 PA	1	#ifndef _ASM_X86_ACPI_H
1965aae3 PA	2	#define _ASM_X86_ACPI_H
c1c30634	3
0b80fc72 TG	4	/*
	5	* Copyright (C) 2001 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
	6	* Copyright (C) 2001 Patrick Mochel <mochel@osdl.org>
	7	*
	8	* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; either version 2 of the License, or
	13	* (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	23	*
	24	* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
	25	*/
	26	#include <acpi/pdc_intel.h>
c1c30634	27
0b80fc72	28	#include <asm/numa.h>
bee7f9c8	29	#include <asm/fixmap.h>
c1c30634	30	#include <asm/processor.h>
bde6f5f5	31	#include <asm/mmu.h>
4c1cbafb	32	#include <asm/mpspec.h>
319b6ffc	33	#include <asm/realmode.h>
c1c30634	34
0b80fc72 TG	35	#ifdef CONFIG_ACPI
	36	extern int acpi_lapic;
	37	extern int acpi_ioapic;
	38	extern int acpi_noirq;
	39	extern int acpi_strict;
	40	extern int acpi_disabled;
0b80fc72 TG	41	extern int acpi_pci_disabled;
	42	extern int acpi_skip_timer_override;
	43	extern int acpi_use_timer_override;
7f74f8f2	44	extern int acpi_fix_pin2_polarity;
9ad95879	45	extern int acpi_disable_cmcff;
0b80fc72	46
6697c052 HH	47	extern u8 acpi_sci_flags;
	48	extern int acpi_sci_override_gsi;
	49	void acpi_pic_sci_set_trigger(unsigned int, u16);
	50
90f6881e JF	51	extern int (__acpi_register_gsi)(struct device dev, u32 gsi,
90f6881e JF	52	int trigger, int polarity);
8abb850a	53	extern void (*__acpi_unregister_gsi)(u32 gsi);
90f6881e	54
0b80fc72 TG	55	static inline void disable_acpi(void)
	56	{
	57	acpi_disabled = 1;
0b80fc72 TG	58	acpi_pci_disabled = 1;
	59	acpi_noirq = 1;
	60	}
	61
0b80fc72 TG	62	extern int acpi_gsi_to_irq(u32 gsi, unsigned int *irq);
	63
	64	static inline void acpi_noirq_set(void) { acpi_noirq = 1; }
	65	static inline void acpi_disable_pci(void)
	66	{
	67	acpi_pci_disabled = 1;
	68	acpi_noirq_set();
	69	}
0b80fc72	70
f1a2003e	71	/* Low-level suspend routine. */
d6a77ead	72	extern int (*acpi_suspend_lowlevel)(void);
0b80fc72	73
319b6ffc PA	74	/* Physical address to resume after wakeup */
319b6ffc PA	75	#define acpi_wakeup_address ((unsigned long)(real_mode_header->wakeup_start))
0b80fc72	76
c1c30634 AS	77	/*
	78	* Check if the CPU can handle C2 and deeper
	79	*/
	80	static inline unsigned int acpi_processor_cstate_check(unsigned int max_cstate)
	81	{
	82	/*
	83	* Early models (<=5) of AMD Opterons are not supposed to go into
	84	* C2 state.
	85	*
	86	* Steppings 0x0A and later are good
	87	*/
	88	if (boot_cpu_data.x86 == 0x0F &&
	89	boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
	90	boot_cpu_data.x86_model <= 0x05 &&
	91	boot_cpu_data.x86_mask < 0x0A)
	92	return 1;
02c68a02	93	else if (amd_e400_c1e_detected)
a8d68290	94	return 1;
c1c30634 AS	95	else
	96	return max_cstate;
	97	}
	98
1d9cb470 AC	99	static inline bool arch_has_acpi_pdc(void)
	100	{
	101	struct cpuinfo_x86 *c = &cpu_data(0);
	102	return (c->x86_vendor == X86_VENDOR_INTEL \|\|
	103	c->x86_vendor == X86_VENDOR_CENTAUR);
	104	}
	105
6c5807d7 AC	106	static inline void arch_acpi_set_pdc_bits(u32 *buf)
	107	{
	108	struct cpuinfo_x86 *c = &cpu_data(0);
	109
	110	buf[2] \|= ACPI_PDC_C_CAPABILITY_SMP;
	111
	112	if (cpu_has(c, X86_FEATURE_EST))
	113	buf[2] \|= ACPI_PDC_EST_CAPABILITY_SWSMP;
	114
	115	if (cpu_has(c, X86_FEATURE_ACPI))
	116	buf[2] \|= ACPI_PDC_T_FFH;
	117
	118	/*
	119	* If mwait/monitor is unsupported, C2/C3_FFH will be disabled
	120	*/
	121	if (!cpu_has(c, X86_FEATURE_MWAIT))
	122	buf[2] &= ~(ACPI_PDC_C_C2C3_FFH);
	123	}
	124
b50154d5 GG	125	static inline bool acpi_has_cpu_in_madt(void)
	126	{
	127	return !!acpi_lapic;
	128	}
	129
0b80fc72 TG	130	#else /* !CONFIG_ACPI */
	131
	132	#define acpi_lapic 0
	133	#define acpi_ioapic 0
9ad95879	134	#define acpi_disable_cmcff 0
0b80fc72 TG	135	static inline void acpi_noirq_set(void) { }
	136	static inline void acpi_disable_pci(void) { }
	137	static inline void disable_acpi(void) { }
	138
	139	#endif /* !CONFIG_ACPI */
	140
	141	#define ARCH_HAS_POWER_INIT 1
	142
0b80fc72 TG	143	#ifdef CONFIG_ACPI_NUMA
0b80fc72 TG	144	extern int acpi_numa;
a9aec56a	145	extern int x86_acpi_numa_init(void);
4e76f4e6	146	#endif /* CONFIG_ACPI_NUMA */
0b80fc72	147
bde6f5f5 VP	148	#define acpi_unlazy_tlb(x) leave_mm(x)
bde6f5f5 VP	149
1965aae3	150	#endif /* _ASM_X86_ACPI_H */