[deliverable/linux.git] / arch / x86 / include / asm / alternative.h

#ifndef _ASM_X86_ALTERNATIVE_H
#define _ASM_X86_ALTERNATIVE_H

#include <linux/types.h>
#include <linux/stddef.h>
#include <linux/stringify.h>
#include <asm/asm.h>

/*
 * Alternative inline assembly for SMP.
 *
 * The LOCK_PREFIX macro defined here replaces the LOCK and
 * LOCK_PREFIX macros used everywhere in the source tree.
 *
 * SMP alternatives use the same data structures as the other
 * alternatives and the X86_FEATURE_UP flag to indicate the case of a
 * UP system running a SMP kernel.  The existing apply_alternatives()
 * works fine for patching a SMP kernel for UP.
 *
 * The SMP alternative tables can be kept after boot and contain both
 * UP and SMP versions of the instructions to allow switching back to
 * SMP at runtime, when hotplugging in a new CPU, which is especially
 * useful in virtualized environments.
 *
 * The very common lock prefix is handled as special case in a
 * separate table which is a pure address list without replacement ptr
 * and size information.  That keeps the table sizes small.
 */

#ifdef CONFIG_SMP
#define LOCK_PREFIX_HERE \
		".section .smp_locks,\"a\"\n"	\
		_ASM_ALIGN "\n"			\
		_ASM_PTR "671f\n" /* address */	\
		".previous\n"			\
		"671:"

#define LOCK_PREFIX LOCK_PREFIX_HERE "\n\tlock; "

#else /* ! CONFIG_SMP */
#define LOCK_PREFIX_HERE ""
#define LOCK_PREFIX ""
#endif

/* This must be included *after* the definition of LOCK_PREFIX */
#include <asm/cpufeature.h>

struct alt_instr {
	u8 *instr;		/* original instruction */
	u8 *replacement;
	u8  cpuid;		/* cpuid bit set for replacement */
	u8  instrlen;		/* length of original instruction */
	u8  replacementlen;	/* length of new instruction, <= instrlen */
	u8  pad1;
#ifdef CONFIG_X86_64
	u32 pad2;
#endif
};

extern void alternative_instructions(void);
extern void apply_alternatives(struct alt_instr *start, struct alt_instr *end);

struct module;

#ifdef CONFIG_SMP
extern void alternatives_smp_module_add(struct module *mod, char *name,
					void *locks, void *locks_end,
					void *text, void *text_end);
extern void alternatives_smp_module_del(struct module *mod);
extern void alternatives_smp_switch(int smp);
#else
static inline void alternatives_smp_module_add(struct module *mod, char *name,
					       void *locks, void *locks_end,
					       void *text, void *text_end) {}
static inline void alternatives_smp_module_del(struct module *mod) {}
static inline void alternatives_smp_switch(int smp) {}
#endif	/* CONFIG_SMP */

/* alternative assembly primitive: */
#define ALTERNATIVE(oldinstr, newinstr, feature)			\
									\
      "661:\n\t" oldinstr "\n662:\n"					\
      ".section .altinstructions,\"a\"\n"				\
      _ASM_ALIGN "\n"							\
      _ASM_PTR "661b\n"				/* label           */	\
      _ASM_PTR "663f\n"				/* new instruction */	\
      "	 .byte " __stringify(feature) "\n"	/* feature bit     */	\
      "	 .byte 662b-661b\n"			/* sourcelen       */	\
      "	 .byte 664f-663f\n"			/* replacementlen  */	\
      "	 .byte 0xff + (664f-663f) - (662b-661b)\n" /* rlen <= slen */	\
      ".previous\n"							\
      ".section .altinstr_replacement, \"ax\"\n"			\
      "663:\n\t" newinstr "\n664:\n"		/* replacement     */	\
      ".previous"

/*
 * Alternative instructions for different CPU types or capabilities.
 *
 * This allows to use optimized instructions even on generic binary
 * kernels.
 *
 * length of oldinstr must be longer or equal the length of newinstr
 * It can be padded with nops as needed.
 *
 * For non barrier like inlines please define new variants
 * without volatile and memory clobber.
 */
#define alternative(oldinstr, newinstr, feature)			\
	asm volatile (ALTERNATIVE(oldinstr, newinstr, feature) : : : "memory")

/*
 * Alternative inline assembly with input.
 *
 * Pecularities:
 * No memory clobber here.
 * Argument numbers start with 1.
 * Best is to use constraints that are fixed size (like (%1) ... "r")
 * If you use variable sized constraints like "m" or "g" in the
 * replacement make sure to pad to the worst case length.
 * Leaving an unused argument 0 to keep API compatibility.
 */
#define alternative_input(oldinstr, newinstr, feature, input...)	\
	asm volatile (ALTERNATIVE(oldinstr, newinstr, feature)		\
		: : "i" (0), ## input)

/* Like alternative_input, but with a single output argument */
#define alternative_io(oldinstr, newinstr, feature, output, input...)	\
	asm volatile (ALTERNATIVE(oldinstr, newinstr, feature)		\
		: output : "i" (0), ## input)

/* Like alternative_io, but for replacing a direct call with another one. */
#define alternative_call(oldfunc, newfunc, feature, output, input...)	\
	asm volatile (ALTERNATIVE("call %P[old]", "call %P[new]", feature) \
		: output : [old] "i" (oldfunc), [new] "i" (newfunc), ## input)

/*
 * use this macro(s) if you need more than one output parameter
 * in alternative_io
 */
#define ASM_OUTPUT2(a...) a

struct paravirt_patch_site;
#ifdef CONFIG_PARAVIRT
void apply_paravirt(struct paravirt_patch_site *start,
		    struct paravirt_patch_site *end);
#else
static inline void apply_paravirt(struct paravirt_patch_site *start,
				  struct paravirt_patch_site *end)
{}
#define __parainstructions	NULL
#define __parainstructions_end	NULL
#endif

/*
 * Clear and restore the kernel write-protection flag on the local CPU.
 * Allows the kernel to edit read-only pages.
 * Side-effect: any interrupt handler running between save and restore will have
 * the ability to write to read-only pages.
 *
 * Warning:
 * Code patching in the UP case is safe if NMIs and MCE handlers are stopped and
 * no thread can be preempted in the instructions being modified (no iret to an
 * invalid instruction possible) or if the instructions are changed from a
 * consistent state to another consistent state atomically.
 * More care must be taken when modifying code in the SMP case because of
 * Intel's errata.
 * On the local CPU you need to be protected again NMI or MCE handlers seeing an
 * inconsistent instruction while you patch.
 */
extern void *text_poke(void *addr, const void *opcode, size_t len);

#endif /* _ASM_X86_ALTERNATIVE_H */
Commit	Line	Data
1965aae3 PA	1	#ifndef _ASM_X86_ALTERNATIVE_H
1965aae3 PA	2	#define _ASM_X86_ALTERNATIVE_H
6b592570 PA	3
	4	#include <linux/types.h>
	5	#include <linux/stddef.h>
edc953fa	6	#include <linux/stringify.h>
6b592570 PA	7	#include <asm/asm.h>
	8
	9	/*
	10	* Alternative inline assembly for SMP.
	11	*
	12	* The LOCK_PREFIX macro defined here replaces the LOCK and
	13	* LOCK_PREFIX macros used everywhere in the source tree.
	14	*
	15	* SMP alternatives use the same data structures as the other
	16	* alternatives and the X86_FEATURE_UP flag to indicate the case of a
	17	* UP system running a SMP kernel. The existing apply_alternatives()
	18	* works fine for patching a SMP kernel for UP.
	19	*
	20	* The SMP alternative tables can be kept after boot and contain both
	21	* UP and SMP versions of the instructions to allow switching back to
	22	* SMP at runtime, when hotplugging in a new CPU, which is especially
	23	* useful in virtualized environments.
	24	*
	25	* The very common lock prefix is handled as special case in a
	26	* separate table which is a pure address list without replacement ptr
	27	* and size information. That keeps the table sizes small.
	28	*/
	29
	30	#ifdef CONFIG_SMP
b3ac891b	31	#define LOCK_PREFIX_HERE \
6b592570 PA	32	".section .smp_locks,\"a\"\n" \
6b592570 PA	33	_ASM_ALIGN "\n" \
b3ac891b	34	_ASM_PTR "671f\n" /* address */ \
6b592570	35	".previous\n" \
b3ac891b LB	36	"671:"
	37
	38	#define LOCK_PREFIX LOCK_PREFIX_HERE "\n\tlock; "
6b592570 PA	39
6b592570 PA	40	#else /* ! CONFIG_SMP */
b701a47b	41	#define LOCK_PREFIX_HERE ""
6b592570 PA	42	#define LOCK_PREFIX ""
	43	#endif
	44
	45	/* This must be included after the definition of LOCK_PREFIX */
	46	#include <asm/cpufeature.h>
	47
	48	struct alt_instr {
	49	u8 instr; / original instruction */
	50	u8 *replacement;
	51	u8 cpuid; /* cpuid bit set for replacement */
	52	u8 instrlen; /* length of original instruction */
	53	u8 replacementlen; /* length of new instruction, <= instrlen */
	54	u8 pad1;
	55	#ifdef CONFIG_X86_64
	56	u32 pad2;
	57	#endif
	58	};
	59
	60	extern void alternative_instructions(void);
	61	extern void apply_alternatives(struct alt_instr start, struct alt_instr end);
	62
	63	struct module;
	64
	65	#ifdef CONFIG_SMP
	66	extern void alternatives_smp_module_add(struct module mod, char name,
	67	void locks, void locks_end,
	68	void text, void text_end);
	69	extern void alternatives_smp_module_del(struct module *mod);
	70	extern void alternatives_smp_switch(int smp);
	71	#else
	72	static inline void alternatives_smp_module_add(struct module mod, char name,
2ac1ea7c JP	73	void locks, void locks_end,
2ac1ea7c JP	74	void text, void text_end) {}
6b592570 PA	75	static inline void alternatives_smp_module_del(struct module *mod) {}
	76	static inline void alternatives_smp_switch(int smp) {}
	77	#endif /* CONFIG_SMP */
	78
edc953fa MD	79	/* alternative assembly primitive: */
	80	#define ALTERNATIVE(oldinstr, newinstr, feature) \
	81	\
	82	"661:\n\t" oldinstr "\n662:\n" \
	83	".section .altinstructions,\"a\"\n" \
	84	_ASM_ALIGN "\n" \
	85	_ASM_PTR "661b\n" /* label */ \
	86	_ASM_PTR "663f\n" /* new instruction */ \
	87	" .byte " __stringify(feature) "\n" /* feature bit */ \
	88	" .byte 662b-661b\n" /* sourcelen */ \
	89	" .byte 664f-663f\n" /* replacementlen */ \
01be50a3	90	" .byte 0xff + (664f-663f) - (662b-661b)\n" /* rlen <= slen */ \
edc953fa MD	91	".previous\n" \
	92	".section .altinstr_replacement, \"ax\"\n" \
	93	"663:\n\t" newinstr "\n664:\n" /* replacement */ \
	94	".previous"
	95
6b592570 PA	96	/*
	97	* Alternative instructions for different CPU types or capabilities.
	98	*
	99	* This allows to use optimized instructions even on generic binary
	100	* kernels.
	101	*
	102	* length of oldinstr must be longer or equal the length of newinstr
	103	* It can be padded with nops as needed.
	104	*
	105	* For non barrier like inlines please define new variants
	106	* without volatile and memory clobber.
	107	*/
	108	#define alternative(oldinstr, newinstr, feature) \
edc953fa	109	asm volatile (ALTERNATIVE(oldinstr, newinstr, feature) : : : "memory")
6b592570 PA	110
	111	/*
	112	* Alternative inline assembly with input.
	113	*
	114	* Pecularities:
	115	* No memory clobber here.
	116	* Argument numbers start with 1.
	117	* Best is to use constraints that are fixed size (like (%1) ... "r")
	118	* If you use variable sized constraints like "m" or "g" in the
	119	* replacement make sure to pad to the worst case length.
edc953fa	120	* Leaving an unused argument 0 to keep API compatibility.
6b592570 PA	121	*/
6b592570 PA	122	#define alternative_input(oldinstr, newinstr, feature, input...) \
edc953fa MD	123	asm volatile (ALTERNATIVE(oldinstr, newinstr, feature) \
edc953fa MD	124	: : "i" (0), ## input)
6b592570 PA	125
	126	/* Like alternative_input, but with a single output argument */
	127	#define alternative_io(oldinstr, newinstr, feature, output, input...) \
edc953fa MD	128	asm volatile (ALTERNATIVE(oldinstr, newinstr, feature) \
edc953fa MD	129	: output : "i" (0), ## input)
6b592570	130
1b1d9258 JB	131	/* Like alternative_io, but for replacing a direct call with another one. */
	132	#define alternative_call(oldfunc, newfunc, feature, output, input...) \
	133	asm volatile (ALTERNATIVE("call %P[old]", "call %P[new]", feature) \
	134	: output : [old] "i" (oldfunc), [new] "i" (newfunc), ## input)
	135
6b592570 PA	136	/*
	137	* use this macro(s) if you need more than one output parameter
	138	* in alternative_io
	139	*/
1b1d9258	140	#define ASM_OUTPUT2(a...) a
6b592570 PA	141
	142	struct paravirt_patch_site;
	143	#ifdef CONFIG_PARAVIRT
	144	void apply_paravirt(struct paravirt_patch_site *start,
	145	struct paravirt_patch_site *end);
96a388de	146	#else
2ac1ea7c JP	147	static inline void apply_paravirt(struct paravirt_patch_site *start,
2ac1ea7c JP	148	struct paravirt_patch_site *end)
6b592570 PA	149	{}
	150	#define __parainstructions NULL
	151	#define __parainstructions_end NULL
96a388de	152	#endif
6b592570	153
e587cadd MD	154	/*
	155	* Clear and restore the kernel write-protection flag on the local CPU.
	156	* Allows the kernel to edit read-only pages.
	157	* Side-effect: any interrupt handler running between save and restore will have
	158	* the ability to write to read-only pages.
	159	*
	160	* Warning:
	161	* Code patching in the UP case is safe if NMIs and MCE handlers are stopped and
	162	* no thread can be preempted in the instructions being modified (no iret to an
	163	* invalid instruction possible) or if the instructions are changed from a
	164	* consistent state to another consistent state atomically.
	165	* More care must be taken when modifying code in the SMP case because of
	166	* Intel's errata.
	167	* On the local CPU you need to be protected again NMI or MCE handlers seeing an
	168	* inconsistent instruction while you patch.
e587cadd	169	*/
e587cadd	170	extern void text_poke(void addr, const void *opcode, size_t len);
6b592570	171
1965aae3	172	#endif /* _ASM_X86_ALTERNATIVE_H */