Merge branches 'fixes', 'pgt-next' and 'versatile' into devel
[deliverable/linux.git] / arch / x86 / include / asm / amd_nb.h
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1#ifndef _ASM_X86_AMD_NB_H
2#define _ASM_X86_AMD_NB_H
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3
4#include <linux/pci.h>
5
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6struct amd_nb_bus_dev_range {
7 u8 bus;
8 u8 dev_base;
9 u8 dev_limit;
10};
11
691269f0 12extern const struct pci_device_id amd_nb_misc_ids[];
24d9b70b 13extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[];
0420101c 14struct bootnode;
a32073bf 15
84fd1d35 16extern bool early_is_amd_nb(u32 value);
9653a5c7 17extern int amd_cache_northbridges(void);
eec1d4fa 18extern void amd_flush_garts(void);
940fed2e 19extern int amd_numa_init(void);
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20extern int amd_get_subcaches(int);
21extern int amd_set_subcaches(int, int);
a32073bf 22
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23struct amd_northbridge {
24 struct pci_dev *misc;
41b2610c 25 struct pci_dev *link;
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26};
27
eec1d4fa 28struct amd_northbridge_info {
900f9ac9 29 u16 num;
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30 u64 flags;
31 struct amd_northbridge *nb;
900f9ac9 32};
eec1d4fa 33extern struct amd_northbridge_info amd_northbridges;
900f9ac9 34
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35#define AMD_NB_GART BIT(0)
36#define AMD_NB_L3_INDEX_DISABLE BIT(1)
37#define AMD_NB_L3_PARTITIONING BIT(2)
9653a5c7 38
23ac4ae8 39#ifdef CONFIG_AMD_NB
ade029e2 40
84fd1d35 41static inline u16 amd_nb_num(void)
b206525a 42{
9653a5c7 43 return amd_northbridges.num;
b206525a 44}
ade029e2 45
84fd1d35 46static inline bool amd_nb_has_feature(unsigned feature)
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47{
48 return ((amd_northbridges.flags & feature) == feature);
49}
ade029e2 50
9653a5c7 51static inline struct amd_northbridge *node_to_amd_nb(int node)
b206525a 52{
9653a5c7 53 return (node < amd_northbridges.num) ? &amd_northbridges.nb[node] : NULL;
b206525a 54}
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55
56#else
57
58#define amd_nb_num(x) 0
59#define amd_nb_has_feature(x) false
60#define node_to_amd_nb(x) NULL
61
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62#endif
63
64
23ac4ae8 65#endif /* _ASM_X86_AMD_NB_H */
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