Commit | Line | Data |
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23ac4ae8 AH |
1 | #ifndef _ASM_X86_AMD_NB_H |
2 | #define _ASM_X86_AMD_NB_H | |
a32073bf | 3 | |
24d25dbf | 4 | #include <linux/ioport.h> |
a32073bf AK |
5 | #include <linux/pci.h> |
6 | ||
24d9b70b JB |
7 | struct amd_nb_bus_dev_range { |
8 | u8 bus; | |
9 | u8 dev_base; | |
10 | u8 dev_limit; | |
11 | }; | |
12 | ||
691269f0 | 13 | extern const struct pci_device_id amd_nb_misc_ids[]; |
24d9b70b | 14 | extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[]; |
a32073bf | 15 | |
84fd1d35 | 16 | extern bool early_is_amd_nb(u32 value); |
24d25dbf | 17 | extern struct resource *amd_get_mmconfig_range(struct resource *res); |
9653a5c7 | 18 | extern int amd_cache_northbridges(void); |
eec1d4fa | 19 | extern void amd_flush_garts(void); |
940fed2e | 20 | extern int amd_numa_init(void); |
cabb5bd7 HR |
21 | extern int amd_get_subcaches(int); |
22 | extern int amd_set_subcaches(int, int); | |
a32073bf | 23 | |
d2946041 TG |
24 | struct amd_l3_cache { |
25 | unsigned indices; | |
26 | u8 subcaches[4]; | |
27 | }; | |
28 | ||
019f34fc BP |
29 | struct threshold_block { |
30 | unsigned int block; | |
31 | unsigned int bank; | |
32 | unsigned int cpu; | |
33 | u32 address; | |
34 | u16 interrupt_enable; | |
35 | bool interrupt_capable; | |
36 | u16 threshold_limit; | |
37 | struct kobject kobj; | |
38 | struct list_head miscj; | |
39 | }; | |
40 | ||
41 | struct threshold_bank { | |
42 | struct kobject *kobj; | |
43 | struct threshold_block *blocks; | |
44 | ||
45 | /* initialized to the number of CPUs on the node sharing this bank */ | |
46 | atomic_t cpus; | |
47 | }; | |
48 | ||
9653a5c7 HR |
49 | struct amd_northbridge { |
50 | struct pci_dev *misc; | |
41b2610c | 51 | struct pci_dev *link; |
d2946041 | 52 | struct amd_l3_cache l3_cache; |
019f34fc | 53 | struct threshold_bank *bank4; |
9653a5c7 HR |
54 | }; |
55 | ||
eec1d4fa | 56 | struct amd_northbridge_info { |
900f9ac9 | 57 | u16 num; |
9653a5c7 HR |
58 | u64 flags; |
59 | struct amd_northbridge *nb; | |
900f9ac9 | 60 | }; |
eec1d4fa | 61 | extern struct amd_northbridge_info amd_northbridges; |
900f9ac9 | 62 | |
84fd1d35 BP |
63 | #define AMD_NB_GART BIT(0) |
64 | #define AMD_NB_L3_INDEX_DISABLE BIT(1) | |
65 | #define AMD_NB_L3_PARTITIONING BIT(2) | |
9653a5c7 | 66 | |
23ac4ae8 | 67 | #ifdef CONFIG_AMD_NB |
ade029e2 | 68 | |
84fd1d35 | 69 | static inline u16 amd_nb_num(void) |
b206525a | 70 | { |
9653a5c7 | 71 | return amd_northbridges.num; |
b206525a | 72 | } |
ade029e2 | 73 | |
84fd1d35 | 74 | static inline bool amd_nb_has_feature(unsigned feature) |
9653a5c7 HR |
75 | { |
76 | return ((amd_northbridges.flags & feature) == feature); | |
77 | } | |
ade029e2 | 78 | |
9653a5c7 | 79 | static inline struct amd_northbridge *node_to_amd_nb(int node) |
b206525a | 80 | { |
9653a5c7 | 81 | return (node < amd_northbridges.num) ? &amd_northbridges.nb[node] : NULL; |
b206525a | 82 | } |
9653a5c7 HR |
83 | |
84 | #else | |
85 | ||
86 | #define amd_nb_num(x) 0 | |
87 | #define amd_nb_has_feature(x) false | |
88 | #define node_to_amd_nb(x) NULL | |
89 | ||
afd9fcee AH |
90 | #endif |
91 | ||
92 | ||
23ac4ae8 | 93 | #endif /* _ASM_X86_AMD_NB_H */ |