[deliverable/linux.git] / arch / x86 / include / asm / apic.h

#ifndef _ASM_X86_APIC_H
#define _ASM_X86_APIC_H

#include <linux/pm.h>
#include <linux/delay.h>

#include <asm/alternative.h>
#include <asm/fixmap.h>
#include <asm/apicdef.h>
#include <asm/processor.h>
#include <asm/system.h>
#include <asm/cpufeature.h>
#include <asm/msr.h>

#define ARCH_APICTIMER_STOPS_ON_C3	1

/*
 * Debugging macros
 */
#define APIC_QUIET   0
#define APIC_VERBOSE 1
#define APIC_DEBUG   2

/*
 * Define the default level of output to be very little
 * This can be turned up by using apic=verbose for more
 * information and apic=debug for _lots_ of information.
 * apic_verbosity is defined in apic.c
 */
#define apic_printk(v, s, a...) do {       \
		if ((v) <= apic_verbosity) \
			printk(s, ##a);    \
	} while (0)


extern void generic_apic_probe(void);

#ifdef CONFIG_X86_LOCAL_APIC

extern unsigned int apic_verbosity;
extern int local_apic_timer_c2_ok;

extern int disable_apic;
/*
 * Basic functions accessing APICs.
 */
#ifdef CONFIG_PARAVIRT
#include <asm/paravirt.h>
#else
#define setup_boot_clock setup_boot_APIC_clock
#define setup_secondary_clock setup_secondary_APIC_clock
#endif

extern int is_vsmp_box(void);
extern void xapic_wait_icr_idle(void);
extern u32 safe_xapic_wait_icr_idle(void);
extern u64 xapic_icr_read(void);
extern void xapic_icr_write(u32, u32);
extern int setup_profiling_timer(unsigned int);

static inline void native_apic_mem_write(u32 reg, u32 v)
{
	volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);

	alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP,
		       ASM_OUTPUT2("=r" (v), "=m" (*addr)),
		       ASM_OUTPUT2("0" (v), "m" (*addr)));
}

static inline u32 native_apic_mem_read(u32 reg)
{
	return *((volatile u32 *)(APIC_BASE + reg));
}

static inline void native_apic_msr_write(u32 reg, u32 v)
{
	if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
	    reg == APIC_LVR)
		return;

	wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
}

static inline u32 native_apic_msr_read(u32 reg)
{
	u32 low, high;

	if (reg == APIC_DFR)
		return -1;

	rdmsr(APIC_BASE_MSR + (reg >> 4), low, high);
	return low;
}

#ifndef CONFIG_X86_32
extern int x2apic, x2apic_preenabled;
extern void check_x2apic(void);
extern void enable_x2apic(void);
extern void enable_IR_x2apic(void);
extern void x2apic_icr_write(u32 low, u32 id);
static inline int x2apic_enabled(void)
{
	int msr, msr2;

	if (!cpu_has_x2apic)
		return 0;

	rdmsr(MSR_IA32_APICBASE, msr, msr2);
	if (msr & X2APIC_ENABLE)
		return 1;
	return 0;
}
#else
#define x2apic_enabled()	0
#endif

struct apic_ops {
	u32 (*read)(u32 reg);
	void (*write)(u32 reg, u32 v);
	u64 (*icr_read)(void);
	void (*icr_write)(u32 low, u32 high);
	void (*wait_icr_idle)(void);
	u32 (*safe_wait_icr_idle)(void);
};

extern struct apic_ops *apic_ops;

#define apic_read (apic_ops->read)
#define apic_write (apic_ops->write)
#define apic_icr_read (apic_ops->icr_read)
#define apic_icr_write (apic_ops->icr_write)
#define apic_wait_icr_idle (apic_ops->wait_icr_idle)
#define safe_apic_wait_icr_idle (apic_ops->safe_wait_icr_idle)

extern int get_physical_broadcast(void);

#ifdef CONFIG_X86_64
static inline void ack_x2APIC_irq(void)
{
	/* Docs say use 0 for future compatibility */
	native_apic_msr_write(APIC_EOI, 0);
}
#endif


static inline void ack_APIC_irq(void)
{
	/*
	 * ack_APIC_irq() actually gets compiled as a single instruction
	 * ... yummie.
	 */

	/* Docs say use 0 for future compatibility */
	apic_write(APIC_EOI, 0);
}

extern int lapic_get_maxlvt(void);
extern void clear_local_APIC(void);
extern void connect_bsp_APIC(void);
extern void disconnect_bsp_APIC(int virt_wire_setup);
extern void disable_local_APIC(void);
extern void lapic_shutdown(void);
extern int verify_local_APIC(void);
extern void cache_APIC_registers(void);
extern void sync_Arb_IDs(void);
extern void init_bsp_APIC(void);
extern void setup_local_APIC(void);
extern void end_local_APIC_setup(void);
extern void init_apic_mappings(void);
extern void setup_boot_APIC_clock(void);
extern void setup_secondary_APIC_clock(void);
extern int APIC_init_uniprocessor(void);
extern void enable_NMI_through_LVT0(void);

/*
 * On 32bit this is mach-xxx local
 */
#ifdef CONFIG_X86_64
extern void early_init_lapic_mapping(void);
extern int apic_is_clustered_box(void);
#else
static inline int apic_is_clustered_box(void)
{
	return 0;
}
#endif

extern u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask);
extern u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask);


#else /* !CONFIG_X86_LOCAL_APIC */
static inline void lapic_shutdown(void) { }
#define local_apic_timer_c2_ok		1
static inline void init_apic_mappings(void) { }

#endif /* !CONFIG_X86_LOCAL_APIC */

#endif /* _ASM_X86_APIC_H */
Commit	Line	Data
1965aae3 PA	1	#ifndef _ASM_X86_APIC_H
1965aae3 PA	2	#define _ASM_X86_APIC_H
67c5fc5c TG	3
	4	#include <linux/pm.h>
	5	#include <linux/delay.h>
593f4a78 MR	6
593f4a78 MR	7	#include <asm/alternative.h>
67c5fc5c TG	8	#include <asm/fixmap.h>
	9	#include <asm/apicdef.h>
	10	#include <asm/processor.h>
	11	#include <asm/system.h>
13c88fb5 SS	12	#include <asm/cpufeature.h>
13c88fb5 SS	13	#include <asm/msr.h>
67c5fc5c TG	14
	15	#define ARCH_APICTIMER_STOPS_ON_C3 1
	16
67c5fc5c TG	17	/*
	18	* Debugging macros
	19	*/
	20	#define APIC_QUIET 0
	21	#define APIC_VERBOSE 1
	22	#define APIC_DEBUG 2
	23
	24	/*
	25	* Define the default level of output to be very little
	26	* This can be turned up by using apic=verbose for more
	27	* information and apic=debug for _lots_ of information.
	28	* apic_verbosity is defined in apic.c
	29	*/
	30	#define apic_printk(v, s, a...) do { \
	31	if ((v) <= apic_verbosity) \
	32	printk(s, ##a); \
	33	} while (0)
	34
	35
	36	extern void generic_apic_probe(void);
	37
	38	#ifdef CONFIG_X86_LOCAL_APIC
	39
baa13188	40	extern unsigned int apic_verbosity;
67c5fc5c	41	extern int local_apic_timer_c2_ok;
67c5fc5c	42
3c999f14	43	extern int disable_apic;
67c5fc5c TG	44	/*
	45	* Basic functions accessing APICs.
	46	*/
	47	#ifdef CONFIG_PARAVIRT
	48	#include <asm/paravirt.h>
96a388de	49	#else
67c5fc5c TG	50	#define setup_boot_clock setup_boot_APIC_clock
67c5fc5c TG	51	#define setup_secondary_clock setup_secondary_APIC_clock
96a388de	52	#endif
67c5fc5c	53
aa7d8e25	54	extern int is_vsmp_box(void);
2b97df06 JS	55	extern void xapic_wait_icr_idle(void);
	56	extern u32 safe_xapic_wait_icr_idle(void);
	57	extern u64 xapic_icr_read(void);
	58	extern void xapic_icr_write(u32, u32);
	59	extern int setup_profiling_timer(unsigned int);
aa7d8e25	60
1b374e4d	61	static inline void native_apic_mem_write(u32 reg, u32 v)
67c5fc5c	62	{
593f4a78	63	volatile u32 addr = (volatile u32 )(APIC_BASE + reg);
67c5fc5c	64
593f4a78 MR	65	alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP,
	66	ASM_OUTPUT2("=r" (v), "=m" (*addr)),
	67	ASM_OUTPUT2("0" (v), "m" (*addr)));
67c5fc5c TG	68	}
67c5fc5c TG	69
1b374e4d	70	static inline u32 native_apic_mem_read(u32 reg)
67c5fc5c TG	71	{
	72	return ((volatile u32 )(APIC_BASE + reg));
	73	}
	74
13c88fb5 SS	75	static inline void native_apic_msr_write(u32 reg, u32 v)
	76	{
	77	if (reg == APIC_DFR \|\| reg == APIC_ID \|\| reg == APIC_LDR \|\|
	78	reg == APIC_LVR)
	79	return;
	80
	81	wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
	82	}
	83
	84	static inline u32 native_apic_msr_read(u32 reg)
	85	{
	86	u32 low, high;
	87
	88	if (reg == APIC_DFR)
	89	return -1;
	90
	91	rdmsr(APIC_BASE_MSR + (reg >> 4), low, high);
	92	return low;
	93	}
	94
c535b6a1	95	#ifndef CONFIG_X86_32
6e1cb38a SS	96	extern int x2apic, x2apic_preenabled;
	97	extern void check_x2apic(void);
	98	extern void enable_x2apic(void);
	99	extern void enable_IR_x2apic(void);
	100	extern void x2apic_icr_write(u32 low, u32 id);
a11b5abe YL	101	static inline int x2apic_enabled(void)
	102	{
	103	int msr, msr2;
	104
	105	if (!cpu_has_x2apic)
	106	return 0;
	107
	108	rdmsr(MSR_IA32_APICBASE, msr, msr2);
	109	if (msr & X2APIC_ENABLE)
	110	return 1;
	111	return 0;
	112	}
	113	#else
	114	#define x2apic_enabled() 0
c535b6a1	115	#endif
1b374e4d SS	116
	117	struct apic_ops {
	118	u32 (*read)(u32 reg);
	119	void (*write)(u32 reg, u32 v);
1b374e4d SS	120	u64 (*icr_read)(void);
	121	void (*icr_write)(u32 low, u32 high);
	122	void (*wait_icr_idle)(void);
	123	u32 (*safe_wait_icr_idle)(void);
	124	};
	125
	126	extern struct apic_ops *apic_ops;
	127
	128	#define apic_read (apic_ops->read)
	129	#define apic_write (apic_ops->write)
1b374e4d SS	130	#define apic_icr_read (apic_ops->icr_read)
	131	#define apic_icr_write (apic_ops->icr_write)
	132	#define apic_wait_icr_idle (apic_ops->wait_icr_idle)
	133	#define safe_apic_wait_icr_idle (apic_ops->safe_wait_icr_idle)
1b374e4d	134
67c5fc5c TG	135	extern int get_physical_broadcast(void);
67c5fc5c TG	136
89027d35 SS	137	#ifdef CONFIG_X86_64
	138	static inline void ack_x2APIC_irq(void)
	139	{
	140	/* Docs say use 0 for future compatibility */
	141	native_apic_msr_write(APIC_EOI, 0);
	142	}
	143	#endif
	144
	145
67c5fc5c TG	146	static inline void ack_APIC_irq(void)
	147	{
	148	/*
0791e13f	149	* ack_APIC_irq() actually gets compiled as a single instruction
67c5fc5c TG	150	* ... yummie.
	151	*/
	152
	153	/* Docs say use 0 for future compatibility */
593f4a78	154	apic_write(APIC_EOI, 0);
67c5fc5c TG	155	}
	156
	157	extern int lapic_get_maxlvt(void);
	158	extern void clear_local_APIC(void);
	159	extern void connect_bsp_APIC(void);
	160	extern void disconnect_bsp_APIC(int virt_wire_setup);
	161	extern void disable_local_APIC(void);
	162	extern void lapic_shutdown(void);
	163	extern int verify_local_APIC(void);
	164	extern void cache_APIC_registers(void);
	165	extern void sync_Arb_IDs(void);
	166	extern void init_bsp_APIC(void);
	167	extern void setup_local_APIC(void);
739f33b3	168	extern void end_local_APIC_setup(void);
67c5fc5c	169	extern void init_apic_mappings(void);
67c5fc5c TG	170	extern void setup_boot_APIC_clock(void);
	171	extern void setup_secondary_APIC_clock(void);
	172	extern int APIC_init_uniprocessor(void);
e9427101	173	extern void enable_NMI_through_LVT0(void);
67c5fc5c TG	174
	175	/*
	176	* On 32bit this is mach-xxx local
	177	*/
	178	#ifdef CONFIG_X86_64
8643f9d0	179	extern void early_init_lapic_mapping(void);
8fbbc4b4 AK	180	extern int apic_is_clustered_box(void);
	181	#else
	182	static inline int apic_is_clustered_box(void)
	183	{
	184	return 0;
	185	}
67c5fc5c TG	186	#endif
67c5fc5c TG	187
7b83dae7 RR	188	extern u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask);
7b83dae7 RR	189	extern u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask);
67c5fc5c	190
67c5fc5c TG	191
	192	#else /* !CONFIG_X86_LOCAL_APIC */
	193	static inline void lapic_shutdown(void) { }
	194	#define local_apic_timer_c2_ok 1
f3294a33	195	static inline void init_apic_mappings(void) { }
67c5fc5c TG	196
	197	#endif /* !CONFIG_X86_LOCAL_APIC */
	198
1965aae3	199	#endif /* _ASM_X86_APIC_H */