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1965aae3 PA |
1 | #ifndef _ASM_X86_APIC_H |
2 | #define _ASM_X86_APIC_H | |
67c5fc5c | 3 | |
e2780a68 | 4 | #include <linux/cpumask.h> |
e2780a68 | 5 | #include <linux/pm.h> |
593f4a78 MR |
6 | |
7 | #include <asm/alternative.h> | |
e2780a68 | 8 | #include <asm/cpufeature.h> |
67c5fc5c | 9 | #include <asm/processor.h> |
e2780a68 | 10 | #include <asm/apicdef.h> |
60063497 | 11 | #include <linux/atomic.h> |
e2780a68 IM |
12 | #include <asm/fixmap.h> |
13 | #include <asm/mpspec.h> | |
13c88fb5 | 14 | #include <asm/msr.h> |
eddc0e92 | 15 | #include <asm/idle.h> |
67c5fc5c TG |
16 | |
17 | #define ARCH_APICTIMER_STOPS_ON_C3 1 | |
18 | ||
67c5fc5c TG |
19 | /* |
20 | * Debugging macros | |
21 | */ | |
22 | #define APIC_QUIET 0 | |
23 | #define APIC_VERBOSE 1 | |
24 | #define APIC_DEBUG 2 | |
25 | ||
26 | /* | |
27 | * Define the default level of output to be very little | |
28 | * This can be turned up by using apic=verbose for more | |
29 | * information and apic=debug for _lots_ of information. | |
30 | * apic_verbosity is defined in apic.c | |
31 | */ | |
32 | #define apic_printk(v, s, a...) do { \ | |
33 | if ((v) <= apic_verbosity) \ | |
34 | printk(s, ##a); \ | |
35 | } while (0) | |
36 | ||
37 | ||
160d8dac | 38 | #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) |
67c5fc5c | 39 | extern void generic_apic_probe(void); |
160d8dac IM |
40 | #else |
41 | static inline void generic_apic_probe(void) | |
42 | { | |
43 | } | |
44 | #endif | |
67c5fc5c TG |
45 | |
46 | #ifdef CONFIG_X86_LOCAL_APIC | |
47 | ||
baa13188 | 48 | extern unsigned int apic_verbosity; |
67c5fc5c | 49 | extern int local_apic_timer_c2_ok; |
67c5fc5c | 50 | |
3c999f14 | 51 | extern int disable_apic; |
1ade93ef | 52 | extern unsigned int lapic_timer_frequency; |
0939e4fd IM |
53 | |
54 | #ifdef CONFIG_SMP | |
55 | extern void __inquire_remote_apic(int apicid); | |
56 | #else /* CONFIG_SMP */ | |
57 | static inline void __inquire_remote_apic(int apicid) | |
58 | { | |
59 | } | |
60 | #endif /* CONFIG_SMP */ | |
61 | ||
62 | static inline void default_inquire_remote_apic(int apicid) | |
63 | { | |
64 | if (apic_verbosity >= APIC_DEBUG) | |
65 | __inquire_remote_apic(apicid); | |
66 | } | |
67 | ||
8312136f CG |
68 | /* |
69 | * With 82489DX we can't rely on apic feature bit | |
70 | * retrieved via cpuid but still have to deal with | |
71 | * such an apic chip so we assume that SMP configuration | |
72 | * is found from MP table (64bit case uses ACPI mostly | |
73 | * which set smp presence flag as well so we are safe | |
74 | * to use this helper too). | |
75 | */ | |
76 | static inline bool apic_from_smp_config(void) | |
77 | { | |
78 | return smp_found_config && !disable_apic; | |
79 | } | |
80 | ||
67c5fc5c TG |
81 | /* |
82 | * Basic functions accessing APICs. | |
83 | */ | |
84 | #ifdef CONFIG_PARAVIRT | |
85 | #include <asm/paravirt.h> | |
96a388de | 86 | #endif |
67c5fc5c | 87 | |
2b97df06 | 88 | extern int setup_profiling_timer(unsigned int); |
aa7d8e25 | 89 | |
1b374e4d | 90 | static inline void native_apic_mem_write(u32 reg, u32 v) |
67c5fc5c | 91 | { |
593f4a78 | 92 | volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); |
67c5fc5c | 93 | |
9b13a93d | 94 | alternative_io("movl %0, %1", "xchgl %0, %1", X86_BUG_11AP, |
593f4a78 MR |
95 | ASM_OUTPUT2("=r" (v), "=m" (*addr)), |
96 | ASM_OUTPUT2("0" (v), "m" (*addr))); | |
67c5fc5c TG |
97 | } |
98 | ||
1b374e4d | 99 | static inline u32 native_apic_mem_read(u32 reg) |
67c5fc5c TG |
100 | { |
101 | return *((volatile u32 *)(APIC_BASE + reg)); | |
102 | } | |
103 | ||
c1eeb2de YL |
104 | extern void native_apic_wait_icr_idle(void); |
105 | extern u32 native_safe_apic_wait_icr_idle(void); | |
106 | extern void native_apic_icr_write(u32 low, u32 id); | |
107 | extern u64 native_apic_icr_read(void); | |
108 | ||
fc1edaf9 | 109 | extern int x2apic_mode; |
b24696bc | 110 | |
d0b03bd1 | 111 | #ifdef CONFIG_X86_X2APIC |
ce4e240c SS |
112 | /* |
113 | * Make previous memory operations globally visible before | |
114 | * sending the IPI through x2apic wrmsr. We need a serializing instruction or | |
115 | * mfence for this. | |
116 | */ | |
117 | static inline void x2apic_wrmsr_fence(void) | |
118 | { | |
119 | asm volatile("mfence" : : : "memory"); | |
120 | } | |
121 | ||
13c88fb5 SS |
122 | static inline void native_apic_msr_write(u32 reg, u32 v) |
123 | { | |
124 | if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || | |
125 | reg == APIC_LVR) | |
126 | return; | |
127 | ||
128 | wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); | |
129 | } | |
130 | ||
0ab711ae MT |
131 | static inline void native_apic_msr_eoi_write(u32 reg, u32 v) |
132 | { | |
133 | wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); | |
134 | } | |
135 | ||
13c88fb5 SS |
136 | static inline u32 native_apic_msr_read(u32 reg) |
137 | { | |
0059b243 | 138 | u64 msr; |
13c88fb5 SS |
139 | |
140 | if (reg == APIC_DFR) | |
141 | return -1; | |
142 | ||
0059b243 AK |
143 | rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); |
144 | return (u32)msr; | |
13c88fb5 SS |
145 | } |
146 | ||
c1eeb2de YL |
147 | static inline void native_x2apic_wait_icr_idle(void) |
148 | { | |
149 | /* no need to wait for icr idle in x2apic */ | |
150 | return; | |
151 | } | |
152 | ||
153 | static inline u32 native_safe_x2apic_wait_icr_idle(void) | |
154 | { | |
155 | /* no need to wait for icr idle in x2apic */ | |
156 | return 0; | |
157 | } | |
158 | ||
159 | static inline void native_x2apic_icr_write(u32 low, u32 id) | |
160 | { | |
161 | wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); | |
162 | } | |
163 | ||
164 | static inline u64 native_x2apic_icr_read(void) | |
165 | { | |
166 | unsigned long val; | |
167 | ||
168 | rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); | |
169 | return val; | |
170 | } | |
171 | ||
fc1edaf9 | 172 | extern int x2apic_phys; |
fb209bd8 | 173 | extern int x2apic_preenabled; |
6e1cb38a SS |
174 | extern void check_x2apic(void); |
175 | extern void enable_x2apic(void); | |
a11b5abe YL |
176 | static inline int x2apic_enabled(void) |
177 | { | |
0059b243 | 178 | u64 msr; |
a11b5abe YL |
179 | |
180 | if (!cpu_has_x2apic) | |
181 | return 0; | |
182 | ||
0059b243 | 183 | rdmsrl(MSR_IA32_APICBASE, msr); |
a11b5abe YL |
184 | if (msr & X2APIC_ENABLE) |
185 | return 1; | |
186 | return 0; | |
187 | } | |
fc1edaf9 SS |
188 | |
189 | #define x2apic_supported() (cpu_has_x2apic) | |
ce69a784 GN |
190 | static inline void x2apic_force_phys(void) |
191 | { | |
192 | x2apic_phys = 1; | |
193 | } | |
a11b5abe | 194 | #else |
fb209bd8 YL |
195 | static inline void disable_x2apic(void) |
196 | { | |
197 | } | |
06cd9a7d YL |
198 | static inline void check_x2apic(void) |
199 | { | |
200 | } | |
201 | static inline void enable_x2apic(void) | |
202 | { | |
203 | } | |
06cd9a7d YL |
204 | static inline int x2apic_enabled(void) |
205 | { | |
206 | return 0; | |
207 | } | |
ce69a784 GN |
208 | static inline void x2apic_force_phys(void) |
209 | { | |
210 | } | |
cf6567fe | 211 | |
93758238 | 212 | #define x2apic_preenabled 0 |
fc1edaf9 | 213 | #define x2apic_supported() 0 |
c535b6a1 | 214 | #endif |
1b374e4d | 215 | |
93758238 WH |
216 | extern void enable_IR_x2apic(void); |
217 | ||
67c5fc5c TG |
218 | extern int get_physical_broadcast(void); |
219 | ||
67c5fc5c TG |
220 | extern int lapic_get_maxlvt(void); |
221 | extern void clear_local_APIC(void); | |
222 | extern void connect_bsp_APIC(void); | |
223 | extern void disconnect_bsp_APIC(int virt_wire_setup); | |
224 | extern void disable_local_APIC(void); | |
225 | extern void lapic_shutdown(void); | |
226 | extern int verify_local_APIC(void); | |
67c5fc5c TG |
227 | extern void sync_Arb_IDs(void); |
228 | extern void init_bsp_APIC(void); | |
229 | extern void setup_local_APIC(void); | |
739f33b3 | 230 | extern void end_local_APIC_setup(void); |
2fb270f3 | 231 | extern void bsp_end_local_APIC_setup(void); |
67c5fc5c | 232 | extern void init_apic_mappings(void); |
c0104d38 | 233 | void register_lapic_address(unsigned long address); |
67c5fc5c TG |
234 | extern void setup_boot_APIC_clock(void); |
235 | extern void setup_secondary_APIC_clock(void); | |
236 | extern int APIC_init_uniprocessor(void); | |
a906fdaa | 237 | extern int apic_force_enable(unsigned long addr); |
67c5fc5c TG |
238 | |
239 | /* | |
240 | * On 32bit this is mach-xxx local | |
241 | */ | |
242 | #ifdef CONFIG_X86_64 | |
8fbbc4b4 AK |
243 | extern int apic_is_clustered_box(void); |
244 | #else | |
245 | static inline int apic_is_clustered_box(void) | |
246 | { | |
247 | return 0; | |
248 | } | |
67c5fc5c TG |
249 | #endif |
250 | ||
27afdf20 | 251 | extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); |
67c5fc5c TG |
252 | |
253 | #else /* !CONFIG_X86_LOCAL_APIC */ | |
254 | static inline void lapic_shutdown(void) { } | |
255 | #define local_apic_timer_c2_ok 1 | |
f3294a33 | 256 | static inline void init_apic_mappings(void) { } |
d3ec5cae | 257 | static inline void disable_local_APIC(void) { } |
736decac TG |
258 | # define setup_boot_APIC_clock x86_init_noop |
259 | # define setup_secondary_APIC_clock x86_init_noop | |
67c5fc5c TG |
260 | #endif /* !CONFIG_X86_LOCAL_APIC */ |
261 | ||
1f75ed0c IM |
262 | #ifdef CONFIG_X86_64 |
263 | #define SET_APIC_ID(x) (apic->set_apic_id(x)) | |
264 | #else | |
265 | ||
1f75ed0c IM |
266 | #endif |
267 | ||
e2780a68 IM |
268 | /* |
269 | * Copyright 2004 James Cleverdon, IBM. | |
270 | * Subject to the GNU Public License, v.2 | |
271 | * | |
272 | * Generic APIC sub-arch data struct. | |
273 | * | |
274 | * Hacked for x86-64 by James Cleverdon from i386 architecture code by | |
275 | * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and | |
276 | * James Cleverdon. | |
277 | */ | |
be163a15 | 278 | struct apic { |
e2780a68 IM |
279 | char *name; |
280 | ||
281 | int (*probe)(void); | |
282 | int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); | |
fa63030e | 283 | int (*apic_id_valid)(int apicid); |
e2780a68 IM |
284 | int (*apic_id_registered)(void); |
285 | ||
286 | u32 irq_delivery_mode; | |
287 | u32 irq_dest_mode; | |
288 | ||
289 | const struct cpumask *(*target_cpus)(void); | |
290 | ||
291 | int disable_esr; | |
292 | ||
293 | int dest_logical; | |
7abc0753 | 294 | unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid); |
e2780a68 | 295 | |
1ac322d0 SS |
296 | void (*vector_allocation_domain)(int cpu, struct cpumask *retmask, |
297 | const struct cpumask *mask); | |
e2780a68 IM |
298 | void (*init_apic_ldr)(void); |
299 | ||
7abc0753 | 300 | void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); |
e2780a68 IM |
301 | |
302 | void (*setup_apic_routing)(void); | |
e2780a68 | 303 | int (*cpu_present_to_apicid)(int mps_cpu); |
7abc0753 | 304 | void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap); |
e11dadab | 305 | int (*check_phys_apicid_present)(int phys_apicid); |
e2780a68 IM |
306 | int (*phys_pkg_id)(int cpuid_apic, int index_msb); |
307 | ||
e2780a68 IM |
308 | unsigned int (*get_apic_id)(unsigned long x); |
309 | unsigned long (*set_apic_id)(unsigned int id); | |
310 | unsigned long apic_id_mask; | |
311 | ||
ff164324 AG |
312 | int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask, |
313 | const struct cpumask *andmask, | |
314 | unsigned int *apicid); | |
e2780a68 IM |
315 | |
316 | /* ipi */ | |
317 | void (*send_IPI_mask)(const struct cpumask *mask, int vector); | |
318 | void (*send_IPI_mask_allbutself)(const struct cpumask *mask, | |
319 | int vector); | |
320 | void (*send_IPI_allbutself)(int vector); | |
321 | void (*send_IPI_all)(int vector); | |
322 | void (*send_IPI_self)(int vector); | |
323 | ||
324 | /* wakeup_secondary_cpu */ | |
1f5bcabf | 325 | int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); |
e2780a68 | 326 | |
465822cf | 327 | bool wait_for_init_deassert; |
e2780a68 IM |
328 | void (*inquire_remote_apic)(int apicid); |
329 | ||
330 | /* apic ops */ | |
331 | u32 (*read)(u32 reg); | |
332 | void (*write)(u32 reg, u32 v); | |
2a43195d MT |
333 | /* |
334 | * ->eoi_write() has the same signature as ->write(). | |
335 | * | |
336 | * Drivers can support both ->eoi_write() and ->write() by passing the same | |
337 | * callback value. Kernel can override ->eoi_write() and fall back | |
338 | * on write for EOI. | |
339 | */ | |
340 | void (*eoi_write)(u32 reg, u32 v); | |
e2780a68 IM |
341 | u64 (*icr_read)(void); |
342 | void (*icr_write)(u32 low, u32 high); | |
343 | void (*wait_icr_idle)(void); | |
344 | u32 (*safe_wait_icr_idle)(void); | |
acb8bc09 TH |
345 | |
346 | #ifdef CONFIG_X86_32 | |
347 | /* | |
348 | * Called very early during boot from get_smp_config(). It should | |
349 | * return the logical apicid. x86_[bios]_cpu_to_apicid is | |
350 | * initialized before this function is called. | |
351 | * | |
352 | * If logical apicid can't be determined that early, the function | |
353 | * may return BAD_APICID. Logical apicid will be configured after | |
354 | * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity | |
355 | * won't be applied properly during early boot in this case. | |
356 | */ | |
357 | int (*x86_32_early_logical_apicid)(int cpu); | |
358 | #endif | |
e2780a68 IM |
359 | }; |
360 | ||
0917c01f IM |
361 | /* |
362 | * Pointer to the local APIC driver in use on this system (there's | |
363 | * always just one such driver in use - the kernel decides via an | |
364 | * early probing process which one it picks - and then sticks to it): | |
365 | */ | |
be163a15 | 366 | extern struct apic *apic; |
0917c01f | 367 | |
107e0e0c SS |
368 | /* |
369 | * APIC drivers are probed based on how they are listed in the .apicdrivers | |
370 | * section. So the order is important and enforced by the ordering | |
371 | * of different apic driver files in the Makefile. | |
372 | * | |
373 | * For the files having two apic drivers, we use apic_drivers() | |
374 | * to enforce the order with in them. | |
375 | */ | |
376 | #define apic_driver(sym) \ | |
75fdd155 | 377 | static const struct apic *__apicdrivers_##sym __used \ |
107e0e0c SS |
378 | __aligned(sizeof(struct apic *)) \ |
379 | __section(.apicdrivers) = { &sym } | |
380 | ||
381 | #define apic_drivers(sym1, sym2) \ | |
382 | static struct apic *__apicdrivers_##sym1##sym2[2] __used \ | |
383 | __aligned(sizeof(struct apic *)) \ | |
384 | __section(.apicdrivers) = { &sym1, &sym2 } | |
385 | ||
386 | extern struct apic *__apicdrivers[], *__apicdrivers_end[]; | |
387 | ||
0917c01f IM |
388 | /* |
389 | * APIC functionality to boot other CPUs - only used on SMP: | |
390 | */ | |
391 | #ifdef CONFIG_SMP | |
2b6163bf YL |
392 | extern atomic_t init_deasserted; |
393 | extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip); | |
0917c01f | 394 | #endif |
e2780a68 | 395 | |
d674cd19 | 396 | #ifdef CONFIG_X86_LOCAL_APIC |
346b46be | 397 | |
e2780a68 IM |
398 | static inline u32 apic_read(u32 reg) |
399 | { | |
400 | return apic->read(reg); | |
401 | } | |
402 | ||
403 | static inline void apic_write(u32 reg, u32 val) | |
404 | { | |
405 | apic->write(reg, val); | |
406 | } | |
407 | ||
2a43195d MT |
408 | static inline void apic_eoi(void) |
409 | { | |
410 | apic->eoi_write(APIC_EOI, APIC_EOI_ACK); | |
411 | } | |
412 | ||
e2780a68 IM |
413 | static inline u64 apic_icr_read(void) |
414 | { | |
415 | return apic->icr_read(); | |
416 | } | |
417 | ||
418 | static inline void apic_icr_write(u32 low, u32 high) | |
419 | { | |
420 | apic->icr_write(low, high); | |
421 | } | |
422 | ||
423 | static inline void apic_wait_icr_idle(void) | |
424 | { | |
425 | apic->wait_icr_idle(); | |
426 | } | |
427 | ||
428 | static inline u32 safe_apic_wait_icr_idle(void) | |
429 | { | |
430 | return apic->safe_wait_icr_idle(); | |
431 | } | |
432 | ||
1551df64 MT |
433 | extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)); |
434 | ||
d674cd19 CG |
435 | #else /* CONFIG_X86_LOCAL_APIC */ |
436 | ||
437 | static inline u32 apic_read(u32 reg) { return 0; } | |
438 | static inline void apic_write(u32 reg, u32 val) { } | |
2a43195d | 439 | static inline void apic_eoi(void) { } |
d674cd19 CG |
440 | static inline u64 apic_icr_read(void) { return 0; } |
441 | static inline void apic_icr_write(u32 low, u32 high) { } | |
442 | static inline void apic_wait_icr_idle(void) { } | |
443 | static inline u32 safe_apic_wait_icr_idle(void) { return 0; } | |
1551df64 | 444 | static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {} |
d674cd19 CG |
445 | |
446 | #endif /* CONFIG_X86_LOCAL_APIC */ | |
e2780a68 IM |
447 | |
448 | static inline void ack_APIC_irq(void) | |
449 | { | |
450 | /* | |
451 | * ack_APIC_irq() actually gets compiled as a single instruction | |
452 | * ... yummie. | |
453 | */ | |
2a43195d | 454 | apic_eoi(); |
e2780a68 IM |
455 | } |
456 | ||
457 | static inline unsigned default_get_apic_id(unsigned long x) | |
458 | { | |
459 | unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); | |
460 | ||
42937e81 | 461 | if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) |
e2780a68 IM |
462 | return (x >> 24) & 0xFF; |
463 | else | |
464 | return (x >> 24) & 0x0F; | |
465 | } | |
466 | ||
467 | /* | |
6ab1b27c | 468 | * Warm reset vector position: |
e2780a68 | 469 | */ |
6ab1b27c DR |
470 | #define TRAMPOLINE_PHYS_LOW 0x467 |
471 | #define TRAMPOLINE_PHYS_HIGH 0x469 | |
e2780a68 | 472 | |
2b6163bf | 473 | #ifdef CONFIG_X86_64 |
e2780a68 IM |
474 | extern void apic_send_IPI_self(int vector); |
475 | ||
e2780a68 IM |
476 | DECLARE_PER_CPU(int, x2apic_extra_bits); |
477 | ||
478 | extern int default_cpu_present_to_apicid(int mps_cpu); | |
e11dadab | 479 | extern int default_check_phys_apicid_present(int phys_apicid); |
e2780a68 IM |
480 | #endif |
481 | ||
838312be | 482 | extern void generic_bigsmp_probe(void); |
e2780a68 IM |
483 | |
484 | ||
485 | #ifdef CONFIG_X86_LOCAL_APIC | |
486 | ||
487 | #include <asm/smp.h> | |
488 | ||
489 | #define APIC_DFR_VALUE (APIC_DFR_FLAT) | |
490 | ||
491 | static inline const struct cpumask *default_target_cpus(void) | |
492 | { | |
493 | #ifdef CONFIG_SMP | |
494 | return cpu_online_mask; | |
495 | #else | |
496 | return cpumask_of(0); | |
497 | #endif | |
498 | } | |
499 | ||
bf721d3a AG |
500 | static inline const struct cpumask *online_target_cpus(void) |
501 | { | |
502 | return cpu_online_mask; | |
503 | } | |
504 | ||
0816b0f0 | 505 | DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid); |
e2780a68 IM |
506 | |
507 | ||
508 | static inline unsigned int read_apic_id(void) | |
509 | { | |
510 | unsigned int reg; | |
511 | ||
512 | reg = apic_read(APIC_ID); | |
513 | ||
514 | return apic->get_apic_id(reg); | |
515 | } | |
516 | ||
fa63030e DB |
517 | static inline int default_apic_id_valid(int apicid) |
518 | { | |
b7157acf | 519 | return (apicid < 255); |
fa63030e DB |
520 | } |
521 | ||
a491cc90 JL |
522 | extern int default_acpi_madt_oem_check(char *, char *); |
523 | ||
e2780a68 IM |
524 | extern void default_setup_apic_routing(void); |
525 | ||
9844ab11 CG |
526 | extern struct apic apic_noop; |
527 | ||
e2780a68 | 528 | #ifdef CONFIG_X86_32 |
2c1b284e | 529 | |
acb8bc09 TH |
530 | static inline int noop_x86_32_early_logical_apicid(int cpu) |
531 | { | |
532 | return BAD_APICID; | |
533 | } | |
534 | ||
e2780a68 IM |
535 | /* |
536 | * Set up the logical destination ID. | |
537 | * | |
538 | * Intel recommends to set DFR, LDR and TPR before enabling | |
539 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
540 | * document number 292116). So here it goes... | |
541 | */ | |
542 | extern void default_init_apic_ldr(void); | |
543 | ||
544 | static inline int default_apic_id_registered(void) | |
545 | { | |
546 | return physid_isset(read_apic_id(), phys_cpu_present_map); | |
547 | } | |
548 | ||
f56e5034 YL |
549 | static inline int default_phys_pkg_id(int cpuid_apic, int index_msb) |
550 | { | |
551 | return cpuid_apic >> index_msb; | |
552 | } | |
553 | ||
f56e5034 YL |
554 | #endif |
555 | ||
ff164324 | 556 | static inline int |
a5a39156 AG |
557 | flat_cpu_mask_to_apicid_and(const struct cpumask *cpumask, |
558 | const struct cpumask *andmask, | |
559 | unsigned int *apicid) | |
e2780a68 | 560 | { |
a5a39156 AG |
561 | unsigned long cpu_mask = cpumask_bits(cpumask)[0] & |
562 | cpumask_bits(andmask)[0] & | |
563 | cpumask_bits(cpu_online_mask)[0] & | |
564 | APIC_ALL_CPUS; | |
565 | ||
ff164324 AG |
566 | if (likely(cpu_mask)) { |
567 | *apicid = (unsigned int)cpu_mask; | |
568 | return 0; | |
569 | } else { | |
570 | return -EINVAL; | |
571 | } | |
572 | } | |
573 | ||
ff164324 | 574 | extern int |
6398268d | 575 | default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, |
ff164324 AG |
576 | const struct cpumask *andmask, |
577 | unsigned int *apicid); | |
6398268d | 578 | |
b39f25a8 | 579 | static inline void |
1ac322d0 SS |
580 | flat_vector_allocation_domain(int cpu, struct cpumask *retmask, |
581 | const struct cpumask *mask) | |
9d8e1066 AG |
582 | { |
583 | /* Careful. Some cpus do not strictly honor the set of cpus | |
584 | * specified in the interrupt destination when using lowest | |
585 | * priority interrupt delivery mode. | |
586 | * | |
587 | * In particular there was a hyperthreading cpu observed to | |
588 | * deliver interrupts to the wrong hyperthread when only one | |
589 | * hyperthread was specified in the interrupt desitination. | |
590 | */ | |
591 | cpumask_clear(retmask); | |
592 | cpumask_bits(retmask)[0] = APIC_ALL_CPUS; | |
593 | } | |
594 | ||
b39f25a8 | 595 | static inline void |
1ac322d0 SS |
596 | default_vector_allocation_domain(int cpu, struct cpumask *retmask, |
597 | const struct cpumask *mask) | |
9d8e1066 AG |
598 | { |
599 | cpumask_copy(retmask, cpumask_of(cpu)); | |
600 | } | |
601 | ||
7abc0753 | 602 | static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid) |
e2780a68 | 603 | { |
7abc0753 | 604 | return physid_isset(apicid, *map); |
e2780a68 IM |
605 | } |
606 | ||
7abc0753 | 607 | static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap) |
e2780a68 | 608 | { |
7abc0753 | 609 | *retmap = *phys_map; |
e2780a68 IM |
610 | } |
611 | ||
e2780a68 IM |
612 | static inline int __default_cpu_present_to_apicid(int mps_cpu) |
613 | { | |
614 | if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) | |
615 | return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); | |
616 | else | |
617 | return BAD_APICID; | |
618 | } | |
619 | ||
620 | static inline int | |
e11dadab | 621 | __default_check_phys_apicid_present(int phys_apicid) |
e2780a68 | 622 | { |
e11dadab | 623 | return physid_isset(phys_apicid, phys_cpu_present_map); |
e2780a68 IM |
624 | } |
625 | ||
626 | #ifdef CONFIG_X86_32 | |
627 | static inline int default_cpu_present_to_apicid(int mps_cpu) | |
628 | { | |
629 | return __default_cpu_present_to_apicid(mps_cpu); | |
630 | } | |
631 | ||
632 | static inline int | |
e11dadab | 633 | default_check_phys_apicid_present(int phys_apicid) |
e2780a68 | 634 | { |
e11dadab | 635 | return __default_check_phys_apicid_present(phys_apicid); |
e2780a68 IM |
636 | } |
637 | #else | |
638 | extern int default_cpu_present_to_apicid(int mps_cpu); | |
e11dadab | 639 | extern int default_check_phys_apicid_present(int phys_apicid); |
e2780a68 IM |
640 | #endif |
641 | ||
e2780a68 | 642 | #endif /* CONFIG_X86_LOCAL_APIC */ |
eddc0e92 SA |
643 | extern void irq_enter(void); |
644 | extern void irq_exit(void); | |
645 | ||
646 | static inline void entering_irq(void) | |
647 | { | |
648 | irq_enter(); | |
649 | exit_idle(); | |
650 | } | |
651 | ||
652 | static inline void entering_ack_irq(void) | |
653 | { | |
654 | ack_APIC_irq(); | |
655 | entering_irq(); | |
656 | } | |
657 | ||
658 | static inline void exiting_irq(void) | |
659 | { | |
660 | irq_exit(); | |
661 | } | |
662 | ||
663 | static inline void exiting_ack_irq(void) | |
664 | { | |
665 | irq_exit(); | |
666 | /* Ack only at the end to avoid potential reentry */ | |
667 | ack_APIC_irq(); | |
668 | } | |
e2780a68 | 669 | |
17405453 YY |
670 | extern void ioapic_zap_locks(void); |
671 | ||
1965aae3 | 672 | #endif /* _ASM_X86_APIC_H */ |