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1965aae3 PA |
1 | #ifndef _ASM_X86_APIC_H |
2 | #define _ASM_X86_APIC_H | |
67c5fc5c | 3 | |
e2780a68 | 4 | #include <linux/cpumask.h> |
e2780a68 | 5 | #include <linux/pm.h> |
593f4a78 MR |
6 | |
7 | #include <asm/alternative.h> | |
e2780a68 | 8 | #include <asm/cpufeature.h> |
67c5fc5c | 9 | #include <asm/processor.h> |
e2780a68 | 10 | #include <asm/apicdef.h> |
60063497 | 11 | #include <linux/atomic.h> |
e2780a68 IM |
12 | #include <asm/fixmap.h> |
13 | #include <asm/mpspec.h> | |
13c88fb5 | 14 | #include <asm/msr.h> |
eddc0e92 | 15 | #include <asm/idle.h> |
67c5fc5c TG |
16 | |
17 | #define ARCH_APICTIMER_STOPS_ON_C3 1 | |
18 | ||
67c5fc5c TG |
19 | /* |
20 | * Debugging macros | |
21 | */ | |
22 | #define APIC_QUIET 0 | |
23 | #define APIC_VERBOSE 1 | |
24 | #define APIC_DEBUG 2 | |
25 | ||
26 | /* | |
27 | * Define the default level of output to be very little | |
28 | * This can be turned up by using apic=verbose for more | |
29 | * information and apic=debug for _lots_ of information. | |
30 | * apic_verbosity is defined in apic.c | |
31 | */ | |
32 | #define apic_printk(v, s, a...) do { \ | |
33 | if ((v) <= apic_verbosity) \ | |
34 | printk(s, ##a); \ | |
35 | } while (0) | |
36 | ||
37 | ||
160d8dac | 38 | #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) |
67c5fc5c | 39 | extern void generic_apic_probe(void); |
160d8dac IM |
40 | #else |
41 | static inline void generic_apic_probe(void) | |
42 | { | |
43 | } | |
44 | #endif | |
67c5fc5c TG |
45 | |
46 | #ifdef CONFIG_X86_LOCAL_APIC | |
47 | ||
baa13188 | 48 | extern unsigned int apic_verbosity; |
67c5fc5c | 49 | extern int local_apic_timer_c2_ok; |
67c5fc5c | 50 | |
3c999f14 | 51 | extern int disable_apic; |
1ade93ef | 52 | extern unsigned int lapic_timer_frequency; |
0939e4fd IM |
53 | |
54 | #ifdef CONFIG_SMP | |
55 | extern void __inquire_remote_apic(int apicid); | |
56 | #else /* CONFIG_SMP */ | |
57 | static inline void __inquire_remote_apic(int apicid) | |
58 | { | |
59 | } | |
60 | #endif /* CONFIG_SMP */ | |
61 | ||
62 | static inline void default_inquire_remote_apic(int apicid) | |
63 | { | |
64 | if (apic_verbosity >= APIC_DEBUG) | |
65 | __inquire_remote_apic(apicid); | |
66 | } | |
67 | ||
8312136f CG |
68 | /* |
69 | * With 82489DX we can't rely on apic feature bit | |
70 | * retrieved via cpuid but still have to deal with | |
71 | * such an apic chip so we assume that SMP configuration | |
72 | * is found from MP table (64bit case uses ACPI mostly | |
73 | * which set smp presence flag as well so we are safe | |
74 | * to use this helper too). | |
75 | */ | |
76 | static inline bool apic_from_smp_config(void) | |
77 | { | |
78 | return smp_found_config && !disable_apic; | |
79 | } | |
80 | ||
67c5fc5c TG |
81 | /* |
82 | * Basic functions accessing APICs. | |
83 | */ | |
84 | #ifdef CONFIG_PARAVIRT | |
85 | #include <asm/paravirt.h> | |
96a388de | 86 | #endif |
67c5fc5c | 87 | |
2b97df06 | 88 | extern int setup_profiling_timer(unsigned int); |
aa7d8e25 | 89 | |
1b374e4d | 90 | static inline void native_apic_mem_write(u32 reg, u32 v) |
67c5fc5c | 91 | { |
593f4a78 | 92 | volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); |
67c5fc5c | 93 | |
a930dc45 | 94 | alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP, |
593f4a78 MR |
95 | ASM_OUTPUT2("=r" (v), "=m" (*addr)), |
96 | ASM_OUTPUT2("0" (v), "m" (*addr))); | |
67c5fc5c TG |
97 | } |
98 | ||
1b374e4d | 99 | static inline u32 native_apic_mem_read(u32 reg) |
67c5fc5c TG |
100 | { |
101 | return *((volatile u32 *)(APIC_BASE + reg)); | |
102 | } | |
103 | ||
c1eeb2de YL |
104 | extern void native_apic_wait_icr_idle(void); |
105 | extern u32 native_safe_apic_wait_icr_idle(void); | |
106 | extern void native_apic_icr_write(u32 low, u32 id); | |
107 | extern u64 native_apic_icr_read(void); | |
108 | ||
8d806960 TG |
109 | static inline bool apic_is_x2apic_enabled(void) |
110 | { | |
111 | u64 msr; | |
112 | ||
113 | if (rdmsrl_safe(MSR_IA32_APICBASE, &msr)) | |
114 | return false; | |
115 | return msr & X2APIC_ENABLE; | |
116 | } | |
117 | ||
d0b03bd1 | 118 | #ifdef CONFIG_X86_X2APIC |
ce4e240c SS |
119 | /* |
120 | * Make previous memory operations globally visible before | |
121 | * sending the IPI through x2apic wrmsr. We need a serializing instruction or | |
122 | * mfence for this. | |
123 | */ | |
124 | static inline void x2apic_wrmsr_fence(void) | |
125 | { | |
126 | asm volatile("mfence" : : : "memory"); | |
127 | } | |
128 | ||
13c88fb5 SS |
129 | static inline void native_apic_msr_write(u32 reg, u32 v) |
130 | { | |
131 | if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || | |
132 | reg == APIC_LVR) | |
133 | return; | |
134 | ||
135 | wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); | |
136 | } | |
137 | ||
0ab711ae MT |
138 | static inline void native_apic_msr_eoi_write(u32 reg, u32 v) |
139 | { | |
140 | wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); | |
141 | } | |
142 | ||
13c88fb5 SS |
143 | static inline u32 native_apic_msr_read(u32 reg) |
144 | { | |
0059b243 | 145 | u64 msr; |
13c88fb5 SS |
146 | |
147 | if (reg == APIC_DFR) | |
148 | return -1; | |
149 | ||
0059b243 AK |
150 | rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); |
151 | return (u32)msr; | |
13c88fb5 SS |
152 | } |
153 | ||
c1eeb2de YL |
154 | static inline void native_x2apic_wait_icr_idle(void) |
155 | { | |
156 | /* no need to wait for icr idle in x2apic */ | |
157 | return; | |
158 | } | |
159 | ||
160 | static inline u32 native_safe_x2apic_wait_icr_idle(void) | |
161 | { | |
162 | /* no need to wait for icr idle in x2apic */ | |
163 | return 0; | |
164 | } | |
165 | ||
166 | static inline void native_x2apic_icr_write(u32 low, u32 id) | |
167 | { | |
168 | wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); | |
169 | } | |
170 | ||
171 | static inline u64 native_x2apic_icr_read(void) | |
172 | { | |
173 | unsigned long val; | |
174 | ||
175 | rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); | |
176 | return val; | |
177 | } | |
178 | ||
81a46dd8 | 179 | extern int x2apic_mode; |
fc1edaf9 | 180 | extern int x2apic_phys; |
d524165c | 181 | extern void __init check_x2apic(void); |
659006bf | 182 | extern void x2apic_setup(void); |
a11b5abe YL |
183 | static inline int x2apic_enabled(void) |
184 | { | |
8d806960 | 185 | return cpu_has_x2apic && apic_is_x2apic_enabled(); |
a11b5abe | 186 | } |
fc1edaf9 SS |
187 | |
188 | #define x2apic_supported() (cpu_has_x2apic) | |
a11b5abe | 189 | #else |
55eae7de | 190 | static inline void check_x2apic(void) { } |
659006bf | 191 | static inline void x2apic_setup(void) { } |
55eae7de | 192 | static inline int x2apic_enabled(void) { return 0; } |
cf6567fe | 193 | |
81a46dd8 | 194 | #define x2apic_mode (0) |
81a46dd8 | 195 | #define x2apic_supported() (0) |
c535b6a1 | 196 | #endif |
1b374e4d | 197 | |
93758238 WH |
198 | extern void enable_IR_x2apic(void); |
199 | ||
67c5fc5c TG |
200 | extern int get_physical_broadcast(void); |
201 | ||
67c5fc5c TG |
202 | extern int lapic_get_maxlvt(void); |
203 | extern void clear_local_APIC(void); | |
67c5fc5c TG |
204 | extern void disconnect_bsp_APIC(int virt_wire_setup); |
205 | extern void disable_local_APIC(void); | |
206 | extern void lapic_shutdown(void); | |
67c5fc5c TG |
207 | extern void sync_Arb_IDs(void); |
208 | extern void init_bsp_APIC(void); | |
209 | extern void setup_local_APIC(void); | |
210 | extern void init_apic_mappings(void); | |
c0104d38 | 211 | void register_lapic_address(unsigned long address); |
67c5fc5c TG |
212 | extern void setup_boot_APIC_clock(void); |
213 | extern void setup_secondary_APIC_clock(void); | |
214 | extern int APIC_init_uniprocessor(void); | |
b273c2c2 RRD |
215 | |
216 | #ifdef CONFIG_X86_64 | |
217 | static inline int apic_force_enable(unsigned long addr) | |
218 | { | |
219 | return -1; | |
220 | } | |
221 | #else | |
a906fdaa | 222 | extern int apic_force_enable(unsigned long addr); |
b273c2c2 | 223 | #endif |
67c5fc5c | 224 | |
374aab33 | 225 | extern int apic_bsp_setup(bool upmode); |
05f7e46d TG |
226 | extern void apic_ap_setup(void); |
227 | ||
67c5fc5c TG |
228 | /* |
229 | * On 32bit this is mach-xxx local | |
230 | */ | |
231 | #ifdef CONFIG_X86_64 | |
8fbbc4b4 AK |
232 | extern int apic_is_clustered_box(void); |
233 | #else | |
234 | static inline int apic_is_clustered_box(void) | |
235 | { | |
236 | return 0; | |
237 | } | |
67c5fc5c TG |
238 | #endif |
239 | ||
27afdf20 | 240 | extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); |
67c5fc5c TG |
241 | |
242 | #else /* !CONFIG_X86_LOCAL_APIC */ | |
243 | static inline void lapic_shutdown(void) { } | |
244 | #define local_apic_timer_c2_ok 1 | |
f3294a33 | 245 | static inline void init_apic_mappings(void) { } |
d3ec5cae | 246 | static inline void disable_local_APIC(void) { } |
736decac TG |
247 | # define setup_boot_APIC_clock x86_init_noop |
248 | # define setup_secondary_APIC_clock x86_init_noop | |
67c5fc5c TG |
249 | #endif /* !CONFIG_X86_LOCAL_APIC */ |
250 | ||
1f75ed0c IM |
251 | #ifdef CONFIG_X86_64 |
252 | #define SET_APIC_ID(x) (apic->set_apic_id(x)) | |
253 | #else | |
254 | ||
1f75ed0c IM |
255 | #endif |
256 | ||
e2780a68 IM |
257 | /* |
258 | * Copyright 2004 James Cleverdon, IBM. | |
259 | * Subject to the GNU Public License, v.2 | |
260 | * | |
261 | * Generic APIC sub-arch data struct. | |
262 | * | |
263 | * Hacked for x86-64 by James Cleverdon from i386 architecture code by | |
264 | * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and | |
265 | * James Cleverdon. | |
266 | */ | |
be163a15 | 267 | struct apic { |
e2780a68 IM |
268 | char *name; |
269 | ||
270 | int (*probe)(void); | |
271 | int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); | |
fa63030e | 272 | int (*apic_id_valid)(int apicid); |
e2780a68 IM |
273 | int (*apic_id_registered)(void); |
274 | ||
275 | u32 irq_delivery_mode; | |
276 | u32 irq_dest_mode; | |
277 | ||
278 | const struct cpumask *(*target_cpus)(void); | |
279 | ||
280 | int disable_esr; | |
281 | ||
282 | int dest_logical; | |
7abc0753 | 283 | unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid); |
e2780a68 | 284 | |
1ac322d0 SS |
285 | void (*vector_allocation_domain)(int cpu, struct cpumask *retmask, |
286 | const struct cpumask *mask); | |
e2780a68 IM |
287 | void (*init_apic_ldr)(void); |
288 | ||
7abc0753 | 289 | void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); |
e2780a68 IM |
290 | |
291 | void (*setup_apic_routing)(void); | |
e2780a68 | 292 | int (*cpu_present_to_apicid)(int mps_cpu); |
7abc0753 | 293 | void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap); |
e11dadab | 294 | int (*check_phys_apicid_present)(int phys_apicid); |
e2780a68 IM |
295 | int (*phys_pkg_id)(int cpuid_apic, int index_msb); |
296 | ||
e2780a68 IM |
297 | unsigned int (*get_apic_id)(unsigned long x); |
298 | unsigned long (*set_apic_id)(unsigned int id); | |
299 | unsigned long apic_id_mask; | |
300 | ||
ff164324 AG |
301 | int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask, |
302 | const struct cpumask *andmask, | |
303 | unsigned int *apicid); | |
e2780a68 IM |
304 | |
305 | /* ipi */ | |
306 | void (*send_IPI_mask)(const struct cpumask *mask, int vector); | |
307 | void (*send_IPI_mask_allbutself)(const struct cpumask *mask, | |
308 | int vector); | |
309 | void (*send_IPI_allbutself)(int vector); | |
310 | void (*send_IPI_all)(int vector); | |
311 | void (*send_IPI_self)(int vector); | |
312 | ||
313 | /* wakeup_secondary_cpu */ | |
1f5bcabf | 314 | int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); |
e2780a68 | 315 | |
465822cf | 316 | bool wait_for_init_deassert; |
e2780a68 IM |
317 | void (*inquire_remote_apic)(int apicid); |
318 | ||
319 | /* apic ops */ | |
320 | u32 (*read)(u32 reg); | |
321 | void (*write)(u32 reg, u32 v); | |
2a43195d MT |
322 | /* |
323 | * ->eoi_write() has the same signature as ->write(). | |
324 | * | |
325 | * Drivers can support both ->eoi_write() and ->write() by passing the same | |
326 | * callback value. Kernel can override ->eoi_write() and fall back | |
327 | * on write for EOI. | |
328 | */ | |
329 | void (*eoi_write)(u32 reg, u32 v); | |
e2780a68 IM |
330 | u64 (*icr_read)(void); |
331 | void (*icr_write)(u32 low, u32 high); | |
332 | void (*wait_icr_idle)(void); | |
333 | u32 (*safe_wait_icr_idle)(void); | |
acb8bc09 TH |
334 | |
335 | #ifdef CONFIG_X86_32 | |
336 | /* | |
337 | * Called very early during boot from get_smp_config(). It should | |
338 | * return the logical apicid. x86_[bios]_cpu_to_apicid is | |
339 | * initialized before this function is called. | |
340 | * | |
341 | * If logical apicid can't be determined that early, the function | |
342 | * may return BAD_APICID. Logical apicid will be configured after | |
343 | * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity | |
344 | * won't be applied properly during early boot in this case. | |
345 | */ | |
346 | int (*x86_32_early_logical_apicid)(int cpu); | |
347 | #endif | |
e2780a68 IM |
348 | }; |
349 | ||
0917c01f IM |
350 | /* |
351 | * Pointer to the local APIC driver in use on this system (there's | |
352 | * always just one such driver in use - the kernel decides via an | |
353 | * early probing process which one it picks - and then sticks to it): | |
354 | */ | |
be163a15 | 355 | extern struct apic *apic; |
0917c01f | 356 | |
107e0e0c SS |
357 | /* |
358 | * APIC drivers are probed based on how they are listed in the .apicdrivers | |
359 | * section. So the order is important and enforced by the ordering | |
360 | * of different apic driver files in the Makefile. | |
361 | * | |
362 | * For the files having two apic drivers, we use apic_drivers() | |
363 | * to enforce the order with in them. | |
364 | */ | |
365 | #define apic_driver(sym) \ | |
75fdd155 | 366 | static const struct apic *__apicdrivers_##sym __used \ |
107e0e0c SS |
367 | __aligned(sizeof(struct apic *)) \ |
368 | __section(.apicdrivers) = { &sym } | |
369 | ||
370 | #define apic_drivers(sym1, sym2) \ | |
371 | static struct apic *__apicdrivers_##sym1##sym2[2] __used \ | |
372 | __aligned(sizeof(struct apic *)) \ | |
373 | __section(.apicdrivers) = { &sym1, &sym2 } | |
374 | ||
375 | extern struct apic *__apicdrivers[], *__apicdrivers_end[]; | |
376 | ||
0917c01f IM |
377 | /* |
378 | * APIC functionality to boot other CPUs - only used on SMP: | |
379 | */ | |
380 | #ifdef CONFIG_SMP | |
2b6163bf YL |
381 | extern atomic_t init_deasserted; |
382 | extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip); | |
0917c01f | 383 | #endif |
e2780a68 | 384 | |
d674cd19 | 385 | #ifdef CONFIG_X86_LOCAL_APIC |
346b46be | 386 | |
e2780a68 IM |
387 | static inline u32 apic_read(u32 reg) |
388 | { | |
389 | return apic->read(reg); | |
390 | } | |
391 | ||
392 | static inline void apic_write(u32 reg, u32 val) | |
393 | { | |
394 | apic->write(reg, val); | |
395 | } | |
396 | ||
2a43195d MT |
397 | static inline void apic_eoi(void) |
398 | { | |
399 | apic->eoi_write(APIC_EOI, APIC_EOI_ACK); | |
400 | } | |
401 | ||
e2780a68 IM |
402 | static inline u64 apic_icr_read(void) |
403 | { | |
404 | return apic->icr_read(); | |
405 | } | |
406 | ||
407 | static inline void apic_icr_write(u32 low, u32 high) | |
408 | { | |
409 | apic->icr_write(low, high); | |
410 | } | |
411 | ||
412 | static inline void apic_wait_icr_idle(void) | |
413 | { | |
414 | apic->wait_icr_idle(); | |
415 | } | |
416 | ||
417 | static inline u32 safe_apic_wait_icr_idle(void) | |
418 | { | |
419 | return apic->safe_wait_icr_idle(); | |
420 | } | |
421 | ||
1551df64 MT |
422 | extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)); |
423 | ||
d674cd19 CG |
424 | #else /* CONFIG_X86_LOCAL_APIC */ |
425 | ||
426 | static inline u32 apic_read(u32 reg) { return 0; } | |
427 | static inline void apic_write(u32 reg, u32 val) { } | |
2a43195d | 428 | static inline void apic_eoi(void) { } |
d674cd19 CG |
429 | static inline u64 apic_icr_read(void) { return 0; } |
430 | static inline void apic_icr_write(u32 low, u32 high) { } | |
431 | static inline void apic_wait_icr_idle(void) { } | |
432 | static inline u32 safe_apic_wait_icr_idle(void) { return 0; } | |
1551df64 | 433 | static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {} |
d674cd19 CG |
434 | |
435 | #endif /* CONFIG_X86_LOCAL_APIC */ | |
e2780a68 IM |
436 | |
437 | static inline void ack_APIC_irq(void) | |
438 | { | |
439 | /* | |
440 | * ack_APIC_irq() actually gets compiled as a single instruction | |
441 | * ... yummie. | |
442 | */ | |
2a43195d | 443 | apic_eoi(); |
e2780a68 IM |
444 | } |
445 | ||
446 | static inline unsigned default_get_apic_id(unsigned long x) | |
447 | { | |
448 | unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); | |
449 | ||
42937e81 | 450 | if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID)) |
e2780a68 IM |
451 | return (x >> 24) & 0xFF; |
452 | else | |
453 | return (x >> 24) & 0x0F; | |
454 | } | |
455 | ||
456 | /* | |
6ab1b27c | 457 | * Warm reset vector position: |
e2780a68 | 458 | */ |
6ab1b27c DR |
459 | #define TRAMPOLINE_PHYS_LOW 0x467 |
460 | #define TRAMPOLINE_PHYS_HIGH 0x469 | |
e2780a68 | 461 | |
2b6163bf | 462 | #ifdef CONFIG_X86_64 |
e2780a68 IM |
463 | extern void apic_send_IPI_self(int vector); |
464 | ||
e2780a68 IM |
465 | DECLARE_PER_CPU(int, x2apic_extra_bits); |
466 | ||
467 | extern int default_cpu_present_to_apicid(int mps_cpu); | |
e11dadab | 468 | extern int default_check_phys_apicid_present(int phys_apicid); |
e2780a68 IM |
469 | #endif |
470 | ||
838312be | 471 | extern void generic_bigsmp_probe(void); |
e2780a68 IM |
472 | |
473 | ||
474 | #ifdef CONFIG_X86_LOCAL_APIC | |
475 | ||
476 | #include <asm/smp.h> | |
477 | ||
478 | #define APIC_DFR_VALUE (APIC_DFR_FLAT) | |
479 | ||
480 | static inline const struct cpumask *default_target_cpus(void) | |
481 | { | |
482 | #ifdef CONFIG_SMP | |
483 | return cpu_online_mask; | |
484 | #else | |
485 | return cpumask_of(0); | |
486 | #endif | |
487 | } | |
488 | ||
bf721d3a AG |
489 | static inline const struct cpumask *online_target_cpus(void) |
490 | { | |
491 | return cpu_online_mask; | |
492 | } | |
493 | ||
0816b0f0 | 494 | DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid); |
e2780a68 IM |
495 | |
496 | ||
497 | static inline unsigned int read_apic_id(void) | |
498 | { | |
499 | unsigned int reg; | |
500 | ||
501 | reg = apic_read(APIC_ID); | |
502 | ||
503 | return apic->get_apic_id(reg); | |
504 | } | |
505 | ||
fa63030e DB |
506 | static inline int default_apic_id_valid(int apicid) |
507 | { | |
b7157acf | 508 | return (apicid < 255); |
fa63030e DB |
509 | } |
510 | ||
a491cc90 JL |
511 | extern int default_acpi_madt_oem_check(char *, char *); |
512 | ||
e2780a68 IM |
513 | extern void default_setup_apic_routing(void); |
514 | ||
9844ab11 CG |
515 | extern struct apic apic_noop; |
516 | ||
e2780a68 | 517 | #ifdef CONFIG_X86_32 |
2c1b284e | 518 | |
acb8bc09 TH |
519 | static inline int noop_x86_32_early_logical_apicid(int cpu) |
520 | { | |
521 | return BAD_APICID; | |
522 | } | |
523 | ||
e2780a68 IM |
524 | /* |
525 | * Set up the logical destination ID. | |
526 | * | |
527 | * Intel recommends to set DFR, LDR and TPR before enabling | |
528 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
529 | * document number 292116). So here it goes... | |
530 | */ | |
531 | extern void default_init_apic_ldr(void); | |
532 | ||
533 | static inline int default_apic_id_registered(void) | |
534 | { | |
535 | return physid_isset(read_apic_id(), phys_cpu_present_map); | |
536 | } | |
537 | ||
f56e5034 YL |
538 | static inline int default_phys_pkg_id(int cpuid_apic, int index_msb) |
539 | { | |
540 | return cpuid_apic >> index_msb; | |
541 | } | |
542 | ||
f56e5034 YL |
543 | #endif |
544 | ||
ff164324 | 545 | static inline int |
a5a39156 AG |
546 | flat_cpu_mask_to_apicid_and(const struct cpumask *cpumask, |
547 | const struct cpumask *andmask, | |
548 | unsigned int *apicid) | |
e2780a68 | 549 | { |
a5a39156 AG |
550 | unsigned long cpu_mask = cpumask_bits(cpumask)[0] & |
551 | cpumask_bits(andmask)[0] & | |
552 | cpumask_bits(cpu_online_mask)[0] & | |
553 | APIC_ALL_CPUS; | |
554 | ||
ff164324 AG |
555 | if (likely(cpu_mask)) { |
556 | *apicid = (unsigned int)cpu_mask; | |
557 | return 0; | |
558 | } else { | |
559 | return -EINVAL; | |
560 | } | |
561 | } | |
562 | ||
ff164324 | 563 | extern int |
6398268d | 564 | default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, |
ff164324 AG |
565 | const struct cpumask *andmask, |
566 | unsigned int *apicid); | |
6398268d | 567 | |
b39f25a8 | 568 | static inline void |
1ac322d0 SS |
569 | flat_vector_allocation_domain(int cpu, struct cpumask *retmask, |
570 | const struct cpumask *mask) | |
9d8e1066 AG |
571 | { |
572 | /* Careful. Some cpus do not strictly honor the set of cpus | |
573 | * specified in the interrupt destination when using lowest | |
574 | * priority interrupt delivery mode. | |
575 | * | |
576 | * In particular there was a hyperthreading cpu observed to | |
577 | * deliver interrupts to the wrong hyperthread when only one | |
578 | * hyperthread was specified in the interrupt desitination. | |
579 | */ | |
580 | cpumask_clear(retmask); | |
581 | cpumask_bits(retmask)[0] = APIC_ALL_CPUS; | |
582 | } | |
583 | ||
b39f25a8 | 584 | static inline void |
1ac322d0 SS |
585 | default_vector_allocation_domain(int cpu, struct cpumask *retmask, |
586 | const struct cpumask *mask) | |
9d8e1066 AG |
587 | { |
588 | cpumask_copy(retmask, cpumask_of(cpu)); | |
589 | } | |
590 | ||
7abc0753 | 591 | static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid) |
e2780a68 | 592 | { |
7abc0753 | 593 | return physid_isset(apicid, *map); |
e2780a68 IM |
594 | } |
595 | ||
7abc0753 | 596 | static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap) |
e2780a68 | 597 | { |
7abc0753 | 598 | *retmap = *phys_map; |
e2780a68 IM |
599 | } |
600 | ||
e2780a68 IM |
601 | static inline int __default_cpu_present_to_apicid(int mps_cpu) |
602 | { | |
603 | if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) | |
604 | return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); | |
605 | else | |
606 | return BAD_APICID; | |
607 | } | |
608 | ||
609 | static inline int | |
e11dadab | 610 | __default_check_phys_apicid_present(int phys_apicid) |
e2780a68 | 611 | { |
e11dadab | 612 | return physid_isset(phys_apicid, phys_cpu_present_map); |
e2780a68 IM |
613 | } |
614 | ||
615 | #ifdef CONFIG_X86_32 | |
616 | static inline int default_cpu_present_to_apicid(int mps_cpu) | |
617 | { | |
618 | return __default_cpu_present_to_apicid(mps_cpu); | |
619 | } | |
620 | ||
621 | static inline int | |
e11dadab | 622 | default_check_phys_apicid_present(int phys_apicid) |
e2780a68 | 623 | { |
e11dadab | 624 | return __default_check_phys_apicid_present(phys_apicid); |
e2780a68 IM |
625 | } |
626 | #else | |
627 | extern int default_cpu_present_to_apicid(int mps_cpu); | |
e11dadab | 628 | extern int default_check_phys_apicid_present(int phys_apicid); |
e2780a68 IM |
629 | #endif |
630 | ||
e2780a68 | 631 | #endif /* CONFIG_X86_LOCAL_APIC */ |
eddc0e92 SA |
632 | extern void irq_enter(void); |
633 | extern void irq_exit(void); | |
634 | ||
635 | static inline void entering_irq(void) | |
636 | { | |
637 | irq_enter(); | |
638 | exit_idle(); | |
639 | } | |
640 | ||
641 | static inline void entering_ack_irq(void) | |
642 | { | |
643 | ack_APIC_irq(); | |
644 | entering_irq(); | |
645 | } | |
646 | ||
6dc17876 TG |
647 | static inline void ipi_entering_ack_irq(void) |
648 | { | |
649 | ack_APIC_irq(); | |
650 | irq_enter(); | |
651 | } | |
652 | ||
eddc0e92 SA |
653 | static inline void exiting_irq(void) |
654 | { | |
655 | irq_exit(); | |
656 | } | |
657 | ||
658 | static inline void exiting_ack_irq(void) | |
659 | { | |
660 | irq_exit(); | |
661 | /* Ack only at the end to avoid potential reentry */ | |
662 | ack_APIC_irq(); | |
663 | } | |
e2780a68 | 664 | |
17405453 YY |
665 | extern void ioapic_zap_locks(void); |
666 | ||
1965aae3 | 667 | #endif /* _ASM_X86_APIC_H */ |