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1965aae3 PA |
1 | #ifndef _ASM_X86_APIC_H |
2 | #define _ASM_X86_APIC_H | |
67c5fc5c TG |
3 | |
4 | #include <linux/pm.h> | |
5 | #include <linux/delay.h> | |
593f4a78 MR |
6 | |
7 | #include <asm/alternative.h> | |
67c5fc5c TG |
8 | #include <asm/fixmap.h> |
9 | #include <asm/apicdef.h> | |
10 | #include <asm/processor.h> | |
11 | #include <asm/system.h> | |
13c88fb5 SS |
12 | #include <asm/cpufeature.h> |
13 | #include <asm/msr.h> | |
67c5fc5c TG |
14 | |
15 | #define ARCH_APICTIMER_STOPS_ON_C3 1 | |
16 | ||
67c5fc5c TG |
17 | /* |
18 | * Debugging macros | |
19 | */ | |
20 | #define APIC_QUIET 0 | |
21 | #define APIC_VERBOSE 1 | |
22 | #define APIC_DEBUG 2 | |
23 | ||
24 | /* | |
25 | * Define the default level of output to be very little | |
26 | * This can be turned up by using apic=verbose for more | |
27 | * information and apic=debug for _lots_ of information. | |
28 | * apic_verbosity is defined in apic.c | |
29 | */ | |
30 | #define apic_printk(v, s, a...) do { \ | |
31 | if ((v) <= apic_verbosity) \ | |
32 | printk(s, ##a); \ | |
33 | } while (0) | |
34 | ||
35 | ||
36 | extern void generic_apic_probe(void); | |
37 | ||
38 | #ifdef CONFIG_X86_LOCAL_APIC | |
39 | ||
baa13188 | 40 | extern unsigned int apic_verbosity; |
67c5fc5c | 41 | extern int local_apic_timer_c2_ok; |
67c5fc5c | 42 | |
3c999f14 | 43 | extern int disable_apic; |
67c5fc5c TG |
44 | /* |
45 | * Basic functions accessing APICs. | |
46 | */ | |
47 | #ifdef CONFIG_PARAVIRT | |
48 | #include <asm/paravirt.h> | |
96a388de | 49 | #else |
67c5fc5c TG |
50 | #define setup_boot_clock setup_boot_APIC_clock |
51 | #define setup_secondary_clock setup_secondary_APIC_clock | |
96a388de | 52 | #endif |
67c5fc5c | 53 | |
aa7d8e25 | 54 | extern int is_vsmp_box(void); |
2b97df06 JS |
55 | extern void xapic_wait_icr_idle(void); |
56 | extern u32 safe_xapic_wait_icr_idle(void); | |
2b97df06 JS |
57 | extern void xapic_icr_write(u32, u32); |
58 | extern int setup_profiling_timer(unsigned int); | |
aa7d8e25 | 59 | |
1b374e4d | 60 | static inline void native_apic_mem_write(u32 reg, u32 v) |
67c5fc5c | 61 | { |
593f4a78 | 62 | volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); |
67c5fc5c | 63 | |
593f4a78 MR |
64 | alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP, |
65 | ASM_OUTPUT2("=r" (v), "=m" (*addr)), | |
66 | ASM_OUTPUT2("0" (v), "m" (*addr))); | |
67c5fc5c TG |
67 | } |
68 | ||
1b374e4d | 69 | static inline u32 native_apic_mem_read(u32 reg) |
67c5fc5c TG |
70 | { |
71 | return *((volatile u32 *)(APIC_BASE + reg)); | |
72 | } | |
73 | ||
13c88fb5 SS |
74 | static inline void native_apic_msr_write(u32 reg, u32 v) |
75 | { | |
76 | if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || | |
77 | reg == APIC_LVR) | |
78 | return; | |
79 | ||
80 | wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); | |
81 | } | |
82 | ||
83 | static inline u32 native_apic_msr_read(u32 reg) | |
84 | { | |
85 | u32 low, high; | |
86 | ||
87 | if (reg == APIC_DFR) | |
88 | return -1; | |
89 | ||
90 | rdmsr(APIC_BASE_MSR + (reg >> 4), low, high); | |
91 | return low; | |
92 | } | |
93 | ||
c535b6a1 | 94 | #ifndef CONFIG_X86_32 |
b6b301aa | 95 | extern int x2apic; |
6e1cb38a SS |
96 | extern void check_x2apic(void); |
97 | extern void enable_x2apic(void); | |
98 | extern void enable_IR_x2apic(void); | |
99 | extern void x2apic_icr_write(u32 low, u32 id); | |
a11b5abe YL |
100 | static inline int x2apic_enabled(void) |
101 | { | |
102 | int msr, msr2; | |
103 | ||
104 | if (!cpu_has_x2apic) | |
105 | return 0; | |
106 | ||
107 | rdmsr(MSR_IA32_APICBASE, msr, msr2); | |
108 | if (msr & X2APIC_ENABLE) | |
109 | return 1; | |
110 | return 0; | |
111 | } | |
112 | #else | |
113 | #define x2apic_enabled() 0 | |
c535b6a1 | 114 | #endif |
1b374e4d SS |
115 | |
116 | struct apic_ops { | |
117 | u32 (*read)(u32 reg); | |
118 | void (*write)(u32 reg, u32 v); | |
1b374e4d SS |
119 | u64 (*icr_read)(void); |
120 | void (*icr_write)(u32 low, u32 high); | |
121 | void (*wait_icr_idle)(void); | |
122 | u32 (*safe_wait_icr_idle)(void); | |
123 | }; | |
124 | ||
125 | extern struct apic_ops *apic_ops; | |
126 | ||
127 | #define apic_read (apic_ops->read) | |
128 | #define apic_write (apic_ops->write) | |
1b374e4d SS |
129 | #define apic_icr_read (apic_ops->icr_read) |
130 | #define apic_icr_write (apic_ops->icr_write) | |
131 | #define apic_wait_icr_idle (apic_ops->wait_icr_idle) | |
132 | #define safe_apic_wait_icr_idle (apic_ops->safe_wait_icr_idle) | |
1b374e4d | 133 | |
67c5fc5c TG |
134 | extern int get_physical_broadcast(void); |
135 | ||
89027d35 SS |
136 | #ifdef CONFIG_X86_64 |
137 | static inline void ack_x2APIC_irq(void) | |
138 | { | |
139 | /* Docs say use 0 for future compatibility */ | |
140 | native_apic_msr_write(APIC_EOI, 0); | |
141 | } | |
142 | #endif | |
143 | ||
144 | ||
67c5fc5c TG |
145 | static inline void ack_APIC_irq(void) |
146 | { | |
147 | /* | |
0791e13f | 148 | * ack_APIC_irq() actually gets compiled as a single instruction |
67c5fc5c TG |
149 | * ... yummie. |
150 | */ | |
151 | ||
152 | /* Docs say use 0 for future compatibility */ | |
593f4a78 | 153 | apic_write(APIC_EOI, 0); |
67c5fc5c TG |
154 | } |
155 | ||
156 | extern int lapic_get_maxlvt(void); | |
157 | extern void clear_local_APIC(void); | |
158 | extern void connect_bsp_APIC(void); | |
159 | extern void disconnect_bsp_APIC(int virt_wire_setup); | |
160 | extern void disable_local_APIC(void); | |
161 | extern void lapic_shutdown(void); | |
162 | extern int verify_local_APIC(void); | |
163 | extern void cache_APIC_registers(void); | |
164 | extern void sync_Arb_IDs(void); | |
165 | extern void init_bsp_APIC(void); | |
166 | extern void setup_local_APIC(void); | |
739f33b3 | 167 | extern void end_local_APIC_setup(void); |
67c5fc5c | 168 | extern void init_apic_mappings(void); |
67c5fc5c TG |
169 | extern void setup_boot_APIC_clock(void); |
170 | extern void setup_secondary_APIC_clock(void); | |
171 | extern int APIC_init_uniprocessor(void); | |
e9427101 | 172 | extern void enable_NMI_through_LVT0(void); |
67c5fc5c TG |
173 | |
174 | /* | |
175 | * On 32bit this is mach-xxx local | |
176 | */ | |
177 | #ifdef CONFIG_X86_64 | |
8643f9d0 | 178 | extern void early_init_lapic_mapping(void); |
8fbbc4b4 AK |
179 | extern int apic_is_clustered_box(void); |
180 | #else | |
181 | static inline int apic_is_clustered_box(void) | |
182 | { | |
183 | return 0; | |
184 | } | |
67c5fc5c TG |
185 | #endif |
186 | ||
7b83dae7 RR |
187 | extern u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask); |
188 | extern u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask); | |
67c5fc5c | 189 | |
67c5fc5c TG |
190 | |
191 | #else /* !CONFIG_X86_LOCAL_APIC */ | |
192 | static inline void lapic_shutdown(void) { } | |
193 | #define local_apic_timer_c2_ok 1 | |
f3294a33 | 194 | static inline void init_apic_mappings(void) { } |
d3ec5cae | 195 | static inline void disable_local_APIC(void) { } |
67c5fc5c TG |
196 | |
197 | #endif /* !CONFIG_X86_LOCAL_APIC */ | |
198 | ||
1965aae3 | 199 | #endif /* _ASM_X86_APIC_H */ |