[deliverable/linux.git] / arch / x86 / include / asm / apicdef.h

#ifndef _ASM_X86_APICDEF_H
#define _ASM_X86_APICDEF_H

/*
 * Constants for various Intel APICs. (local APIC, IOAPIC, etc.)
 *
 * Alan Cox <Alan.Cox@linux.org>, 1995.
 * Ingo Molnar <mingo@redhat.com>, 1999, 2000
 */

#define IO_APIC_DEFAULT_PHYS_BASE	0xfec00000
#define	APIC_DEFAULT_PHYS_BASE		0xfee00000

/*
 * This is the IO-APIC register space as specified
 * by Intel docs:
 */
#define IO_APIC_SLOT_SIZE		1024

#define	APIC_ID		0x20

#define	APIC_LVR	0x30
#define		APIC_LVR_MASK		0xFF00FF
#define		APIC_LVR_DIRECTED_EOI	(1 << 24)
#define		GET_APIC_VERSION(x)	((x) & 0xFFu)
#define		GET_APIC_MAXLVT(x)	(((x) >> 16) & 0xFFu)
#ifdef CONFIG_X86_32
#  define	APIC_INTEGRATED(x)	((x) & 0xF0u)
#else
#  define	APIC_INTEGRATED(x)	(1)
#endif
#define		APIC_XAPIC(x)		((x) >= 0x14)
#define		APIC_EXT_SPACE(x)	((x) & 0x80000000)
#define	APIC_TASKPRI	0x80
#define		APIC_TPRI_MASK		0xFFu
#define	APIC_ARBPRI	0x90
#define		APIC_ARBPRI_MASK	0xFFu
#define	APIC_PROCPRI	0xA0
#define	APIC_EOI	0xB0
#define		APIC_EIO_ACK		0x0
#define	APIC_RRR	0xC0
#define	APIC_LDR	0xD0
#define		APIC_LDR_MASK		(0xFFu << 24)
#define		GET_APIC_LOGICAL_ID(x)	(((x) >> 24) & 0xFFu)
#define		SET_APIC_LOGICAL_ID(x)	(((x) << 24))
#define		APIC_ALL_CPUS		0xFFu
#define	APIC_DFR	0xE0
#define		APIC_DFR_CLUSTER		0x0FFFFFFFul
#define		APIC_DFR_FLAT			0xFFFFFFFFul
#define	APIC_SPIV	0xF0
#define		APIC_SPIV_DIRECTED_EOI		(1 << 12)
#define		APIC_SPIV_FOCUS_DISABLED	(1 << 9)
#define		APIC_SPIV_APIC_ENABLED		(1 << 8)
#define	APIC_ISR	0x100
#define	APIC_ISR_NR     0x8     /* Number of 32 bit ISR registers. */
#define	APIC_TMR	0x180
#define	APIC_IRR	0x200
#define	APIC_ESR	0x280
#define		APIC_ESR_SEND_CS	0x00001
#define		APIC_ESR_RECV_CS	0x00002
#define		APIC_ESR_SEND_ACC	0x00004
#define		APIC_ESR_RECV_ACC	0x00008
#define		APIC_ESR_SENDILL	0x00020
#define		APIC_ESR_RECVILL	0x00040
#define		APIC_ESR_ILLREGA	0x00080
#define 	APIC_LVTCMCI	0x2f0
#define	APIC_ICR	0x300
#define		APIC_DEST_SELF		0x40000
#define		APIC_DEST_ALLINC	0x80000
#define		APIC_DEST_ALLBUT	0xC0000
#define		APIC_ICR_RR_MASK	0x30000
#define		APIC_ICR_RR_INVALID	0x00000
#define		APIC_ICR_RR_INPROG	0x10000
#define		APIC_ICR_RR_VALID	0x20000
#define		APIC_INT_LEVELTRIG	0x08000
#define		APIC_INT_ASSERT		0x04000
#define		APIC_ICR_BUSY		0x01000
#define		APIC_DEST_LOGICAL	0x00800
#define		APIC_DEST_PHYSICAL	0x00000
#define		APIC_DM_FIXED		0x00000
#define		APIC_DM_FIXED_MASK	0x00700
#define		APIC_DM_LOWEST		0x00100
#define		APIC_DM_SMI		0x00200
#define		APIC_DM_REMRD		0x00300
#define		APIC_DM_NMI		0x00400
#define		APIC_DM_INIT		0x00500
#define		APIC_DM_STARTUP		0x00600
#define		APIC_DM_EXTINT		0x00700
#define		APIC_VECTOR_MASK	0x000FF
#define	APIC_ICR2	0x310
#define		GET_APIC_DEST_FIELD(x)	(((x) >> 24) & 0xFF)
#define		SET_APIC_DEST_FIELD(x)	((x) << 24)
#define	APIC_LVTT	0x320
#define	APIC_LVTTHMR	0x330
#define	APIC_LVTPC	0x340
#define	APIC_LVT0	0x350
#define		APIC_LVT_TIMER_BASE_MASK	(0x3 << 18)
#define		GET_APIC_TIMER_BASE(x)		(((x) >> 18) & 0x3)
#define		SET_APIC_TIMER_BASE(x)		(((x) << 18))
#define		APIC_TIMER_BASE_CLKIN		0x0
#define		APIC_TIMER_BASE_TMBASE		0x1
#define		APIC_TIMER_BASE_DIV		0x2
#define		APIC_LVT_TIMER_PERIODIC		(1 << 17)
#define		APIC_LVT_MASKED			(1 << 16)
#define		APIC_LVT_LEVEL_TRIGGER		(1 << 15)
#define		APIC_LVT_REMOTE_IRR		(1 << 14)
#define		APIC_INPUT_POLARITY		(1 << 13)
#define		APIC_SEND_PENDING		(1 << 12)
#define		APIC_MODE_MASK			0x700
#define		GET_APIC_DELIVERY_MODE(x)	(((x) >> 8) & 0x7)
#define		SET_APIC_DELIVERY_MODE(x, y)	(((x) & ~0x700) | ((y) << 8))
#define			APIC_MODE_FIXED		0x0
#define			APIC_MODE_NMI		0x4
#define			APIC_MODE_EXTINT	0x7
#define	APIC_LVT1	0x360
#define	APIC_LVTERR	0x370
#define	APIC_TMICT	0x380
#define	APIC_TMCCT	0x390
#define	APIC_TDCR	0x3E0
#define APIC_SELF_IPI	0x3F0
#define		APIC_TDR_DIV_TMBASE	(1 << 2)
#define		APIC_TDR_DIV_1		0xB
#define		APIC_TDR_DIV_2		0x0
#define		APIC_TDR_DIV_4		0x1
#define		APIC_TDR_DIV_8		0x2
#define		APIC_TDR_DIV_16		0x3
#define		APIC_TDR_DIV_32		0x8
#define		APIC_TDR_DIV_64		0x9
#define		APIC_TDR_DIV_128	0xA
#define	APIC_EFEAT	0x400
#define	APIC_ECTRL	0x410
#define APIC_EILVTn(n)	(0x500 + 0x10 * n)
#define		APIC_EILVT_NR_AMD_K8	1	/* # of extended interrupts */
#define		APIC_EILVT_NR_AMD_10H	4
#define		APIC_EILVT_NR_MAX	APIC_EILVT_NR_AMD_10H
#define		APIC_EILVT_LVTOFF(x)	(((x) >> 4) & 0xF)
#define		APIC_EILVT_MSG_FIX	0x0
#define		APIC_EILVT_MSG_SMI	0x2
#define		APIC_EILVT_MSG_NMI	0x4
#define		APIC_EILVT_MSG_EXT	0x7
#define		APIC_EILVT_MASKED	(1 << 16)

#define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
#define APIC_BASE_MSR	0x800
#define X2APIC_ENABLE	(1UL << 10)

#ifdef CONFIG_X86_32
# define MAX_IO_APICS 64
# define MAX_LOCAL_APIC 256
#else
# define MAX_IO_APICS 128
# define MAX_LOCAL_APIC 32768
#endif

/*
 * All x86-64 systems are xAPIC compatible.
 * In the following, "apicid" is a physical APIC ID.
 */
#define XAPIC_DEST_CPUS_SHIFT	4
#define XAPIC_DEST_CPUS_MASK	((1u << XAPIC_DEST_CPUS_SHIFT) - 1)
#define XAPIC_DEST_CLUSTER_MASK	(XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT)
#define APIC_CLUSTER(apicid)	((apicid) & XAPIC_DEST_CLUSTER_MASK)
#define APIC_CLUSTERID(apicid)	(APIC_CLUSTER(apicid) >> XAPIC_DEST_CPUS_SHIFT)
#define APIC_CPUID(apicid)	((apicid) & XAPIC_DEST_CPUS_MASK)
#define NUM_APIC_CLUSTERS	((BAD_APICID + 1) >> XAPIC_DEST_CPUS_SHIFT)

/*
 * the local APIC register structure, memory mapped. Not terribly well
 * tested, but we might eventually use this one in the future - the
 * problem why we cannot use it right now is the P5 APIC, it has an
 * errata which cannot take 8-bit reads and writes, only 32-bit ones ...
 */
#define u32 unsigned int

struct local_apic {

/*000*/	struct { u32 __reserved[4]; } __reserved_01;

/*010*/	struct { u32 __reserved[4]; } __reserved_02;

/*020*/	struct { /* APIC ID Register */
		u32   __reserved_1	: 24,
			phys_apic_id	:  4,
			__reserved_2	:  4;
		u32 __reserved[3];
	} id;

/*030*/	const
	struct { /* APIC Version Register */
		u32   version		:  8,
			__reserved_1	:  8,
			max_lvt		:  8,
			__reserved_2	:  8;
		u32 __reserved[3];
	} version;

/*040*/	struct { u32 __reserved[4]; } __reserved_03;

/*050*/	struct { u32 __reserved[4]; } __reserved_04;

/*060*/	struct { u32 __reserved[4]; } __reserved_05;

/*070*/	struct { u32 __reserved[4]; } __reserved_06;

/*080*/	struct { /* Task Priority Register */
		u32   priority	:  8,
			__reserved_1	: 24;
		u32 __reserved_2[3];
	} tpr;

/*090*/	const
	struct { /* Arbitration Priority Register */
		u32   priority	:  8,
			__reserved_1	: 24;
		u32 __reserved_2[3];
	} apr;

/*0A0*/	const
	struct { /* Processor Priority Register */
		u32   priority	:  8,
			__reserved_1	: 24;
		u32 __reserved_2[3];
	} ppr;

/*0B0*/	struct { /* End Of Interrupt Register */
		u32   eoi;
		u32 __reserved[3];
	} eoi;

/*0C0*/	struct { u32 __reserved[4]; } __reserved_07;

/*0D0*/	struct { /* Logical Destination Register */
		u32   __reserved_1	: 24,
			logical_dest	:  8;
		u32 __reserved_2[3];
	} ldr;

/*0E0*/	struct { /* Destination Format Register */
		u32   __reserved_1	: 28,
			model		:  4;
		u32 __reserved_2[3];
	} dfr;

/*0F0*/	struct { /* Spurious Interrupt Vector Register */
		u32	spurious_vector	:  8,
			apic_enabled	:  1,
			focus_cpu	:  1,
			__reserved_2	: 22;
		u32 __reserved_3[3];
	} svr;

/*100*/	struct { /* In Service Register */
/*170*/		u32 bitfield;
		u32 __reserved[3];
	} isr [8];

/*180*/	struct { /* Trigger Mode Register */
/*1F0*/		u32 bitfield;
		u32 __reserved[3];
	} tmr [8];

/*200*/	struct { /* Interrupt Request Register */
/*270*/		u32 bitfield;
		u32 __reserved[3];
	} irr [8];

/*280*/	union { /* Error Status Register */
		struct {
			u32   send_cs_error			:  1,
				receive_cs_error		:  1,
				send_accept_error		:  1,
				receive_accept_error		:  1,
				__reserved_1			:  1,
				send_illegal_vector		:  1,
				receive_illegal_vector		:  1,
				illegal_register_address	:  1,
				__reserved_2			: 24;
			u32 __reserved_3[3];
		} error_bits;
		struct {
			u32 errors;
			u32 __reserved_3[3];
		} all_errors;
	} esr;

/*290*/	struct { u32 __reserved[4]; } __reserved_08;

/*2A0*/	struct { u32 __reserved[4]; } __reserved_09;

/*2B0*/	struct { u32 __reserved[4]; } __reserved_10;

/*2C0*/	struct { u32 __reserved[4]; } __reserved_11;

/*2D0*/	struct { u32 __reserved[4]; } __reserved_12;

/*2E0*/	struct { u32 __reserved[4]; } __reserved_13;

/*2F0*/	struct { u32 __reserved[4]; } __reserved_14;

/*300*/	struct { /* Interrupt Command Register 1 */
		u32   vector			:  8,
			delivery_mode		:  3,
			destination_mode	:  1,
			delivery_status		:  1,
			__reserved_1		:  1,
			level			:  1,
			trigger			:  1,
			__reserved_2		:  2,
			shorthand		:  2,
			__reserved_3		:  12;
		u32 __reserved_4[3];
	} icr1;

/*310*/	struct { /* Interrupt Command Register 2 */
		union {
			u32   __reserved_1	: 24,
				phys_dest	:  4,
				__reserved_2	:  4;
			u32   __reserved_3	: 24,
				logical_dest	:  8;
		} dest;
		u32 __reserved_4[3];
	} icr2;

/*320*/	struct { /* LVT - Timer */
		u32   vector		:  8,
			__reserved_1	:  4,
			delivery_status	:  1,
			__reserved_2	:  3,
			mask		:  1,
			timer_mode	:  1,
			__reserved_3	: 14;
		u32 __reserved_4[3];
	} lvt_timer;

/*330*/	struct { /* LVT - Thermal Sensor */
		u32  vector		:  8,
			delivery_mode	:  3,
			__reserved_1	:  1,
			delivery_status	:  1,
			__reserved_2	:  3,
			mask		:  1,
			__reserved_3	: 15;
		u32 __reserved_4[3];
	} lvt_thermal;

/*340*/	struct { /* LVT - Performance Counter */
		u32   vector		:  8,
			delivery_mode	:  3,
			__reserved_1	:  1,
			delivery_status	:  1,
			__reserved_2	:  3,
			mask		:  1,
			__reserved_3	: 15;
		u32 __reserved_4[3];
	} lvt_pc;

/*350*/	struct { /* LVT - LINT0 */
		u32   vector		:  8,
			delivery_mode	:  3,
			__reserved_1	:  1,
			delivery_status	:  1,
			polarity	:  1,
			remote_irr	:  1,
			trigger		:  1,
			mask		:  1,
			__reserved_2	: 15;
		u32 __reserved_3[3];
	} lvt_lint0;

/*360*/	struct { /* LVT - LINT1 */
		u32   vector		:  8,
			delivery_mode	:  3,
			__reserved_1	:  1,
			delivery_status	:  1,
			polarity	:  1,
			remote_irr	:  1,
			trigger		:  1,
			mask		:  1,
			__reserved_2	: 15;
		u32 __reserved_3[3];
	} lvt_lint1;

/*370*/	struct { /* LVT - Error */
		u32   vector		:  8,
			__reserved_1	:  4,
			delivery_status	:  1,
			__reserved_2	:  3,
			mask		:  1,
			__reserved_3	: 15;
		u32 __reserved_4[3];
	} lvt_error;

/*380*/	struct { /* Timer Initial Count Register */
		u32   initial_count;
		u32 __reserved_2[3];
	} timer_icr;

/*390*/	const
	struct { /* Timer Current Count Register */
		u32   curr_count;
		u32 __reserved_2[3];
	} timer_ccr;

/*3A0*/	struct { u32 __reserved[4]; } __reserved_16;

/*3B0*/	struct { u32 __reserved[4]; } __reserved_17;

/*3C0*/	struct { u32 __reserved[4]; } __reserved_18;

/*3D0*/	struct { u32 __reserved[4]; } __reserved_19;

/*3E0*/	struct { /* Timer Divide Configuration Register */
		u32   divisor		:  4,
			__reserved_1	: 28;
		u32 __reserved_2[3];
	} timer_dcr;

/*3F0*/	struct { u32 __reserved[4]; } __reserved_20;

} __attribute__ ((packed));

#undef u32

#ifdef CONFIG_X86_32
 #define BAD_APICID 0xFFu
#else
 #define BAD_APICID 0xFFFFu
#endif

enum ioapic_irq_destination_types {
	dest_Fixed		= 0,
	dest_LowestPrio		= 1,
	dest_SMI		= 2,
	dest__reserved_1	= 3,
	dest_NMI		= 4,
	dest_INIT		= 5,
	dest__reserved_2	= 6,
	dest_ExtINT		= 7
};

#endif /* _ASM_X86_APICDEF_H */
Commit	Line	Data
1965aae3 PA	1	#ifndef _ASM_X86_APICDEF_H
1965aae3 PA	2	#define _ASM_X86_APICDEF_H
2d539553 TG	3
	4	/*
	5	* Constants for various Intel APICs. (local APIC, IOAPIC, etc.)
	6	*
	7	* Alan Cox <Alan.Cox@linux.org>, 1995.
	8	* Ingo Molnar <mingo@redhat.com>, 1999, 2000
	9	*/
	10
8f3e1df4 CG	11	#define IO_APIC_DEFAULT_PHYS_BASE 0xfec00000
8f3e1df4 CG	12	#define APIC_DEFAULT_PHYS_BASE 0xfee00000
2d539553	13
e79c65a9 CG	14	/*
	15	* This is the IO-APIC register space as specified
	16	* by Intel docs:
	17	*/
	18	#define IO_APIC_SLOT_SIZE 1024
	19
2d539553 TG	20	#define APIC_ID 0x20
2d539553 TG	21
2d539553 TG	22	#define APIC_LVR 0x30
2d539553 TG	23	#define APIC_LVR_MASK 0xFF00FF
fc61b800	24	#define APIC_LVR_DIRECTED_EOI (1 << 24)
79a4a961 JP	25	#define GET_APIC_VERSION(x) ((x) & 0xFFu)
79a4a961 JP	26	#define GET_APIC_MAXLVT(x) (((x) >> 16) & 0xFFu)
ac56ef61	27	#ifdef CONFIG_X86_32
79a4a961	28	# define APIC_INTEGRATED(x) ((x) & 0xF0u)
ac56ef61 GOC	29	#else
	30	# define APIC_INTEGRATED(x) (1)
	31	#endif
2d539553	32	#define APIC_XAPIC(x) ((x) >= 0x14)
97a52714	33	#define APIC_EXT_SPACE(x) ((x) & 0x80000000)
2d539553 TG	34	#define APIC_TASKPRI 0x80
	35	#define APIC_TPRI_MASK 0xFFu
	36	#define APIC_ARBPRI 0x90
	37	#define APIC_ARBPRI_MASK 0xFFu
	38	#define APIC_PROCPRI 0xA0
	39	#define APIC_EOI 0xB0
	40	#define APIC_EIO_ACK 0x0
	41	#define APIC_RRR 0xC0
	42	#define APIC_LDR 0xD0
79a4a961 JP	43	#define APIC_LDR_MASK (0xFFu << 24)
	44	#define GET_APIC_LOGICAL_ID(x) (((x) >> 24) & 0xFFu)
	45	#define SET_APIC_LOGICAL_ID(x) (((x) << 24))
2d539553 TG	46	#define APIC_ALL_CPUS 0xFFu
	47	#define APIC_DFR 0xE0
	48	#define APIC_DFR_CLUSTER 0x0FFFFFFFul
	49	#define APIC_DFR_FLAT 0xFFFFFFFFul
	50	#define APIC_SPIV 0xF0
fc61b800	51	#define APIC_SPIV_DIRECTED_EOI (1 << 12)
79a4a961 JP	52	#define APIC_SPIV_FOCUS_DISABLED (1 << 9)
79a4a961 JP	53	#define APIC_SPIV_APIC_ENABLED (1 << 8)
2d539553 TG	54	#define APIC_ISR 0x100
	55	#define APIC_ISR_NR 0x8 /* Number of 32 bit ISR registers. */
	56	#define APIC_TMR 0x180
	57	#define APIC_IRR 0x200
	58	#define APIC_ESR 0x280
	59	#define APIC_ESR_SEND_CS 0x00001
	60	#define APIC_ESR_RECV_CS 0x00002
	61	#define APIC_ESR_SEND_ACC 0x00004
	62	#define APIC_ESR_RECV_ACC 0x00008
	63	#define APIC_ESR_SENDILL 0x00020
	64	#define APIC_ESR_RECVILL 0x00040
	65	#define APIC_ESR_ILLREGA 0x00080
03195c6b	66	#define APIC_LVTCMCI 0x2f0
2d539553 TG	67	#define APIC_ICR 0x300
	68	#define APIC_DEST_SELF 0x40000
	69	#define APIC_DEST_ALLINC 0x80000
	70	#define APIC_DEST_ALLBUT 0xC0000
	71	#define APIC_ICR_RR_MASK 0x30000
	72	#define APIC_ICR_RR_INVALID 0x00000
	73	#define APIC_ICR_RR_INPROG 0x10000
	74	#define APIC_ICR_RR_VALID 0x20000
	75	#define APIC_INT_LEVELTRIG 0x08000
	76	#define APIC_INT_ASSERT 0x04000
	77	#define APIC_ICR_BUSY 0x01000
	78	#define APIC_DEST_LOGICAL 0x00800
	79	#define APIC_DEST_PHYSICAL 0x00000
	80	#define APIC_DM_FIXED 0x00000
e503f9e4	81	#define APIC_DM_FIXED_MASK 0x00700
2d539553 TG	82	#define APIC_DM_LOWEST 0x00100
	83	#define APIC_DM_SMI 0x00200
	84	#define APIC_DM_REMRD 0x00300
	85	#define APIC_DM_NMI 0x00400
	86	#define APIC_DM_INIT 0x00500
	87	#define APIC_DM_STARTUP 0x00600
	88	#define APIC_DM_EXTINT 0x00700
	89	#define APIC_VECTOR_MASK 0x000FF
	90	#define APIC_ICR2 0x310
79a4a961 JP	91	#define GET_APIC_DEST_FIELD(x) (((x) >> 24) & 0xFF)
79a4a961 JP	92	#define SET_APIC_DEST_FIELD(x) ((x) << 24)
2d539553 TG	93	#define APIC_LVTT 0x320
	94	#define APIC_LVTTHMR 0x330
	95	#define APIC_LVTPC 0x340
	96	#define APIC_LVT0 0x350
79a4a961 JP	97	#define APIC_LVT_TIMER_BASE_MASK (0x3 << 18)
	98	#define GET_APIC_TIMER_BASE(x) (((x) >> 18) & 0x3)
	99	#define SET_APIC_TIMER_BASE(x) (((x) << 18))
2d539553 TG	100	#define APIC_TIMER_BASE_CLKIN 0x0
	101	#define APIC_TIMER_BASE_TMBASE 0x1
	102	#define APIC_TIMER_BASE_DIV 0x2
79a4a961 JP	103	#define APIC_LVT_TIMER_PERIODIC (1 << 17)
	104	#define APIC_LVT_MASKED (1 << 16)
	105	#define APIC_LVT_LEVEL_TRIGGER (1 << 15)
	106	#define APIC_LVT_REMOTE_IRR (1 << 14)
	107	#define APIC_INPUT_POLARITY (1 << 13)
	108	#define APIC_SEND_PENDING (1 << 12)
2d539553	109	#define APIC_MODE_MASK 0x700
79a4a961 JP	110	#define GET_APIC_DELIVERY_MODE(x) (((x) >> 8) & 0x7)
79a4a961 JP	111	#define SET_APIC_DELIVERY_MODE(x, y) (((x) & ~0x700) \| ((y) << 8))
2d539553 TG	112	#define APIC_MODE_FIXED 0x0
	113	#define APIC_MODE_NMI 0x4
	114	#define APIC_MODE_EXTINT 0x7
	115	#define APIC_LVT1 0x360
	116	#define APIC_LVTERR 0x370
	117	#define APIC_TMICT 0x380
	118	#define APIC_TMCCT 0x390
	119	#define APIC_TDCR 0x3E0
13c88fb5	120	#define APIC_SELF_IPI 0x3F0
79a4a961	121	#define APIC_TDR_DIV_TMBASE (1 << 2)
2d539553 TG	122	#define APIC_TDR_DIV_1 0xB
	123	#define APIC_TDR_DIV_2 0x0
	124	#define APIC_TDR_DIV_4 0x1
	125	#define APIC_TDR_DIV_8 0x2
	126	#define APIC_TDR_DIV_16 0x3
	127	#define APIC_TDR_DIV_32 0x8
	128	#define APIC_TDR_DIV_64 0x9
	129	#define APIC_TDR_DIV_128 0xA
97a52714 AH	130	#define APIC_EFEAT 0x400
	131	#define APIC_ECTRL 0x410
	132	#define APIC_EILVTn(n) (0x500 + 0x10 * n)
79a4a961	133	#define APIC_EILVT_NR_AMD_K8 1 /* # of extended interrupts */
7b83dae7	134	#define APIC_EILVT_NR_AMD_10H 4
a68c439b	135	#define APIC_EILVT_NR_MAX APIC_EILVT_NR_AMD_10H
79a4a961	136	#define APIC_EILVT_LVTOFF(x) (((x) >> 4) & 0xF)
7b83dae7 RR	137	#define APIC_EILVT_MSG_FIX 0x0
	138	#define APIC_EILVT_MSG_SMI 0x2
	139	#define APIC_EILVT_MSG_NMI 0x4
	140	#define APIC_EILVT_MSG_EXT 0x7
79a4a961	141	#define APIC_EILVT_MASKED (1 << 16)
cff90dbf	142
2d539553	143	#define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
13c88fb5 SS	144	#define APIC_BASE_MSR 0x800
13c88fb5 SS	145	#define X2APIC_ENABLE (1UL << 10)
2d539553	146
96a388de	147	#ifdef CONFIG_X86_32
2d539553	148	# define MAX_IO_APICS 64
56d91f13	149	# define MAX_LOCAL_APIC 256
96a388de	150	#else
2d539553	151	# define MAX_IO_APICS 128
a65d1d64	152	# define MAX_LOCAL_APIC 32768
2d539553 TG	153	#endif
	154
	155	/*
	156	* All x86-64 systems are xAPIC compatible.
	157	* In the following, "apicid" is a physical APIC ID.
	158	*/
	159	#define XAPIC_DEST_CPUS_SHIFT 4
	160	#define XAPIC_DEST_CPUS_MASK ((1u << XAPIC_DEST_CPUS_SHIFT) - 1)
	161	#define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT)
	162	#define APIC_CLUSTER(apicid) ((apicid) & XAPIC_DEST_CLUSTER_MASK)
	163	#define APIC_CLUSTERID(apicid) (APIC_CLUSTER(apicid) >> XAPIC_DEST_CPUS_SHIFT)
	164	#define APIC_CPUID(apicid) ((apicid) & XAPIC_DEST_CPUS_MASK)
	165	#define NUM_APIC_CLUSTERS ((BAD_APICID + 1) >> XAPIC_DEST_CPUS_SHIFT)
	166
	167	/*
	168	* the local APIC register structure, memory mapped. Not terribly well
	169	* tested, but we might eventually use this one in the future - the
	170	* problem why we cannot use it right now is the P5 APIC, it has an
	171	* errata which cannot take 8-bit reads and writes, only 32-bit ones ...
	172	*/
	173	#define u32 unsigned int
	174
	175	struct local_apic {
	176
	177	/000/ struct { u32 __reserved[4]; } __reserved_01;
	178
	179	/010/ struct { u32 __reserved[4]; } __reserved_02;
	180
	181	/020/ struct { /* APIC ID Register */
	182	u32 __reserved_1 : 24,
	183	phys_apic_id : 4,
	184	__reserved_2 : 4;
	185	u32 __reserved[3];
	186	} id;
	187
	188	/030/ const
	189	struct { /* APIC Version Register */
	190	u32 version : 8,
	191	__reserved_1 : 8,
	192	max_lvt : 8,
	193	__reserved_2 : 8;
	194	u32 __reserved[3];
	195	} version;
	196
	197	/040/ struct { u32 __reserved[4]; } __reserved_03;
	198
	199	/050/ struct { u32 __reserved[4]; } __reserved_04;
	200
	201	/060/ struct { u32 __reserved[4]; } __reserved_05;
	202
	203	/070/ struct { u32 __reserved[4]; } __reserved_06;
	204
	205	/080/ struct { /* Task Priority Register */
	206	u32 priority : 8,
	207	__reserved_1 : 24;
	208	u32 __reserved_2[3];
	209	} tpr;
	210
	211	/090/ const
	212	struct { /* Arbitration Priority Register */
	213	u32 priority : 8,
	214	__reserved_1 : 24;
	215	u32 __reserved_2[3];
	216	} apr;
217
218	/0A0/ const
219	struct { /* Processor Priority Register */
220	u32 priority : 8,
221	__reserved_1 : 24;
222	u32 __reserved_2[3];
223	} ppr;
224
225	/0B0/ struct { /* End Of Interrupt Register */
226	u32 eoi;
227	u32 __reserved[3];
228	} eoi;
229
230	/0C0/ struct { u32 __reserved[4]; } __reserved_07;
231
232	/0D0/ struct { /* Logical Destination Register */
233	u32 __reserved_1 : 24,
234	logical_dest : 8;
235	u32 __reserved_2[3];
236	} ldr;
237
238	/0E0/ struct { /* Destination Format Register */
239	u32 __reserved_1 : 28,
240	model : 4;
241	u32 __reserved_2[3];
242	} dfr;
243
244	/0F0/ struct { /* Spurious Interrupt Vector Register */
245	u32 spurious_vector : 8,
246	apic_enabled : 1,
247	focus_cpu : 1,
248	__reserved_2 : 22;
249	u32 __reserved_3[3];
250	} svr;
251
252	/100/ struct { /* In Service Register */
253	/170/ u32 bitfield;
254	u32 __reserved[3];
255	} isr [8];
256
257	/180/ struct { /* Trigger Mode Register */
258	/1F0/ u32 bitfield;
259	u32 __reserved[3];
260	} tmr [8];
261
262	/200/ struct { /* Interrupt Request Register */
263	/270/ u32 bitfield;
264	u32 __reserved[3];
265	} irr [8];
266
267	/280/ union { /* Error Status Register */
268	struct {
269	u32 send_cs_error : 1,
270	receive_cs_error : 1,
271	send_accept_error : 1,
272	receive_accept_error : 1,
273	__reserved_1 : 1,
274	send_illegal_vector : 1,
275	receive_illegal_vector : 1,
276	illegal_register_address : 1,
277	__reserved_2 : 24;
278	u32 __reserved_3[3];
279	} error_bits;
280	struct {
281	u32 errors;
282	u32 __reserved_3[3];
283	} all_errors;
284	} esr;
285
286	/290/ struct { u32 __reserved[4]; } __reserved_08;
287
288	/2A0/ struct { u32 __reserved[4]; } __reserved_09;
289
290	/2B0/ struct { u32 __reserved[4]; } __reserved_10;
291
292	/2C0/ struct { u32 __reserved[4]; } __reserved_11;
293
294	/2D0/ struct { u32 __reserved[4]; } __reserved_12;
295
296	/2E0/ struct { u32 __reserved[4]; } __reserved_13;
297
298	/2F0/ struct { u32 __reserved[4]; } __reserved_14;
299
300	/300/ struct { /* Interrupt Command Register 1 */
301	u32 vector : 8,
302	delivery_mode : 3,
303	destination_mode : 1,
304	delivery_status : 1,
305	__reserved_1 : 1,
306	level : 1,
307	trigger : 1,
308	__reserved_2 : 2,
309	shorthand : 2,
310	__reserved_3 : 12;
311	u32 __reserved_4[3];
312	} icr1;
313
314	/310/ struct { /* Interrupt Command Register 2 */
315	union {
316	u32 __reserved_1 : 24,
317	phys_dest : 4,
318	__reserved_2 : 4;
319	u32 __reserved_3 : 24,
320	logical_dest : 8;
321	} dest;
322	u32 __reserved_4[3];
323	} icr2;
324
325	/320/ struct { /* LVT - Timer */
326	u32 vector : 8,
327	__reserved_1 : 4,
328	delivery_status : 1,
329	__reserved_2 : 3,
330	mask : 1,
331	timer_mode : 1,
332	__reserved_3 : 14;
333	u32 __reserved_4[3];
334	} lvt_timer;
335
336	/330/ struct { /* LVT - Thermal Sensor */
337	u32 vector : 8,
338	delivery_mode : 3,
339	__reserved_1 : 1,
340	delivery_status : 1,
341	__reserved_2 : 3,
342	mask : 1,
343	__reserved_3 : 15;
344	u32 __reserved_4[3];
345	} lvt_thermal;
346
347	/340/ struct { /* LVT - Performance Counter */
348	u32 vector : 8,
349	delivery_mode : 3,
350	__reserved_1 : 1,
351	delivery_status : 1,
352	__reserved_2 : 3,
353	mask : 1,
354	__reserved_3 : 15;
355	u32 __reserved_4[3];
356	} lvt_pc;
357
358	/350/ struct { /* LVT - LINT0 */
359	u32 vector : 8,
360	delivery_mode : 3,
361	__reserved_1 : 1,
362	delivery_status : 1,
363	polarity : 1,
364	remote_irr : 1,
365	trigger : 1,
366	mask : 1,
367	__reserved_2 : 15;
368	u32 __reserved_3[3];
369	} lvt_lint0;
370
371	/360/ struct { /* LVT - LINT1 */
372	u32 vector : 8,
373	delivery_mode : 3,
374	__reserved_1 : 1,
375	delivery_status : 1,
376	polarity : 1,
377	remote_irr : 1,
378	trigger : 1,
379	mask : 1,
380	__reserved_2 : 15;
381	u32 __reserved_3[3];
382	} lvt_lint1;
383
384	/370/ struct { /* LVT - Error */
385	u32 vector : 8,
386	__reserved_1 : 4,
387	delivery_status : 1,
388	__reserved_2 : 3,
389	mask : 1,
390	__reserved_3 : 15;
391	u32 __reserved_4[3];
392	} lvt_error;
393
394	/380/ struct { /* Timer Initial Count Register */
395	u32 initial_count;
396	u32 __reserved_2[3];
397	} timer_icr;
398
399	/390/ const
400	struct { /* Timer Current Count Register */
401	u32 curr_count;
402	u32 __reserved_2[3];
403	} timer_ccr;
404
405	/3A0/ struct { u32 __reserved[4]; } __reserved_16;
406
407	/3B0/ struct { u32 __reserved[4]; } __reserved_17;
408
409	/3C0/ struct { u32 __reserved[4]; } __reserved_18;
410
411	/3D0/ struct { u32 __reserved[4]; } __reserved_19;
412
413	/3E0/ struct { /* Timer Divide Configuration Register */
414	u32 divisor : 4,
415	__reserved_1 : 28;
416	u32 __reserved_2[3];
417	} timer_dcr;
418
419	/3F0/ struct { u32 __reserved[4]; } __reserved_20;
420
421	} __attribute__ ((packed));
422
423	#undef u32
424
a65d1d64 JS	425	#ifdef CONFIG_X86_32
	426	#define BAD_APICID 0xFFu
	427	#else
	428	#define BAD_APICID 0xFFFFu
	429	#endif
4e034b24 HK	430
	431	enum ioapic_irq_destination_types {
	432	dest_Fixed = 0,
	433	dest_LowestPrio = 1,
	434	dest_SMI = 2,
	435	dest__reserved_1 = 3,
	436	dest_NMI = 4,
	437	dest_INIT = 5,
	438	dest__reserved_2 = 6,
	439	dest_ExtINT = 7
	440	};
	441
1965aae3	442	#endif /* _ASM_X86_APICDEF_H */