Commit | Line | Data |
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1176fa91 YL |
1 | #ifndef __ASM_MACH_APIC_H |
2 | #define __ASM_MACH_APIC_H | |
1855a2c4 | 3 | |
cbe879fc | 4 | #define xapic_phys_to_log_apicid(cpu) (per_cpu(x86_bios_cpu_apicid, cpu)) |
1da177e4 | 5 | |
7ed248da | 6 | static inline int bigsmp_apic_id_registered(void) |
1da177e4 | 7 | { |
7ed248da | 8 | return 1; |
1da177e4 LT |
9 | } |
10 | ||
0a9cc20b | 11 | static inline const cpumask_t *bigsmp_target_cpus(void) |
1176fa91 | 12 | { |
497c9a19 | 13 | #ifdef CONFIG_SMP |
e7986739 | 14 | return &cpu_online_map; |
497c9a19 | 15 | #else |
e7986739 | 16 | return &cpumask_of_cpu(0); |
497c9a19 | 17 | #endif |
1da177e4 | 18 | } |
1da177e4 | 19 | |
1855a2c4 | 20 | #define APIC_DFR_VALUE (APIC_DFR_FLAT) |
1da177e4 | 21 | |
d1d7cae8 IM |
22 | static inline unsigned long |
23 | bigsmp_check_apicid_used(physid_mask_t bitmap, int apicid) | |
1da177e4 | 24 | { |
d1d7cae8 | 25 | return 0; |
1da177e4 LT |
26 | } |
27 | ||
d1d7cae8 | 28 | static inline unsigned long bigsmp_check_apicid_present(int bit) |
1da177e4 | 29 | { |
d1d7cae8 | 30 | return 1; |
1da177e4 LT |
31 | } |
32 | ||
1855a2c4 | 33 | static inline unsigned long calculate_ldr(int cpu) |
1da177e4 | 34 | { |
1855a2c4 AR |
35 | unsigned long val, id; |
36 | val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; | |
37 | id = xapic_phys_to_log_apicid(cpu); | |
38 | val |= SET_APIC_LOGICAL_ID(id); | |
39 | return val; | |
1da177e4 LT |
40 | } |
41 | ||
42 | /* | |
43 | * Set up the logical destination ID. | |
44 | * | |
45 | * Intel recommends to set DFR, LDR and TPR before enabling | |
46 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
47 | * document number 292116). So here it goes... | |
48 | */ | |
a5c43296 | 49 | static inline void bigsmp_init_apic_ldr(void) |
1da177e4 LT |
50 | { |
51 | unsigned long val; | |
1855a2c4 | 52 | int cpu = smp_processor_id(); |
1da177e4 | 53 | |
593f4a78 | 54 | apic_write(APIC_DFR, APIC_DFR_VALUE); |
1855a2c4 | 55 | val = calculate_ldr(cpu); |
593f4a78 | 56 | apic_write(APIC_LDR, val); |
1da177e4 LT |
57 | } |
58 | ||
3c43f039 | 59 | static inline void setup_apic_routing(void) |
1da177e4 LT |
60 | { |
61 | printk("Enabling APIC mode: %s. Using %d I/O APICs\n", | |
1855a2c4 | 62 | "Physflat", nr_ioapics); |
1da177e4 LT |
63 | } |
64 | ||
65 | static inline int multi_timer_check(int apic, int irq) | |
66 | { | |
1855a2c4 | 67 | return (0); |
1da177e4 LT |
68 | } |
69 | ||
70 | static inline int apicid_to_node(int logical_apicid) | |
71 | { | |
f47f9d53 | 72 | return apicid_2_node[hard_smp_processor_id()]; |
1da177e4 LT |
73 | } |
74 | ||
1da177e4 LT |
75 | static inline int cpu_present_to_apicid(int mps_cpu) |
76 | { | |
e7986739 | 77 | if (mps_cpu < nr_cpu_ids) |
cbe879fc | 78 | return (int) per_cpu(x86_bios_cpu_apicid, mps_cpu); |
1855a2c4 AR |
79 | |
80 | return BAD_APICID; | |
1da177e4 LT |
81 | } |
82 | ||
83 | static inline physid_mask_t apicid_to_cpu_present(int phys_apicid) | |
84 | { | |
85 | return physid_mask_of_physid(phys_apicid); | |
86 | } | |
87 | ||
88 | extern u8 cpu_2_logical_apicid[]; | |
89 | /* Mapping from cpu number to logical apicid */ | |
90 | static inline int cpu_to_logical_apicid(int cpu) | |
91 | { | |
e7986739 | 92 | if (cpu >= nr_cpu_ids) |
1855a2c4 AR |
93 | return BAD_APICID; |
94 | return cpu_physical_id(cpu); | |
95 | } | |
1da177e4 | 96 | |
1da177e4 LT |
97 | static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_map) |
98 | { | |
99 | /* For clustered we don't have a good way to do this yet - hack */ | |
1855a2c4 | 100 | return physids_promote(0xFFL); |
1da177e4 LT |
101 | } |
102 | ||
1da177e4 LT |
103 | static inline void setup_portio_remap(void) |
104 | { | |
105 | } | |
106 | ||
107 | static inline void enable_apic_mode(void) | |
108 | { | |
109 | } | |
110 | ||
111 | static inline int check_phys_apicid_present(int boot_cpu_physical_apicid) | |
112 | { | |
113 | return (1); | |
114 | } | |
115 | ||
116 | /* As we are using single CPU as destination, pick only one CPU here */ | |
e7986739 | 117 | static inline unsigned int cpu_mask_to_apicid(const cpumask_t *cpumask) |
1da177e4 LT |
118 | { |
119 | int cpu; | |
120 | int apicid; | |
121 | ||
e7986739 | 122 | cpu = first_cpu(*cpumask); |
1da177e4 LT |
123 | apicid = cpu_to_logical_apicid(cpu); |
124 | return apicid; | |
125 | } | |
126 | ||
6eeb7c5a MT |
127 | static inline unsigned int cpu_mask_to_apicid_and(const struct cpumask *cpumask, |
128 | const struct cpumask *andmask) | |
95d313cf MT |
129 | { |
130 | int cpu; | |
131 | ||
132 | /* | |
133 | * We're using fixed IRQ delivery, can only return one phys APIC ID. | |
134 | * May as well be the first. | |
135 | */ | |
a775a38b MT |
136 | for_each_cpu_and(cpu, cpumask, andmask) |
137 | if (cpumask_test_cpu(cpu, cpu_online_mask)) | |
138 | break; | |
6eeb7c5a MT |
139 | if (cpu < nr_cpu_ids) |
140 | return cpu_to_logical_apicid(cpu); | |
95d313cf MT |
141 | |
142 | return BAD_APICID; | |
143 | } | |
144 | ||
1da177e4 LT |
145 | static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb) |
146 | { | |
147 | return cpuid_apic >> index_msb; | |
148 | } | |
149 | ||
1176fa91 | 150 | #endif /* __ASM_MACH_APIC_H */ |