[deliverable/linux.git] / arch / x86 / include / asm / cpu_debug.h

#ifndef _ASM_X86_CPU_DEBUG_H
#define _ASM_X86_CPU_DEBUG_H

/*
 * CPU x86 architecture debug
 *
 * Copyright(C) 2009 Jaswinder Singh Rajput
 */

/* Register flags */
enum cpu_debug_bit {
/* Model Specific Registers (MSRs)					*/
	CPU_MC_BIT,				/* Machine Check	*/
	CPU_MONITOR_BIT,			/* Monitor		*/
	CPU_TIME_BIT,				/* Time			*/
	CPU_PMC_BIT,				/* Performance Monitor	*/
	CPU_PLATFORM_BIT,			/* Platform		*/
	CPU_APIC_BIT,				/* APIC			*/
	CPU_POWERON_BIT,			/* Power-on		*/
	CPU_CONTROL_BIT,			/* Control		*/
	CPU_FEATURES_BIT,			/* Features control	*/
	CPU_LBRANCH_BIT,			/* Last Branch		*/
	CPU_BIOS_BIT,				/* BIOS			*/
	CPU_FREQ_BIT,				/* Frequency		*/
	CPU_MTTR_BIT,				/* MTRR			*/
	CPU_PERF_BIT,				/* Performance		*/
	CPU_CACHE_BIT,				/* Cache		*/
	CPU_SYSENTER_BIT,			/* Sysenter		*/
	CPU_THERM_BIT,				/* Thermal		*/
	CPU_MISC_BIT,				/* Miscellaneous	*/
	CPU_DEBUG_BIT,				/* Debug		*/
	CPU_PAT_BIT,				/* PAT			*/
	CPU_VMX_BIT,				/* VMX			*/
	CPU_CALL_BIT,				/* System Call		*/
	CPU_BASE_BIT,				/* BASE Address		*/
	CPU_SMM_BIT,				/* System mgmt mode	*/
	CPU_SVM_BIT,				/*Secure Virtual Machine*/
	CPU_OSVM_BIT,				/* OS-Visible Workaround*/
/* Standard Registers							*/
	CPU_TSS_BIT,				/* Task Stack Segment	*/
	CPU_CR_BIT,				/* Control Registers	*/
	CPU_DT_BIT,				/* Descriptor Table	*/
/* End of Registers flags						*/
	CPU_REG_ALL_BIT,			/* Select all Registers	*/
};

#define	CPU_REG_ALL		(~0)		/* Select all Registers	*/

#define	CPU_MC			(1 << CPU_MC_BIT)
#define	CPU_MONITOR		(1 << CPU_MONITOR_BIT)
#define	CPU_TIME		(1 << CPU_TIME_BIT)
#define	CPU_PMC			(1 << CPU_PMC_BIT)
#define	CPU_PLATFORM		(1 << CPU_PLATFORM_BIT)
#define	CPU_APIC		(1 << CPU_APIC_BIT)
#define	CPU_POWERON		(1 << CPU_POWERON_BIT)
#define	CPU_CONTROL		(1 << CPU_CONTROL_BIT)
#define	CPU_FEATURES		(1 << CPU_FEATURES_BIT)
#define	CPU_LBRANCH		(1 << CPU_LBRANCH_BIT)
#define	CPU_BIOS		(1 << CPU_BIOS_BIT)
#define	CPU_FREQ		(1 << CPU_FREQ_BIT)
#define	CPU_MTRR		(1 << CPU_MTTR_BIT)
#define	CPU_PERF		(1 << CPU_PERF_BIT)
#define	CPU_CACHE		(1 << CPU_CACHE_BIT)
#define	CPU_SYSENTER		(1 << CPU_SYSENTER_BIT)
#define	CPU_THERM		(1 << CPU_THERM_BIT)
#define	CPU_MISC		(1 << CPU_MISC_BIT)
#define	CPU_DEBUG		(1 << CPU_DEBUG_BIT)
#define	CPU_PAT			(1 << CPU_PAT_BIT)
#define	CPU_VMX			(1 << CPU_VMX_BIT)
#define	CPU_CALL		(1 << CPU_CALL_BIT)
#define	CPU_BASE		(1 << CPU_BASE_BIT)
#define	CPU_SMM			(1 << CPU_SMM_BIT)
#define	CPU_SVM			(1 << CPU_SVM_BIT)
#define	CPU_OSVM		(1 << CPU_OSVM_BIT)
#define	CPU_TSS			(1 << CPU_TSS_BIT)
#define	CPU_CR			(1 << CPU_CR_BIT)
#define	CPU_DT			(1 << CPU_DT_BIT)

/* Register file flags */
enum cpu_file_bit {
	CPU_INDEX_BIT,				/* index		*/
	CPU_VALUE_BIT,				/* value		*/
};

#define	CPU_FILE_VALUE			(1 << CPU_VALUE_BIT)

/*
 * DisplayFamily_DisplayModel	Processor Families/Processor Number Series
 * --------------------------	------------------------------------------
 * 05_01, 05_02, 05_04		Pentium, Pentium with MMX
 *
 * 06_01			Pentium Pro
 * 06_03, 06_05			Pentium II Xeon, Pentium II
 * 06_07, 06_08, 06_0A, 06_0B	Pentium III Xeon, Pentum III
 *
 * 06_09, 060D			Pentium M
 *
 * 06_0E			Core Duo, Core Solo
 *
 * 06_0F			Xeon 3000, 3200, 5100, 5300, 7300 series,
 *				Core 2 Quad, Core 2 Extreme, Core 2 Duo,
 *				Pentium dual-core
 * 06_17			Xeon 5200, 5400 series, Core 2 Quad Q9650
 *
 * 06_1C			Atom
 *
 * 0F_00, 0F_01, 0F_02		Xeon, Xeon MP, Pentium 4
 * 0F_03, 0F_04			Xeon, Xeon MP, Pentium 4, Pentium D
 *
 * 0F_06			Xeon 7100, 5000 Series, Xeon MP,
 *				Pentium 4, Pentium D
 */

/* Register processors bits */
enum cpu_processor_bit {
	CPU_NONE,
/* Intel */
	CPU_INTEL_PENTIUM_BIT,
	CPU_INTEL_P6_BIT,
	CPU_INTEL_PENTIUM_M_BIT,
	CPU_INTEL_CORE_BIT,
	CPU_INTEL_CORE2_BIT,
	CPU_INTEL_ATOM_BIT,
	CPU_INTEL_XEON_P4_BIT,
	CPU_INTEL_XEON_MP_BIT,
};

#define	CPU_ALL			(~0)		/* Select all CPUs	*/

#define	CPU_INTEL_PENTIUM	(1 << CPU_INTEL_PENTIUM_BIT)
#define	CPU_INTEL_P6		(1 << CPU_INTEL_P6_BIT)
#define	CPU_INTEL_PENTIUM_M	(1 << CPU_INTEL_PENTIUM_M_BIT)
#define	CPU_INTEL_CORE		(1 << CPU_INTEL_CORE_BIT)
#define	CPU_INTEL_CORE2		(1 << CPU_INTEL_CORE2_BIT)
#define	CPU_INTEL_ATOM		(1 << CPU_INTEL_ATOM_BIT)
#define	CPU_INTEL_XEON_P4	(1 << CPU_INTEL_XEON_P4_BIT)
#define	CPU_INTEL_XEON_MP	(1 << CPU_INTEL_XEON_MP_BIT)

#define	CPU_INTEL_PX		(CPU_INTEL_P6 | CPU_INTEL_PENTIUM_M)
#define	CPU_INTEL_COREX		(CPU_INTEL_CORE | CPU_INTEL_CORE2)
#define	CPU_INTEL_XEON		(CPU_INTEL_XEON_P4 | CPU_INTEL_XEON_MP)
#define	CPU_CO_AT		(CPU_INTEL_CORE | CPU_INTEL_ATOM)
#define	CPU_C2_AT		(CPU_INTEL_CORE2 | CPU_INTEL_ATOM)
#define	CPU_CX_AT		(CPU_INTEL_COREX | CPU_INTEL_ATOM)
#define	CPU_CX_XE		(CPU_INTEL_COREX | CPU_INTEL_XEON)
#define	CPU_P6_XE		(CPU_INTEL_P6 | CPU_INTEL_XEON)
#define	CPU_PM_CO_AT		(CPU_INTEL_PENTIUM_M | CPU_CO_AT)
#define	CPU_C2_AT_XE		(CPU_C2_AT | CPU_INTEL_XEON)
#define	CPU_CX_AT_XE		(CPU_CX_AT | CPU_INTEL_XEON)
#define	CPU_P6_CX_AT		(CPU_INTEL_P6 | CPU_CX_AT)
#define	CPU_P6_CX_XE		(CPU_P6_XE | CPU_INTEL_COREX)
#define	CPU_P6_CX_AT_XE		(CPU_INTEL_P6 | CPU_CX_AT_XE)
#define	CPU_PM_CX_AT_XE		(CPU_INTEL_PENTIUM_M | CPU_CX_AT_XE)
#define	CPU_PM_CX_AT		(CPU_INTEL_PENTIUM_M | CPU_CX_AT)
#define	CPU_PM_CX_XE		(CPU_INTEL_PENTIUM_M | CPU_CX_XE)
#define	CPU_PX_CX_AT		(CPU_INTEL_PX | CPU_CX_AT)
#define	CPU_PX_CX_AT_XE		(CPU_INTEL_PX | CPU_CX_AT_XE)

/* Select all Intel CPUs*/
#define	CPU_INTEL_ALL		(CPU_INTEL_PENTIUM | CPU_PX_CX_AT_XE)

#define MAX_CPU_FILES		512

struct cpu_private {
	unsigned		cpu;
	unsigned		type;
	unsigned		reg;
	unsigned		file;
};

struct cpu_debug_base {
	char			*name;		/* Register name	*/
	unsigned		flag;		/* Register flag	*/
};

struct cpu_cpuX_base {
	struct dentry		*dentry;	/* Register dentry	*/
	int			init;		/* Register index file	*/
};

struct cpu_file_base {
	char			*name;		/* Register file name	*/
	unsigned		flag;		/* Register file flag	*/
};

struct cpu_debug_range {
	unsigned		min;		/* Register range min	*/
	unsigned		max;		/* Register range max	*/
	unsigned		flag;		/* Supported flags	*/
	unsigned		model;		/* Supported models	*/
};

#endif /* _ASM_X86_CPU_DEBUG_H */
Commit	Line	Data
9b779edf JSR	1	#ifndef _ASM_X86_CPU_DEBUG_H
	2	#define _ASM_X86_CPU_DEBUG_H
	3
	4	/*
	5	* CPU x86 architecture debug
	6	*
	7	* Copyright(C) 2009 Jaswinder Singh Rajput
	8	*/
	9
	10	/* Register flags */
	11	enum cpu_debug_bit {
	12	/* Model Specific Registers (MSRs) */
	13	CPU_MC_BIT, /* Machine Check */
	14	CPU_MONITOR_BIT, /* Monitor */
	15	CPU_TIME_BIT, /* Time */
	16	CPU_PMC_BIT, /* Performance Monitor */
	17	CPU_PLATFORM_BIT, /* Platform */
	18	CPU_APIC_BIT, /* APIC */
	19	CPU_POWERON_BIT, /* Power-on */
	20	CPU_CONTROL_BIT, /* Control */
	21	CPU_FEATURES_BIT, /* Features control */
	22	CPU_LBRANCH_BIT, /* Last Branch */
	23	CPU_BIOS_BIT, /* BIOS */
	24	CPU_FREQ_BIT, /* Frequency */
	25	CPU_MTTR_BIT, /* MTRR */
	26	CPU_PERF_BIT, /* Performance */
	27	CPU_CACHE_BIT, /* Cache */
	28	CPU_SYSENTER_BIT, /* Sysenter */
	29	CPU_THERM_BIT, /* Thermal */
	30	CPU_MISC_BIT, /* Miscellaneous */
	31	CPU_DEBUG_BIT, /* Debug */
	32	CPU_PAT_BIT, /* PAT */
	33	CPU_VMX_BIT, /* VMX */
	34	CPU_CALL_BIT, /* System Call */
	35	CPU_BASE_BIT, /* BASE Address */
	36	CPU_SMM_BIT, /* System mgmt mode */
	37	CPU_SVM_BIT, /Secure Virtual Machine/
	38	CPU_OSVM_BIT, /* OS-Visible Workaround*/
	39	/* Standard Registers */
	40	CPU_TSS_BIT, /* Task Stack Segment */
	41	CPU_CR_BIT, /* Control Registers */
	42	CPU_DT_BIT, /* Descriptor Table */
	43	/* End of Registers flags */
	44	CPU_REG_ALL_BIT, /* Select all Registers */
	45	};
	46
	47	#define CPU_REG_ALL (~0) /* Select all Registers */
	48
	49	#define CPU_MC (1 << CPU_MC_BIT)
	50	#define CPU_MONITOR (1 << CPU_MONITOR_BIT)
	51	#define CPU_TIME (1 << CPU_TIME_BIT)
	52	#define CPU_PMC (1 << CPU_PMC_BIT)
	53	#define CPU_PLATFORM (1 << CPU_PLATFORM_BIT)
	54	#define CPU_APIC (1 << CPU_APIC_BIT)
	55	#define CPU_POWERON (1 << CPU_POWERON_BIT)
	56	#define CPU_CONTROL (1 << CPU_CONTROL_BIT)
	57	#define CPU_FEATURES (1 << CPU_FEATURES_BIT)
	58	#define CPU_LBRANCH (1 << CPU_LBRANCH_BIT)
	59	#define CPU_BIOS (1 << CPU_BIOS_BIT)
	60	#define CPU_FREQ (1 << CPU_FREQ_BIT)
	61	#define CPU_MTRR (1 << CPU_MTTR_BIT)
	62	#define CPU_PERF (1 << CPU_PERF_BIT)
	63	#define CPU_CACHE (1 << CPU_CACHE_BIT)
	64	#define CPU_SYSENTER (1 << CPU_SYSENTER_BIT)
65	#define CPU_THERM (1 << CPU_THERM_BIT)
66	#define CPU_MISC (1 << CPU_MISC_BIT)
67	#define CPU_DEBUG (1 << CPU_DEBUG_BIT)
68	#define CPU_PAT (1 << CPU_PAT_BIT)
69	#define CPU_VMX (1 << CPU_VMX_BIT)
70	#define CPU_CALL (1 << CPU_CALL_BIT)
71	#define CPU_BASE (1 << CPU_BASE_BIT)
72	#define CPU_SMM (1 << CPU_SMM_BIT)
73	#define CPU_SVM (1 << CPU_SVM_BIT)
74	#define CPU_OSVM (1 << CPU_OSVM_BIT)
75	#define CPU_TSS (1 << CPU_TSS_BIT)
76	#define CPU_CR (1 << CPU_CR_BIT)
77	#define CPU_DT (1 << CPU_DT_BIT)
78
79	/* Register file flags */
80	enum cpu_file_bit {
81	CPU_INDEX_BIT, /* index */
82	CPU_VALUE_BIT, /* value */
83	};
84
85	#define CPU_FILE_VALUE (1 << CPU_VALUE_BIT)
86
87	/*
88	* DisplayFamily_DisplayModel Processor Families/Processor Number Series
89	* -------------------------- ------------------------------------------
90	* 05_01, 05_02, 05_04 Pentium, Pentium with MMX
91	*
92	* 06_01 Pentium Pro
93	* 06_03, 06_05 Pentium II Xeon, Pentium II
94	* 06_07, 06_08, 06_0A, 06_0B Pentium III Xeon, Pentum III
95	*
96	* 06_09, 060D Pentium M
97	*
98	* 06_0E Core Duo, Core Solo
99	*
100	* 06_0F Xeon 3000, 3200, 5100, 5300, 7300 series,
101	* Core 2 Quad, Core 2 Extreme, Core 2 Duo,
102	* Pentium dual-core
103	* 06_17 Xeon 5200, 5400 series, Core 2 Quad Q9650
104	*
105	* 06_1C Atom
106	*
107	* 0F_00, 0F_01, 0F_02 Xeon, Xeon MP, Pentium 4
108	* 0F_03, 0F_04 Xeon, Xeon MP, Pentium 4, Pentium D
109	*
110	* 0F_06 Xeon 7100, 5000 Series, Xeon MP,
111	* Pentium 4, Pentium D
112	*/
113
114	/* Register processors bits */
115	enum cpu_processor_bit {
116	CPU_NONE,
117	/* Intel */
118	CPU_INTEL_PENTIUM_BIT,
119	CPU_INTEL_P6_BIT,
120	CPU_INTEL_PENTIUM_M_BIT,
121	CPU_INTEL_CORE_BIT,
122	CPU_INTEL_CORE2_BIT,
123	CPU_INTEL_ATOM_BIT,
124	CPU_INTEL_XEON_P4_BIT,
125	CPU_INTEL_XEON_MP_BIT,
126	};
127
128	#define CPU_ALL (~0) /* Select all CPUs */
129
130	#define CPU_INTEL_PENTIUM (1 << CPU_INTEL_PENTIUM_BIT)
131	#define CPU_INTEL_P6 (1 << CPU_INTEL_P6_BIT)
132	#define CPU_INTEL_PENTIUM_M (1 << CPU_INTEL_PENTIUM_M_BIT)
133	#define CPU_INTEL_CORE (1 << CPU_INTEL_CORE_BIT)
134	#define CPU_INTEL_CORE2 (1 << CPU_INTEL_CORE2_BIT)
135	#define CPU_INTEL_ATOM (1 << CPU_INTEL_ATOM_BIT)
136	#define CPU_INTEL_XEON_P4 (1 << CPU_INTEL_XEON_P4_BIT)
137	#define CPU_INTEL_XEON_MP (1 << CPU_INTEL_XEON_MP_BIT)
138
139	#define CPU_INTEL_PX (CPU_INTEL_P6 \| CPU_INTEL_PENTIUM_M)
140	#define CPU_INTEL_COREX (CPU_INTEL_CORE \| CPU_INTEL_CORE2)
141	#define CPU_INTEL_XEON (CPU_INTEL_XEON_P4 \| CPU_INTEL_XEON_MP)
142	#define CPU_CO_AT (CPU_INTEL_CORE \| CPU_INTEL_ATOM)
143	#define CPU_C2_AT (CPU_INTEL_CORE2 \| CPU_INTEL_ATOM)
144	#define CPU_CX_AT (CPU_INTEL_COREX \| CPU_INTEL_ATOM)
145	#define CPU_CX_XE (CPU_INTEL_COREX \| CPU_INTEL_XEON)
146	#define CPU_P6_XE (CPU_INTEL_P6 \| CPU_INTEL_XEON)
147	#define CPU_PM_CO_AT (CPU_INTEL_PENTIUM_M \| CPU_CO_AT)
148	#define CPU_C2_AT_XE (CPU_C2_AT \| CPU_INTEL_XEON)
149	#define CPU_CX_AT_XE (CPU_CX_AT \| CPU_INTEL_XEON)
150	#define CPU_P6_CX_AT (CPU_INTEL_P6 \| CPU_CX_AT)
151	#define CPU_P6_CX_XE (CPU_P6_XE \| CPU_INTEL_COREX)
152	#define CPU_P6_CX_AT_XE (CPU_INTEL_P6 \| CPU_CX_AT_XE)
153	#define CPU_PM_CX_AT_XE (CPU_INTEL_PENTIUM_M \| CPU_CX_AT_XE)
154	#define CPU_PM_CX_AT (CPU_INTEL_PENTIUM_M \| CPU_CX_AT)
155	#define CPU_PM_CX_XE (CPU_INTEL_PENTIUM_M \| CPU_CX_XE)
156	#define CPU_PX_CX_AT (CPU_INTEL_PX \| CPU_CX_AT)
157	#define CPU_PX_CX_AT_XE (CPU_INTEL_PX \| CPU_CX_AT_XE)
158
159	/* Select all Intel CPUs*/
160	#define CPU_INTEL_ALL (CPU_INTEL_PENTIUM \| CPU_PX_CX_AT_XE)
161
162	#define MAX_CPU_FILES 512
163
164	struct cpu_private {
165	unsigned cpu;
166	unsigned type;
167	unsigned reg;
168	unsigned file;
169	};
170
171	struct cpu_debug_base {
172	char name; / Register name */
173	unsigned flag; /* Register flag */
174	};
175
176	struct cpu_cpuX_base {
177	struct dentry dentry; / Register dentry */
178	int init; /* Register index file */
179	};
180
181	struct cpu_file_base {
182	char name; / Register file name */
183	unsigned flag; /* Register file flag */
184	};
185
186	struct cpu_debug_range {
187	unsigned min; /* Register range min */
188	unsigned max; /* Register range max */
189	unsigned flag; /* Supported flags */
190	unsigned model; /* Supported models */
191	};
192
193	#endif /* _ASM_X86_CPU_DEBUG_H */