[deliverable/linux.git] / arch / x86 / include / asm / cpu_debug.h

#ifndef _ASM_X86_CPU_DEBUG_H
#define _ASM_X86_CPU_DEBUG_H

/*
 * CPU x86 architecture debug
 *
 * Copyright(C) 2009 Jaswinder Singh Rajput
 */

/* Register flags */
enum cpu_debug_bit {
/* Model Specific Registers (MSRs)					*/
	CPU_MC_BIT,				/* Machine Check	*/
	CPU_MONITOR_BIT,			/* Monitor		*/
	CPU_TIME_BIT,				/* Time			*/
	CPU_PMC_BIT,				/* Performance Monitor	*/
	CPU_PLATFORM_BIT,			/* Platform		*/
	CPU_APIC_BIT,				/* APIC			*/
	CPU_POWERON_BIT,			/* Power-on		*/
	CPU_CONTROL_BIT,			/* Control		*/
	CPU_FEATURES_BIT,			/* Features control	*/
	CPU_LBRANCH_BIT,			/* Last Branch		*/
	CPU_BIOS_BIT,				/* BIOS			*/
	CPU_FREQ_BIT,				/* Frequency		*/
	CPU_MTTR_BIT,				/* MTRR			*/
	CPU_PERF_BIT,				/* Performance		*/
	CPU_CACHE_BIT,				/* Cache		*/
	CPU_SYSENTER_BIT,			/* Sysenter		*/
	CPU_THERM_BIT,				/* Thermal		*/
	CPU_MISC_BIT,				/* Miscellaneous	*/
	CPU_DEBUG_BIT,				/* Debug		*/
	CPU_PAT_BIT,				/* PAT			*/
	CPU_VMX_BIT,				/* VMX			*/
	CPU_CALL_BIT,				/* System Call		*/
	CPU_BASE_BIT,				/* BASE Address		*/
	CPU_VER_BIT,				/* Version ID		*/
	CPU_CONF_BIT,				/* Configuration	*/
	CPU_SMM_BIT,				/* System mgmt mode	*/
	CPU_SVM_BIT,				/*Secure Virtual Machine*/
	CPU_OSVM_BIT,				/* OS-Visible Workaround*/
/* Standard Registers							*/
	CPU_TSS_BIT,				/* Task Stack Segment	*/
	CPU_CR_BIT,				/* Control Registers	*/
	CPU_DT_BIT,				/* Descriptor Table	*/
/* End of Registers flags						*/
	CPU_REG_ALL_BIT,			/* Select all Registers	*/
};

#define	CPU_REG_ALL		(~0)		/* Select all Registers	*/

#define	CPU_MC			(1 << CPU_MC_BIT)
#define	CPU_MONITOR		(1 << CPU_MONITOR_BIT)
#define	CPU_TIME		(1 << CPU_TIME_BIT)
#define	CPU_PMC			(1 << CPU_PMC_BIT)
#define	CPU_PLATFORM		(1 << CPU_PLATFORM_BIT)
#define	CPU_APIC		(1 << CPU_APIC_BIT)
#define	CPU_POWERON		(1 << CPU_POWERON_BIT)
#define	CPU_CONTROL		(1 << CPU_CONTROL_BIT)
#define	CPU_FEATURES		(1 << CPU_FEATURES_BIT)
#define	CPU_LBRANCH		(1 << CPU_LBRANCH_BIT)
#define	CPU_BIOS		(1 << CPU_BIOS_BIT)
#define	CPU_FREQ		(1 << CPU_FREQ_BIT)
#define	CPU_MTRR		(1 << CPU_MTTR_BIT)
#define	CPU_PERF		(1 << CPU_PERF_BIT)
#define	CPU_CACHE		(1 << CPU_CACHE_BIT)
#define	CPU_SYSENTER		(1 << CPU_SYSENTER_BIT)
#define	CPU_THERM		(1 << CPU_THERM_BIT)
#define	CPU_MISC		(1 << CPU_MISC_BIT)
#define	CPU_DEBUG		(1 << CPU_DEBUG_BIT)
#define	CPU_PAT			(1 << CPU_PAT_BIT)
#define	CPU_VMX			(1 << CPU_VMX_BIT)
#define	CPU_CALL		(1 << CPU_CALL_BIT)
#define	CPU_BASE		(1 << CPU_BASE_BIT)
#define	CPU_VER			(1 << CPU_VER_BIT)
#define	CPU_CONF		(1 << CPU_CONF_BIT)
#define	CPU_SMM			(1 << CPU_SMM_BIT)
#define	CPU_SVM			(1 << CPU_SVM_BIT)
#define	CPU_OSVM		(1 << CPU_OSVM_BIT)
#define	CPU_TSS			(1 << CPU_TSS_BIT)
#define	CPU_CR			(1 << CPU_CR_BIT)
#define	CPU_DT			(1 << CPU_DT_BIT)

/* Register file flags */
enum cpu_file_bit {
	CPU_INDEX_BIT,				/* index		*/
	CPU_VALUE_BIT,				/* value		*/
};

#define	CPU_FILE_VALUE		(1 << CPU_VALUE_BIT)

#define MAX_CPU_FILES		512

struct cpu_private {
	unsigned		cpu;
	unsigned		type;
	unsigned		reg;
	unsigned		file;
};

struct cpu_debug_base {
	char			*name;		/* Register name	*/
	unsigned		flag;		/* Register flag	*/
	unsigned		write;		/* Register write flag	*/
};

/*
 * Currently it looks similar to cpu_debug_base but once we add more files
 * cpu_file_base will go in different direction
 */
struct cpu_file_base {
	char			*name;		/* Register file name	*/
	unsigned		flag;		/* Register file flag	*/
	unsigned		write;		/* Register write flag	*/
};

struct cpu_cpuX_base {
	struct dentry		*dentry;	/* Register dentry	*/
	int			init;		/* Register index file	*/
};

struct cpu_debug_range {
	unsigned		min;		/* Register range min	*/
	unsigned		max;		/* Register range max	*/
	unsigned		flag;		/* Supported flags	*/
};

#endif /* _ASM_X86_CPU_DEBUG_H */
Commit	Line	Data
9b779edf JSR	1	#ifndef _ASM_X86_CPU_DEBUG_H
	2	#define _ASM_X86_CPU_DEBUG_H
	3
	4	/*
	5	* CPU x86 architecture debug
	6	*
	7	* Copyright(C) 2009 Jaswinder Singh Rajput
	8	*/
	9
	10	/* Register flags */
	11	enum cpu_debug_bit {
	12	/* Model Specific Registers (MSRs) */
	13	CPU_MC_BIT, /* Machine Check */
	14	CPU_MONITOR_BIT, /* Monitor */
	15	CPU_TIME_BIT, /* Time */
	16	CPU_PMC_BIT, /* Performance Monitor */
	17	CPU_PLATFORM_BIT, /* Platform */
	18	CPU_APIC_BIT, /* APIC */
	19	CPU_POWERON_BIT, /* Power-on */
	20	CPU_CONTROL_BIT, /* Control */
	21	CPU_FEATURES_BIT, /* Features control */
	22	CPU_LBRANCH_BIT, /* Last Branch */
	23	CPU_BIOS_BIT, /* BIOS */
	24	CPU_FREQ_BIT, /* Frequency */
	25	CPU_MTTR_BIT, /* MTRR */
	26	CPU_PERF_BIT, /* Performance */
	27	CPU_CACHE_BIT, /* Cache */
	28	CPU_SYSENTER_BIT, /* Sysenter */
	29	CPU_THERM_BIT, /* Thermal */
	30	CPU_MISC_BIT, /* Miscellaneous */
	31	CPU_DEBUG_BIT, /* Debug */
	32	CPU_PAT_BIT, /* PAT */
	33	CPU_VMX_BIT, /* VMX */
	34	CPU_CALL_BIT, /* System Call */
	35	CPU_BASE_BIT, /* BASE Address */
f4c3c4cd JSR	36	CPU_VER_BIT, /* Version ID */
f4c3c4cd JSR	37	CPU_CONF_BIT, /* Configuration */
9b779edf JSR	38	CPU_SMM_BIT, /* System mgmt mode */
	39	CPU_SVM_BIT, /Secure Virtual Machine/
	40	CPU_OSVM_BIT, /* OS-Visible Workaround*/
	41	/* Standard Registers */
	42	CPU_TSS_BIT, /* Task Stack Segment */
	43	CPU_CR_BIT, /* Control Registers */
	44	CPU_DT_BIT, /* Descriptor Table */
	45	/* End of Registers flags */
	46	CPU_REG_ALL_BIT, /* Select all Registers */
	47	};
	48
	49	#define CPU_REG_ALL (~0) /* Select all Registers */
	50
	51	#define CPU_MC (1 << CPU_MC_BIT)
	52	#define CPU_MONITOR (1 << CPU_MONITOR_BIT)
	53	#define CPU_TIME (1 << CPU_TIME_BIT)
	54	#define CPU_PMC (1 << CPU_PMC_BIT)
	55	#define CPU_PLATFORM (1 << CPU_PLATFORM_BIT)
	56	#define CPU_APIC (1 << CPU_APIC_BIT)
	57	#define CPU_POWERON (1 << CPU_POWERON_BIT)
	58	#define CPU_CONTROL (1 << CPU_CONTROL_BIT)
	59	#define CPU_FEATURES (1 << CPU_FEATURES_BIT)
	60	#define CPU_LBRANCH (1 << CPU_LBRANCH_BIT)
	61	#define CPU_BIOS (1 << CPU_BIOS_BIT)
	62	#define CPU_FREQ (1 << CPU_FREQ_BIT)
	63	#define CPU_MTRR (1 << CPU_MTTR_BIT)
	64	#define CPU_PERF (1 << CPU_PERF_BIT)
	65	#define CPU_CACHE (1 << CPU_CACHE_BIT)
	66	#define CPU_SYSENTER (1 << CPU_SYSENTER_BIT)
	67	#define CPU_THERM (1 << CPU_THERM_BIT)
	68	#define CPU_MISC (1 << CPU_MISC_BIT)
	69	#define CPU_DEBUG (1 << CPU_DEBUG_BIT)
	70	#define CPU_PAT (1 << CPU_PAT_BIT)
	71	#define CPU_VMX (1 << CPU_VMX_BIT)
	72	#define CPU_CALL (1 << CPU_CALL_BIT)
	73	#define CPU_BASE (1 << CPU_BASE_BIT)
f4c3c4cd JSR	74	#define CPU_VER (1 << CPU_VER_BIT)
f4c3c4cd JSR	75	#define CPU_CONF (1 << CPU_CONF_BIT)
9b779edf JSR	76	#define CPU_SMM (1 << CPU_SMM_BIT)
	77	#define CPU_SVM (1 << CPU_SVM_BIT)
	78	#define CPU_OSVM (1 << CPU_OSVM_BIT)
	79	#define CPU_TSS (1 << CPU_TSS_BIT)
	80	#define CPU_CR (1 << CPU_CR_BIT)
	81	#define CPU_DT (1 << CPU_DT_BIT)
	82
	83	/* Register file flags */
	84	enum cpu_file_bit {
	85	CPU_INDEX_BIT, /* index */
	86	CPU_VALUE_BIT, /* value */
	87	};
	88
5095f59b	89	#define CPU_FILE_VALUE (1 << CPU_VALUE_BIT)
f4c3c4cd	90
9b779edf JSR	91	#define MAX_CPU_FILES 512
	92
	93	struct cpu_private {
	94	unsigned cpu;
	95	unsigned type;
	96	unsigned reg;
	97	unsigned file;
	98	};
	99
	100	struct cpu_debug_base {
	101	char name; / Register name */
	102	unsigned flag; /* Register flag */
91219bcb	103	unsigned write; /* Register write flag */
9b779edf JSR	104	};
9b779edf JSR	105
91219bcb JSR	106	/*
	107	* Currently it looks similar to cpu_debug_base but once we add more files
	108	* cpu_file_base will go in different direction
	109	*/
9b779edf JSR	110	struct cpu_file_base {
	111	char name; / Register file name */
	112	unsigned flag; /* Register file flag */
91219bcb JSR	113	unsigned write; /* Register write flag */
	114	};
	115
	116	struct cpu_cpuX_base {
	117	struct dentry dentry; / Register dentry */
	118	int init; /* Register index file */
9b779edf JSR	119	};
	120
	121	struct cpu_debug_range {
	122	unsigned min; /* Register range min */
	123	unsigned max; /* Register range max */
	124	unsigned flag; /* Supported flags */
9b779edf JSR	125	};
	126
	127	#endif /* _ASM_X86_CPU_DEBUG_H */