projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 7b11fb51 PA |
1 | /* |
| 2 | * Defines x86 CPU feature bits | |
| 3 | */ | |
| 1965aae3 PA |
4 | #ifndef _ASM_X86_CPUFEATURE_H |
| 5 | #define _ASM_X86_CPUFEATURE_H | |
| 7b11fb51 | 6 | |
| 7b11fb51 PA |
7 | #include <asm/required-features.h> |
| 8 | ||
| e38e05a8 | 9 | #define NCAPINTS 9 /* N 32-bit words worth of info */ |
| 7b11fb51 | 10 | |
| 7414aa41 PA |
11 | /* |
| 12 | * Note: If the comment begins with a quoted string, that string is used | |
| 13 | * in /proc/cpuinfo instead of the macro name. If the string is "", | |
| 14 | * this feature bit is not displayed in /proc/cpuinfo at all. | |
| 15 | */ | |
| 7b11fb51 PA |
16 | |
| 17 | /* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */ | |
| 18 | #define X86_FEATURE_FPU (0*32+ 0) /* Onboard FPU */ | |
| 19 | #define X86_FEATURE_VME (0*32+ 1) /* Virtual Mode Extensions */ | |
| 20 | #define X86_FEATURE_DE (0*32+ 2) /* Debugging Extensions */ | |
| 21 | #define X86_FEATURE_PSE (0*32+ 3) /* Page Size Extensions */ | |
| 22 | #define X86_FEATURE_TSC (0*32+ 4) /* Time Stamp Counter */ | |
| 2798c63e | 23 | #define X86_FEATURE_MSR (0*32+ 5) /* Model-Specific Registers */ |
| 7b11fb51 PA |
24 | #define X86_FEATURE_PAE (0*32+ 6) /* Physical Address Extensions */ |
| 25 | #define X86_FEATURE_MCE (0*32+ 7) /* Machine Check Architecture */ | |
| 26 | #define X86_FEATURE_CX8 (0*32+ 8) /* CMPXCHG8 instruction */ | |
| 27 | #define X86_FEATURE_APIC (0*32+ 9) /* Onboard APIC */ | |
| 28 | #define X86_FEATURE_SEP (0*32+11) /* SYSENTER/SYSEXIT */ | |
| 29 | #define X86_FEATURE_MTRR (0*32+12) /* Memory Type Range Registers */ | |
| 30 | #define X86_FEATURE_PGE (0*32+13) /* Page Global Enable */ | |
| 31 | #define X86_FEATURE_MCA (0*32+14) /* Machine Check Architecture */ | |
| 2798c63e PA |
32 | #define X86_FEATURE_CMOV (0*32+15) /* CMOV instructions */ |
| 33 | /* (plus FCMOVcc, FCOMI with FPU) */ | |
| 7b11fb51 PA |
34 | #define X86_FEATURE_PAT (0*32+16) /* Page Attribute Table */ |
| 35 | #define X86_FEATURE_PSE36 (0*32+17) /* 36-bit PSEs */ | |
| 36 | #define X86_FEATURE_PN (0*32+18) /* Processor serial number */ | |
| 2798c63e | 37 | #define X86_FEATURE_CLFLSH (0*32+19) /* "clflush" CLFLUSH instruction */ |
| 7414aa41 | 38 | #define X86_FEATURE_DS (0*32+21) /* "dts" Debug Store */ |
| 7b11fb51 PA |
39 | #define X86_FEATURE_ACPI (0*32+22) /* ACPI via MSR */ |
| 40 | #define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */ | |
| 7414aa41 PA |
41 | #define X86_FEATURE_FXSR (0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */ |
| 42 | #define X86_FEATURE_XMM (0*32+25) /* "sse" */ | |
| 43 | #define X86_FEATURE_XMM2 (0*32+26) /* "sse2" */ | |
| 44 | #define X86_FEATURE_SELFSNOOP (0*32+27) /* "ss" CPU self snoop */ | |
| 7b11fb51 | 45 | #define X86_FEATURE_HT (0*32+28) /* Hyper-Threading */ |
| 7414aa41 | 46 | #define X86_FEATURE_ACC (0*32+29) /* "tm" Automatic clock control */ |
| 7b11fb51 | 47 | #define X86_FEATURE_IA64 (0*32+30) /* IA-64 processor */ |
| 7414aa41 | 48 | #define X86_FEATURE_PBE (0*32+31) /* Pending Break Enable */ |
| 7b11fb51 PA |
49 | |
| 50 | /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */ | |
| 51 | /* Don't duplicate feature flags which are redundant with Intel! */ | |
| 52 | #define X86_FEATURE_SYSCALL (1*32+11) /* SYSCALL/SYSRET */ | |
| 53 | #define X86_FEATURE_MP (1*32+19) /* MP Capable. */ | |
| 54 | #define X86_FEATURE_NX (1*32+20) /* Execute Disable */ | |
| 55 | #define X86_FEATURE_MMXEXT (1*32+22) /* AMD MMX extensions */ | |
| 7414aa41 PA |
56 | #define X86_FEATURE_FXSR_OPT (1*32+25) /* FXSAVE/FXRSTOR optimizations */ |
| 57 | #define X86_FEATURE_GBPAGES (1*32+26) /* "pdpe1gb" GB pages */ | |
| 7b11fb51 PA |
58 | #define X86_FEATURE_RDTSCP (1*32+27) /* RDTSCP */ |
| 59 | #define X86_FEATURE_LM (1*32+29) /* Long Mode (x86-64) */ | |
| 60 | #define X86_FEATURE_3DNOWEXT (1*32+30) /* AMD 3DNow! extensions */ | |
| 61 | #define X86_FEATURE_3DNOW (1*32+31) /* 3DNow! */ | |
| 62 | ||
| 63 | /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */ | |
| 64 | #define X86_FEATURE_RECOVERY (2*32+ 0) /* CPU in recovery mode */ | |
| 65 | #define X86_FEATURE_LONGRUN (2*32+ 1) /* Longrun power control */ | |
| 66 | #define X86_FEATURE_LRTI (2*32+ 3) /* LongRun table interface */ | |
| 67 | ||
| 68 | /* Other features, Linux-defined mapping, word 3 */ | |
| 69 | /* This range is used for feature bits which conflict or are synthesized */ | |
| 70 | #define X86_FEATURE_CXMMX (3*32+ 0) /* Cyrix MMX extensions */ | |
| 71 | #define X86_FEATURE_K6_MTRR (3*32+ 1) /* AMD K6 nonstandard MTRRs */ | |
| 72 | #define X86_FEATURE_CYRIX_ARR (3*32+ 2) /* Cyrix ARRs (= MTRRs) */ | |
| 73 | #define X86_FEATURE_CENTAUR_MCR (3*32+ 3) /* Centaur MCRs (= MTRRs) */ | |
| 74 | /* cpu types for specific tunings: */ | |
| 7414aa41 PA |
75 | #define X86_FEATURE_K8 (3*32+ 4) /* "" Opteron, Athlon64 */ |
| 76 | #define X86_FEATURE_K7 (3*32+ 5) /* "" Athlon */ | |
| 77 | #define X86_FEATURE_P3 (3*32+ 6) /* "" P3 */ | |
| 78 | #define X86_FEATURE_P4 (3*32+ 7) /* "" P4 */ | |
| 7b11fb51 PA |
79 | #define X86_FEATURE_CONSTANT_TSC (3*32+ 8) /* TSC ticks at a constant rate */ |
| 80 | #define X86_FEATURE_UP (3*32+ 9) /* smp kernel running on up */ | |
| 7414aa41 | 81 | #define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* "" FXSAVE leaks FOP/FIP/FOP */ |
| 7b11fb51 | 82 | #define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */ |
| 0afe2db2 | 83 | #define X86_FEATURE_NOPL (3*32+20) /* The NOPL (0F 1F) instructions */ |
| b6734c35 PA |
84 | #define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */ |
| 85 | #define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */ | |
| 7414aa41 PA |
86 | #define X86_FEATURE_SYSCALL32 (3*32+14) /* "" syscall in ia32 userspace */ |
| 87 | #define X86_FEATURE_SYSENTER32 (3*32+15) /* "" sysenter in ia32 userspace */ | |
| 2798c63e | 88 | #define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well */ |
| 7414aa41 PA |
89 | #define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* "" Mfence synchronizes RDTSC */ |
| 90 | #define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* "" Lfence synchronizes RDTSC */ | |
| 91 | #define X86_FEATURE_11AP (3*32+19) /* "" Bad local APIC aka 11AP */ | |
| b6734c35 | 92 | #define X86_FEATURE_NOPL (3*32+20) /* The NOPL (0F 1F) instructions */ |
| a8d68290 | 93 | #define X86_FEATURE_AMDC1E (3*32+21) /* AMD C1E detected */ |
| 2576c999 | 94 | #define X86_FEATURE_XTOPOLOGY (3*32+22) /* cpu topology enum extensions */ |
| 7b11fb51 PA |
95 | |
| 96 | /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ | |
| 7414aa41 | 97 | #define X86_FEATURE_XMM3 (4*32+ 0) /* "pni" SSE-3 */ |
| f1240c00 PA |
98 | #define X86_FEATURE_PCLMULQDQ (4*32+ 1) /* PCLMULQDQ instruction */ |
| 99 | #define X86_FEATURE_DTES64 (4*32+ 2) /* 64-bit Debug Store */ | |
| 7414aa41 PA |
100 | #define X86_FEATURE_MWAIT (4*32+ 3) /* "monitor" Monitor/Mwait support */ |
| 101 | #define X86_FEATURE_DSCPL (4*32+ 4) /* "ds_cpl" CPL Qual. Debug Store */ | |
| 102 | #define X86_FEATURE_VMX (4*32+ 5) /* Hardware virtualization */ | |
| af2e1f27 | 103 | #define X86_FEATURE_SMX (4*32+ 6) /* Safer mode */ |
| 7b11fb51 PA |
104 | #define X86_FEATURE_EST (4*32+ 7) /* Enhanced SpeedStep */ |
| 105 | #define X86_FEATURE_TM2 (4*32+ 8) /* Thermal Monitor 2 */ | |
| 7414aa41 | 106 | #define X86_FEATURE_SSSE3 (4*32+ 9) /* Supplemental SSE-3 */ |
| 7b11fb51 | 107 | #define X86_FEATURE_CID (4*32+10) /* Context ID */ |
| f1240c00 | 108 | #define X86_FEATURE_FMA (4*32+12) /* Fused multiply-add */ |
| 7b11fb51 PA |
109 | #define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */ |
| 110 | #define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */ | |
| f1240c00 | 111 | #define X86_FEATURE_PDCM (4*32+15) /* Performance Capabilities */ |
| 7b11fb51 | 112 | #define X86_FEATURE_DCA (4*32+18) /* Direct Cache Access */ |
| 7414aa41 PA |
113 | #define X86_FEATURE_XMM4_1 (4*32+19) /* "sse4_1" SSE-4.1 */ |
| 114 | #define X86_FEATURE_XMM4_2 (4*32+20) /* "sse4_2" SSE-4.2 */ | |
| 32e1d0a0 | 115 | #define X86_FEATURE_X2APIC (4*32+21) /* x2APIC */ |
| f1240c00 PA |
116 | #define X86_FEATURE_AES (4*32+25) /* AES instructions */ |
| 117 | #define X86_FEATURE_XSAVE (4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */ | |
| 118 | #define X86_FEATURE_OSXSAVE (4*32+27) /* "" XSAVE enabled in the OS */ | |
| 119 | #define X86_FEATURE_AVX (4*32+28) /* Advanced Vector Extensions */ | |
| 7b11fb51 PA |
120 | |
| 121 | /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ | |
| 7414aa41 PA |
122 | #define X86_FEATURE_XSTORE (5*32+ 2) /* "rng" RNG present (xstore) */ |
| 123 | #define X86_FEATURE_XSTORE_EN (5*32+ 3) /* "rng_en" RNG enabled */ | |
| 124 | #define X86_FEATURE_XCRYPT (5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */ | |
| 125 | #define X86_FEATURE_XCRYPT_EN (5*32+ 7) /* "ace_en" on-CPU crypto enabled */ | |
| 7b11fb51 PA |
126 | #define X86_FEATURE_ACE2 (5*32+ 8) /* Advanced Cryptography Engine v2 */ |
| 127 | #define X86_FEATURE_ACE2_EN (5*32+ 9) /* ACE v2 enabled */ | |
| 7414aa41 PA |
128 | #define X86_FEATURE_PHE (5*32+10) /* PadLock Hash Engine */ |
| 129 | #define X86_FEATURE_PHE_EN (5*32+11) /* PHE enabled */ | |
| 130 | #define X86_FEATURE_PMM (5*32+12) /* PadLock Montgomery Multiplier */ | |
| 131 | #define X86_FEATURE_PMM_EN (5*32+13) /* PMM enabled */ | |
| 7b11fb51 PA |
132 | |
| 133 | /* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */ | |
| 134 | #define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */ | |
| 135 | #define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */ | |
| 7414aa41 PA |
136 | #define X86_FEATURE_SVM (6*32+ 2) /* Secure virtual machine */ |
| 137 | #define X86_FEATURE_EXTAPIC (6*32+ 3) /* Extended APIC space */ | |
| 138 | #define X86_FEATURE_CR8_LEGACY (6*32+ 4) /* CR8 in 32-bit mode */ | |
| 139 | #define X86_FEATURE_ABM (6*32+ 5) /* Advanced bit manipulation */ | |
| 140 | #define X86_FEATURE_SSE4A (6*32+ 6) /* SSE-4A */ | |
| 141 | #define X86_FEATURE_MISALIGNSSE (6*32+ 7) /* Misaligned SSE mode */ | |
| 142 | #define X86_FEATURE_3DNOWPREFETCH (6*32+ 8) /* 3DNow prefetch instructions */ | |
| 143 | #define X86_FEATURE_OSVW (6*32+ 9) /* OS Visible Workaround */ | |
| 144 | #define X86_FEATURE_IBS (6*32+10) /* Instruction Based Sampling */ | |
| 145 | #define X86_FEATURE_SSE5 (6*32+11) /* SSE-5 */ | |
| 146 | #define X86_FEATURE_SKINIT (6*32+12) /* SKINIT/STGI instructions */ | |
| 147 | #define X86_FEATURE_WDT (6*32+13) /* Watchdog timer */ | |
| 7b11fb51 PA |
148 | |
| 149 | /* | |
| 150 | * Auxiliary flags: Linux defined - For features scattered in various | |
| 151 | * CPUID levels like 0x6, 0xA etc | |
| 152 | */ | |
| 153 | #define X86_FEATURE_IDA (7*32+ 0) /* Intel Dynamic Acceleration */ | |
| 154 | ||
| e38e05a8 SY |
155 | /* Virtualization flags: Linux defined */ |
| 156 | #define X86_FEATURE_TPR_SHADOW (8*32+ 0) /* Intel TPR Shadow */ | |
| 157 | #define X86_FEATURE_VNMI (8*32+ 1) /* Intel Virtual NMI */ | |
| 158 | #define X86_FEATURE_FLEXPRIORITY (8*32+ 2) /* Intel FlexPriority */ | |
| 159 | #define X86_FEATURE_EPT (8*32+ 3) /* Intel Extended Page Table */ | |
| 160 | #define X86_FEATURE_VPID (8*32+ 4) /* Intel Virtual Processor ID */ | |
| 161 | ||
| fa1408e4 PA |
162 | #if defined(__KERNEL__) && !defined(__ASSEMBLY__) |
| 163 | ||
| 164 | #include <linux/bitops.h> | |
| 165 | ||
| 166 | extern const char * const x86_cap_flags[NCAPINTS*32]; | |
| 167 | extern const char * const x86_power_flags[32]; | |
| 168 | ||
| 0f8d2b92 IM |
169 | #define test_cpu_cap(c, bit) \ |
| 170 | test_bit(bit, (unsigned long *)((c)->x86_capability)) | |
| 171 | ||
| 7b11fb51 PA |
172 | #define cpu_has(c, bit) \ |
| 173 | (__builtin_constant_p(bit) && \ | |
| 174 | ( (((bit)>>5)==0 && (1UL<<((bit)&31) & REQUIRED_MASK0)) || \ | |
| 175 | (((bit)>>5)==1 && (1UL<<((bit)&31) & REQUIRED_MASK1)) || \ | |
| 176 | (((bit)>>5)==2 && (1UL<<((bit)&31) & REQUIRED_MASK2)) || \ | |
| 177 | (((bit)>>5)==3 && (1UL<<((bit)&31) & REQUIRED_MASK3)) || \ | |
| 178 | (((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4)) || \ | |
| 179 | (((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5)) || \ | |
| 180 | (((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6)) || \ | |
| 181 | (((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) ) \ | |
| 182 | ? 1 : \ | |
| 0f8d2b92 IM |
183 | test_cpu_cap(c, bit)) |
| 184 | ||
| 7b11fb51 PA |
185 | #define boot_cpu_has(bit) cpu_has(&boot_cpu_data, bit) |
| 186 | ||
| 53756d37 JF |
187 | #define set_cpu_cap(c, bit) set_bit(bit, (unsigned long *)((c)->x86_capability)) |
| 188 | #define clear_cpu_cap(c, bit) clear_bit(bit, (unsigned long *)((c)->x86_capability)) | |
| 7d851c8d AK |
189 | #define setup_clear_cpu_cap(bit) do { \ |
| 190 | clear_cpu_cap(&boot_cpu_data, bit); \ | |
| 23eb271b | 191 | set_bit(bit, (unsigned long *)cleared_cpu_caps); \ |
| 7d851c8d | 192 | } while (0) |
| 404ee5b1 AK |
193 | #define setup_force_cpu_cap(bit) do { \ |
| 194 | set_cpu_cap(&boot_cpu_data, bit); \ | |
| 2798c63e | 195 | clear_bit(bit, (unsigned long *)cleared_cpu_caps); \ |
| 404ee5b1 | 196 | } while (0) |
| 53756d37 | 197 | |
| 7b11fb51 PA |
198 | #define cpu_has_fpu boot_cpu_has(X86_FEATURE_FPU) |
| 199 | #define cpu_has_vme boot_cpu_has(X86_FEATURE_VME) | |
| 200 | #define cpu_has_de boot_cpu_has(X86_FEATURE_DE) | |
| 201 | #define cpu_has_pse boot_cpu_has(X86_FEATURE_PSE) | |
| 202 | #define cpu_has_tsc boot_cpu_has(X86_FEATURE_TSC) | |
| 203 | #define cpu_has_pae boot_cpu_has(X86_FEATURE_PAE) | |
| 204 | #define cpu_has_pge boot_cpu_has(X86_FEATURE_PGE) | |
| 205 | #define cpu_has_apic boot_cpu_has(X86_FEATURE_APIC) | |
| 206 | #define cpu_has_sep boot_cpu_has(X86_FEATURE_SEP) | |
| 207 | #define cpu_has_mtrr boot_cpu_has(X86_FEATURE_MTRR) | |
| 208 | #define cpu_has_mmx boot_cpu_has(X86_FEATURE_MMX) | |
| 209 | #define cpu_has_fxsr boot_cpu_has(X86_FEATURE_FXSR) | |
| 210 | #define cpu_has_xmm boot_cpu_has(X86_FEATURE_XMM) | |
| 211 | #define cpu_has_xmm2 boot_cpu_has(X86_FEATURE_XMM2) | |
| 212 | #define cpu_has_xmm3 boot_cpu_has(X86_FEATURE_XMM3) | |
| 213 | #define cpu_has_ht boot_cpu_has(X86_FEATURE_HT) | |
| 214 | #define cpu_has_mp boot_cpu_has(X86_FEATURE_MP) | |
| 215 | #define cpu_has_nx boot_cpu_has(X86_FEATURE_NX) | |
| 216 | #define cpu_has_k6_mtrr boot_cpu_has(X86_FEATURE_K6_MTRR) | |
| 217 | #define cpu_has_cyrix_arr boot_cpu_has(X86_FEATURE_CYRIX_ARR) | |
| 218 | #define cpu_has_centaur_mcr boot_cpu_has(X86_FEATURE_CENTAUR_MCR) | |
| 219 | #define cpu_has_xstore boot_cpu_has(X86_FEATURE_XSTORE) | |
| 220 | #define cpu_has_xstore_enabled boot_cpu_has(X86_FEATURE_XSTORE_EN) | |
| 221 | #define cpu_has_xcrypt boot_cpu_has(X86_FEATURE_XCRYPT) | |
| 222 | #define cpu_has_xcrypt_enabled boot_cpu_has(X86_FEATURE_XCRYPT_EN) | |
| 223 | #define cpu_has_ace2 boot_cpu_has(X86_FEATURE_ACE2) | |
| 224 | #define cpu_has_ace2_enabled boot_cpu_has(X86_FEATURE_ACE2_EN) | |
| 225 | #define cpu_has_phe boot_cpu_has(X86_FEATURE_PHE) | |
| 226 | #define cpu_has_phe_enabled boot_cpu_has(X86_FEATURE_PHE_EN) | |
| 227 | #define cpu_has_pmm boot_cpu_has(X86_FEATURE_PMM) | |
| 228 | #define cpu_has_pmm_enabled boot_cpu_has(X86_FEATURE_PMM_EN) | |
| 229 | #define cpu_has_ds boot_cpu_has(X86_FEATURE_DS) | |
| 230 | #define cpu_has_pebs boot_cpu_has(X86_FEATURE_PEBS) | |
| 231 | #define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLSH) | |
| 232 | #define cpu_has_bts boot_cpu_has(X86_FEATURE_BTS) | |
| 019c3e7c | 233 | #define cpu_has_gbpages boot_cpu_has(X86_FEATURE_GBPAGES) |
| 86975101 | 234 | #define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON) |
| 2e5d9c85 | 235 | #define cpu_has_pat boot_cpu_has(X86_FEATURE_PAT) |
| f1240c00 | 236 | #define cpu_has_xmm4_1 boot_cpu_has(X86_FEATURE_XMM4_1) |
| 2a61812a | 237 | #define cpu_has_xmm4_2 boot_cpu_has(X86_FEATURE_XMM4_2) |
| 32e1d0a0 | 238 | #define cpu_has_x2apic boot_cpu_has(X86_FEATURE_X2APIC) |
| f1240c00 | 239 | #define cpu_has_xsave boot_cpu_has(X86_FEATURE_XSAVE) |
| 7b11fb51 | 240 | |
| 0b9c99b6 TG |
241 | #if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64) |
| 242 | # define cpu_has_invlpg 1 | |
| 243 | #else | |
| 244 | # define cpu_has_invlpg (boot_cpu_data.x86 > 3) | |
| 245 | #endif | |
| 246 | ||
| 7b11fb51 PA |
247 | #ifdef CONFIG_X86_64 |
| 248 | ||
| 249 | #undef cpu_has_vme | |
| 250 | #define cpu_has_vme 0 | |
| 251 | ||
| 252 | #undef cpu_has_pae | |
| 253 | #define cpu_has_pae ___BUG___ | |
| 254 | ||
| 255 | #undef cpu_has_mp | |
| 256 | #define cpu_has_mp 1 | |
| 257 | ||
| 258 | #undef cpu_has_k6_mtrr | |
| 259 | #define cpu_has_k6_mtrr 0 | |
| 260 | ||
| 261 | #undef cpu_has_cyrix_arr | |
| 262 | #define cpu_has_cyrix_arr 0 | |
| 263 | ||
| 264 | #undef cpu_has_centaur_mcr | |
| 265 | #define cpu_has_centaur_mcr 0 | |
| 266 | ||
| 267 | #endif /* CONFIG_X86_64 */ | |
| 268 | ||
| fa1408e4 PA |
269 | #endif /* defined(__KERNEL__) && !defined(__ASSEMBLY__) */ |
| 270 | ||
| 1965aae3 | 271 | #endif /* _ASM_X86_CPUFEATURE_H */ |