[deliverable/linux.git] / arch / x86 / include / asm / debugreg.h

#ifndef _ASM_X86_DEBUGREG_H
#define _ASM_X86_DEBUGREG_H


/* Indicate the register numbers for a number of the specific
   debug registers.  Registers 0-3 contain the addresses we wish to trap on */
#define DR_FIRSTADDR 0        /* u_debugreg[DR_FIRSTADDR] */
#define DR_LASTADDR 3         /* u_debugreg[DR_LASTADDR]  */

#define DR_STATUS 6           /* u_debugreg[DR_STATUS]     */
#define DR_CONTROL 7          /* u_debugreg[DR_CONTROL] */

/* Define a few things for the status register.  We can use this to determine
   which debugging register was responsible for the trap.  The other bits
   are either reserved or not of interest to us. */

/* Define reserved bits in DR6 which are always set to 1 */
#define DR6_RESERVED	(0xFFFF0FF0)

#define DR_TRAP0	(0x1)		/* db0 */
#define DR_TRAP1	(0x2)		/* db1 */
#define DR_TRAP2	(0x4)		/* db2 */
#define DR_TRAP3	(0x8)		/* db3 */
#define DR_TRAP_BITS	(DR_TRAP0|DR_TRAP1|DR_TRAP2|DR_TRAP3)

#define DR_STEP		(0x4000)	/* single-step */
#define DR_SWITCH	(0x8000)	/* task switch */

/* Now define a bunch of things for manipulating the control register.
   The top two bytes of the control register consist of 4 fields of 4
   bits - each field corresponds to one of the four debug registers,
   and indicates what types of access we trap on, and how large the data
   field is that we are looking at */

#define DR_CONTROL_SHIFT 16 /* Skip this many bits in ctl register */
#define DR_CONTROL_SIZE 4   /* 4 control bits per register */

#define DR_RW_EXECUTE (0x0)   /* Settings for the access types to trap on */
#define DR_RW_WRITE (0x1)
#define DR_RW_READ (0x3)

#define DR_LEN_1 (0x0) /* Settings for data length to trap on */
#define DR_LEN_2 (0x4)
#define DR_LEN_4 (0xC)
#define DR_LEN_8 (0x8)

/* The low byte to the control register determine which registers are
   enabled.  There are 4 fields of two bits.  One bit is "local", meaning
   that the processor will reset the bit after a task switch and the other
   is global meaning that we have to explicitly reset the bit.  With linux,
   you can use either one, since we explicitly zero the register when we enter
   kernel mode. */

#define DR_LOCAL_ENABLE_SHIFT 0    /* Extra shift to the local enable bit */
#define DR_GLOBAL_ENABLE_SHIFT 1   /* Extra shift to the global enable bit */
#define DR_LOCAL_ENABLE (0x1)      /* Local enable for reg 0 */
#define DR_GLOBAL_ENABLE (0x2)     /* Global enable for reg 0 */
#define DR_ENABLE_SIZE 2           /* 2 enable bits per register */

#define DR_LOCAL_ENABLE_MASK (0x55)  /* Set  local bits for all 4 regs */
#define DR_GLOBAL_ENABLE_MASK (0xAA) /* Set global bits for all 4 regs */

/* The second byte to the control register has a few special things.
   We can slow the instruction pipeline for instructions coming via the
   gdt or the ldt if we want to.  I am not sure why this is an advantage */

#ifdef __i386__
#define DR_CONTROL_RESERVED (0xFC00) /* Reserved by Intel */
#else
#define DR_CONTROL_RESERVED (0xFFFFFFFF0000FC00UL) /* Reserved */
#endif

#define DR_LOCAL_SLOWDOWN (0x100)   /* Local slow the pipeline */
#define DR_GLOBAL_SLOWDOWN (0x200)  /* Global slow the pipeline */

/*
 * HW breakpoint additions
 */
#ifdef __KERNEL__

#include <linux/bug.h>

DECLARE_PER_CPU(unsigned long, cpu_dr7);

#ifndef CONFIG_PARAVIRT
/*
 * These special macros can be used to get or set a debugging register
 */
#define get_debugreg(var, register)				\
	(var) = native_get_debugreg(register)
#define set_debugreg(value, register)				\
	native_set_debugreg(register, value)
#endif

static inline unsigned long native_get_debugreg(int regno)
{
	unsigned long val = 0;	/* Damn you, gcc! */

	switch (regno) {
	case 0:
		asm("mov %%db0, %0" :"=r" (val));
		break;
	case 1:
		asm("mov %%db1, %0" :"=r" (val));
		break;
	case 2:
		asm("mov %%db2, %0" :"=r" (val));
		break;
	case 3:
		asm("mov %%db3, %0" :"=r" (val));
		break;
	case 6:
		asm("mov %%db6, %0" :"=r" (val));
		break;
	case 7:
		asm("mov %%db7, %0" :"=r" (val));
		break;
	default:
		BUG();
	}
	return val;
}

static inline void native_set_debugreg(int regno, unsigned long value)
{
	switch (regno) {
	case 0:
		asm("mov %0, %%db0"	::"r" (value));
		break;
	case 1:
		asm("mov %0, %%db1"	::"r" (value));
		break;
	case 2:
		asm("mov %0, %%db2"	::"r" (value));
		break;
	case 3:
		asm("mov %0, %%db3"	::"r" (value));
		break;
	case 6:
		asm("mov %0, %%db6"	::"r" (value));
		break;
	case 7:
		asm("mov %0, %%db7"	::"r" (value));
		break;
	default:
		BUG();
	}
}

static inline void hw_breakpoint_disable(void)
{
	/* Zero the control register for HW Breakpoint */
	set_debugreg(0UL, 7);

	/* Zero-out the individual HW breakpoint address registers */
	set_debugreg(0UL, 0);
	set_debugreg(0UL, 1);
	set_debugreg(0UL, 2);
	set_debugreg(0UL, 3);
}

static inline int hw_breakpoint_active(void)
{
	return __this_cpu_read(cpu_dr7) & DR_GLOBAL_ENABLE_MASK;
}

extern void aout_dump_debugregs(struct user *dump);

extern void hw_breakpoint_restore(void);

#ifdef CONFIG_X86_64
DECLARE_PER_CPU(int, debug_stack_usage);
static inline void debug_stack_usage_inc(void)
{
	__get_cpu_var(debug_stack_usage)++;
}
static inline void debug_stack_usage_dec(void)
{
	__get_cpu_var(debug_stack_usage)--;
}
int is_debug_stack(unsigned long addr);
void debug_stack_set_zero(void);
void debug_stack_reset(void);
#else /* !X86_64 */
static inline int is_debug_stack(unsigned long addr) { return 0; }
static inline void debug_stack_set_zero(void) { }
static inline void debug_stack_reset(void) { }
static inline void debug_stack_usage_inc(void) { }
static inline void debug_stack_usage_dec(void) { }
#endif /* X86_64 */


#endif	/* __KERNEL__ */

#endif /* _ASM_X86_DEBUGREG_H */
Commit	Line	Data
1965aae3 PA	1	#ifndef _ASM_X86_DEBUGREG_H
1965aae3 PA	2	#define _ASM_X86_DEBUGREG_H
21ebddd3 TG	3
	4
	5	/* Indicate the register numbers for a number of the specific
	6	debug registers. Registers 0-3 contain the addresses we wish to trap on */
	7	#define DR_FIRSTADDR 0 /* u_debugreg[DR_FIRSTADDR] */
	8	#define DR_LASTADDR 3 /* u_debugreg[DR_LASTADDR] */
	9
	10	#define DR_STATUS 6 /* u_debugreg[DR_STATUS] */
	11	#define DR_CONTROL 7 /* u_debugreg[DR_CONTROL] */
	12
	13	/* Define a few things for the status register. We can use this to determine
	14	which debugging register was responsible for the trap. The other bits
	15	are either reserved or not of interest to us. */
	16
40f9249a P	17	/* Define reserved bits in DR6 which are always set to 1 */
	18	#define DR6_RESERVED (0xFFFF0FF0)
	19
21ebddd3 TG	20	#define DR_TRAP0 (0x1) /* db0 */
	21	#define DR_TRAP1 (0x2) /* db1 */
	22	#define DR_TRAP2 (0x4) /* db2 */
	23	#define DR_TRAP3 (0x8) /* db3 */
b332828c	24	#define DR_TRAP_BITS (DR_TRAP0\|DR_TRAP1\|DR_TRAP2\|DR_TRAP3)
21ebddd3 TG	25
	26	#define DR_STEP (0x4000) /* single-step */
	27	#define DR_SWITCH (0x8000) /* task switch */
	28
	29	/* Now define a bunch of things for manipulating the control register.
	30	The top two bytes of the control register consist of 4 fields of 4
	31	bits - each field corresponds to one of the four debug registers,
	32	and indicates what types of access we trap on, and how large the data
	33	field is that we are looking at */
	34
	35	#define DR_CONTROL_SHIFT 16 /* Skip this many bits in ctl register */
	36	#define DR_CONTROL_SIZE 4 /* 4 control bits per register */
	37
	38	#define DR_RW_EXECUTE (0x0) /* Settings for the access types to trap on */
	39	#define DR_RW_WRITE (0x1)
	40	#define DR_RW_READ (0x3)
	41
	42	#define DR_LEN_1 (0x0) /* Settings for data length to trap on */
	43	#define DR_LEN_2 (0x4)
	44	#define DR_LEN_4 (0xC)
	45	#define DR_LEN_8 (0x8)
	46
	47	/* The low byte to the control register determine which registers are
	48	enabled. There are 4 fields of two bits. One bit is "local", meaning
	49	that the processor will reset the bit after a task switch and the other
	50	is global meaning that we have to explicitly reset the bit. With linux,
	51	you can use either one, since we explicitly zero the register when we enter
	52	kernel mode. */
	53
	54	#define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit */
	55	#define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit */
b332828c P	56	#define DR_LOCAL_ENABLE (0x1) /* Local enable for reg 0 */
b332828c P	57	#define DR_GLOBAL_ENABLE (0x2) /* Global enable for reg 0 */
21ebddd3 TG	58	#define DR_ENABLE_SIZE 2 /* 2 enable bits per register */
	59
	60	#define DR_LOCAL_ENABLE_MASK (0x55) /* Set local bits for all 4 regs */
	61	#define DR_GLOBAL_ENABLE_MASK (0xAA) /* Set global bits for all 4 regs */
	62
	63	/* The second byte to the control register has a few special things.
	64	We can slow the instruction pipeline for instructions coming via the
	65	gdt or the ldt if we want to. I am not sure why this is an advantage */
	66
	67	#ifdef __i386__
	68	#define DR_CONTROL_RESERVED (0xFC00) /* Reserved by Intel */
96a388de	69	#else
21ebddd3 TG	70	#define DR_CONTROL_RESERVED (0xFFFFFFFF0000FC00UL) /* Reserved */
	71	#endif
	72
	73	#define DR_LOCAL_SLOWDOWN (0x100) /* Local slow the pipeline */
	74	#define DR_GLOBAL_SLOWDOWN (0x200) /* Global slow the pipeline */
	75
b332828c P	76	/*
	77	* HW breakpoint additions
	78	*/
	79	#ifdef __KERNEL__
	80
f649e938 PG	81	#include <linux/bug.h>
f649e938 PG	82
28b4e0d8	83	DECLARE_PER_CPU(unsigned long, cpu_dr7);
b332828c	84
f649e938 PG	85	#ifndef CONFIG_PARAVIRT
	86	/*
	87	* These special macros can be used to get or set a debugging register
	88	*/
	89	#define get_debugreg(var, register) \
	90	(var) = native_get_debugreg(register)
	91	#define set_debugreg(value, register) \
	92	native_set_debugreg(register, value)
	93	#endif
	94
	95	static inline unsigned long native_get_debugreg(int regno)
	96	{
	97	unsigned long val = 0; /* Damn you, gcc! */
	98
	99	switch (regno) {
	100	case 0:
	101	asm("mov %%db0, %0" :"=r" (val));
	102	break;
	103	case 1:
	104	asm("mov %%db1, %0" :"=r" (val));
	105	break;
	106	case 2:
	107	asm("mov %%db2, %0" :"=r" (val));
	108	break;
	109	case 3:
	110	asm("mov %%db3, %0" :"=r" (val));
	111	break;
	112	case 6:
	113	asm("mov %%db6, %0" :"=r" (val));
	114	break;
	115	case 7:
	116	asm("mov %%db7, %0" :"=r" (val));
	117	break;
	118	default:
	119	BUG();
	120	}
	121	return val;
	122	}
	123
	124	static inline void native_set_debugreg(int regno, unsigned long value)
	125	{
	126	switch (regno) {
	127	case 0:
	128	asm("mov %0, %%db0" ::"r" (value));
	129	break;
	130	case 1:
	131	asm("mov %0, %%db1" ::"r" (value));
	132	break;
	133	case 2:
	134	asm("mov %0, %%db2" ::"r" (value));
	135	break;
	136	case 3:
	137	asm("mov %0, %%db3" ::"r" (value));
	138	break;
	139	case 6:
	140	asm("mov %0, %%db6" ::"r" (value));
	141	break;
	142	case 7:
	143	asm("mov %0, %%db7" ::"r" (value));
	144	break;
	145	default:
	146	BUG();
	147	}
	148	}
149
b332828c P	150	static inline void hw_breakpoint_disable(void)
	151	{
	152	/* Zero the control register for HW Breakpoint */
	153	set_debugreg(0UL, 7);
	154
	155	/* Zero-out the individual HW breakpoint address registers */
	156	set_debugreg(0UL, 0);
	157	set_debugreg(0UL, 1);
	158	set_debugreg(0UL, 2);
	159	set_debugreg(0UL, 3);
	160	}
	161
59d8eb53 FW	162	static inline int hw_breakpoint_active(void)
59d8eb53 FW	163	{
0a3aee0d	164	return __this_cpu_read(cpu_dr7) & DR_GLOBAL_ENABLE_MASK;
59d8eb53 FW	165	}
59d8eb53 FW	166
9f6b3c2c FW	167	extern void aout_dump_debugregs(struct user *dump);
9f6b3c2c FW	168
24f1e32c	169	extern void hw_breakpoint_restore(void);
24f1e32c	170
42181186 SR	171	#ifdef CONFIG_X86_64
	172	DECLARE_PER_CPU(int, debug_stack_usage);
	173	static inline void debug_stack_usage_inc(void)
	174	{
	175	__get_cpu_var(debug_stack_usage)++;
	176	}
	177	static inline void debug_stack_usage_dec(void)
	178	{
	179	__get_cpu_var(debug_stack_usage)--;
	180	}
	181	int is_debug_stack(unsigned long addr);
	182	void debug_stack_set_zero(void);
	183	void debug_stack_reset(void);
	184	#else /* !X86_64 */
	185	static inline int is_debug_stack(unsigned long addr) { return 0; }
	186	static inline void debug_stack_set_zero(void) { }
	187	static inline void debug_stack_reset(void) { }
	188	static inline void debug_stack_usage_inc(void) { }
	189	static inline void debug_stack_usage_dec(void) { }
	190	#endif /* X86_64 */
	191
	192
b332828c P	193	#endif /* __KERNEL__ */
b332828c P	194
1965aae3	195	#endif /* _ASM_X86_DEBUGREG_H */