[deliverable/linux.git] / arch / x86 / include / asm / desc.h

#ifndef _ASM_X86_DESC_H
#define _ASM_X86_DESC_H

#ifndef __ASSEMBLY__
#include <asm/desc_defs.h>
#include <asm/ldt.h>
#include <asm/mmu.h>
#include <linux/smp.h>

static inline void fill_ldt(struct desc_struct *desc,
			    const struct user_desc *info)
{
	desc->limit0 = info->limit & 0x0ffff;
	desc->base0 = info->base_addr & 0x0000ffff;

	desc->base1 = (info->base_addr & 0x00ff0000) >> 16;
	desc->type = (info->read_exec_only ^ 1) << 1;
	desc->type |= info->contents << 2;
	desc->s = 1;
	desc->dpl = 0x3;
	desc->p = info->seg_not_present ^ 1;
	desc->limit = (info->limit & 0xf0000) >> 16;
	desc->avl = info->useable;
	desc->d = info->seg_32bit;
	desc->g = info->limit_in_pages;
	desc->base2 = (info->base_addr & 0xff000000) >> 24;
	/*
	 * Don't allow setting of the lm bit. It is useless anyway
	 * because 64bit system calls require __USER_CS:
	 */
	desc->l = 0;
}

extern struct desc_ptr idt_descr;
extern gate_desc idt_table[];

struct gdt_page {
	struct desc_struct gdt[GDT_ENTRIES];
} __attribute__((aligned(PAGE_SIZE)));
DECLARE_PER_CPU(struct gdt_page, gdt_page);

static inline struct desc_struct *get_cpu_gdt_table(unsigned int cpu)
{
	return per_cpu(gdt_page, cpu).gdt;
}

#ifdef CONFIG_X86_64

static inline void pack_gate(gate_desc *gate, unsigned type, unsigned long func,
			     unsigned dpl, unsigned ist, unsigned seg)
{
	gate->offset_low = PTR_LOW(func);
	gate->segment = __KERNEL_CS;
	gate->ist = ist;
	gate->p = 1;
	gate->dpl = dpl;
	gate->zero0 = 0;
	gate->zero1 = 0;
	gate->type = type;
	gate->offset_middle = PTR_MIDDLE(func);
	gate->offset_high = PTR_HIGH(func);
}

#else
static inline void pack_gate(gate_desc *gate, unsigned char type,
			     unsigned long base, unsigned dpl, unsigned flags,
			     unsigned short seg)
{
	gate->a = (seg << 16) | (base & 0xffff);
	gate->b = (base & 0xffff0000) |
		  (((0x80 | type | (dpl << 5)) & 0xff) << 8);
}

#endif

static inline int desc_empty(const void *ptr)
{
	const u32 *desc = ptr;
	return !(desc[0] | desc[1]);
}

#ifdef CONFIG_PARAVIRT
#include <asm/paravirt.h>
#else
#define load_TR_desc() native_load_tr_desc()
#define load_gdt(dtr) native_load_gdt(dtr)
#define load_idt(dtr) native_load_idt(dtr)
#define load_tr(tr) asm volatile("ltr %0"::"m" (tr))
#define load_ldt(ldt) asm volatile("lldt %0"::"m" (ldt))

#define store_gdt(dtr) native_store_gdt(dtr)
#define store_idt(dtr) native_store_idt(dtr)
#define store_tr(tr) (tr = native_store_tr())
#define store_ldt(ldt) asm("sldt %0":"=m" (ldt))

#define load_TLS(t, cpu) native_load_tls(t, cpu)
#define set_ldt native_set_ldt

#define write_ldt_entry(dt, entry, desc)	\
	native_write_ldt_entry(dt, entry, desc)
#define write_gdt_entry(dt, entry, desc, type)		\
	native_write_gdt_entry(dt, entry, desc, type)
#define write_idt_entry(dt, entry, g)		\
	native_write_idt_entry(dt, entry, g)

static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries)
{
}

static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries)
{
}
#endif	/* CONFIG_PARAVIRT */

static inline void native_write_idt_entry(gate_desc *idt, int entry,
					  const gate_desc *gate)
{
	memcpy(&idt[entry], gate, sizeof(*gate));
}

static inline void native_write_ldt_entry(struct desc_struct *ldt, int entry,
					  const void *desc)
{
	memcpy(&ldt[entry], desc, 8);
}

static inline void native_write_gdt_entry(struct desc_struct *gdt, int entry,
					  const void *desc, int type)
{
	unsigned int size;
	switch (type) {
	case DESC_TSS:
		size = sizeof(tss_desc);
		break;
	case DESC_LDT:
		size = sizeof(ldt_desc);
		break;
	default:
		size = sizeof(struct desc_struct);
		break;
	}
	memcpy(&gdt[entry], desc, size);
}

static inline void pack_descriptor(struct desc_struct *desc, unsigned long base,
				   unsigned long limit, unsigned char type,
				   unsigned char flags)
{
	desc->a = ((base & 0xffff) << 16) | (limit & 0xffff);
	desc->b = (base & 0xff000000) | ((base & 0xff0000) >> 16) |
		(limit & 0x000f0000) | ((type & 0xff) << 8) |
		((flags & 0xf) << 20);
	desc->p = 1;
}


static inline void set_tssldt_descriptor(void *d, unsigned long addr,
					 unsigned type, unsigned size)
{
#ifdef CONFIG_X86_64
	struct ldttss_desc64 *desc = d;
	memset(desc, 0, sizeof(*desc));
	desc->limit0 = size & 0xFFFF;
	desc->base0 = PTR_LOW(addr);
	desc->base1 = PTR_MIDDLE(addr) & 0xFF;
	desc->type = type;
	desc->p = 1;
	desc->limit1 = (size >> 16) & 0xF;
	desc->base2 = (PTR_MIDDLE(addr) >> 8) & 0xFF;
	desc->base3 = PTR_HIGH(addr);
#else
	pack_descriptor((struct desc_struct *)d, addr, size, 0x80 | type, 0);
#endif
}

static inline void __set_tss_desc(unsigned cpu, unsigned int entry, void *addr)
{
	struct desc_struct *d = get_cpu_gdt_table(cpu);
	tss_desc tss;

	/*
	 * sizeof(unsigned long) coming from an extra "long" at the end
	 * of the iobitmap. See tss_struct definition in processor.h
	 *
	 * -1? seg base+limit should be pointing to the address of the
	 * last valid byte
	 */
	set_tssldt_descriptor(&tss, (unsigned long)addr, DESC_TSS,
			      IO_BITMAP_OFFSET + IO_BITMAP_BYTES +
			      sizeof(unsigned long) - 1);
	write_gdt_entry(d, entry, &tss, DESC_TSS);
}

#define set_tss_desc(cpu, addr) __set_tss_desc(cpu, GDT_ENTRY_TSS, addr)

static inline void native_set_ldt(const void *addr, unsigned int entries)
{
	if (likely(entries == 0))
		asm volatile("lldt %w0"::"q" (0));
	else {
		unsigned cpu = smp_processor_id();
		ldt_desc ldt;

		set_tssldt_descriptor(&ldt, (unsigned long)addr, DESC_LDT,
				      entries * LDT_ENTRY_SIZE - 1);
		write_gdt_entry(get_cpu_gdt_table(cpu), GDT_ENTRY_LDT,
				&ldt, DESC_LDT);
		asm volatile("lldt %w0"::"q" (GDT_ENTRY_LDT*8));
	}
}

static inline void native_load_tr_desc(void)
{
	asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8));
}

static inline void native_load_gdt(const struct desc_ptr *dtr)
{
	asm volatile("lgdt %0"::"m" (*dtr));
}

static inline void native_load_idt(const struct desc_ptr *dtr)
{
	asm volatile("lidt %0"::"m" (*dtr));
}

static inline void native_store_gdt(struct desc_ptr *dtr)
{
	asm volatile("sgdt %0":"=m" (*dtr));
}

static inline void native_store_idt(struct desc_ptr *dtr)
{
	asm volatile("sidt %0":"=m" (*dtr));
}

static inline unsigned long native_store_tr(void)
{
	unsigned long tr;
	asm volatile("str %0":"=r" (tr));
	return tr;
}

static inline void native_load_tls(struct thread_struct *t, unsigned int cpu)
{
	unsigned int i;
	struct desc_struct *gdt = get_cpu_gdt_table(cpu);

	for (i = 0; i < GDT_ENTRY_TLS_ENTRIES; i++)
		gdt[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i];
}

#define _LDT_empty(info)				\
	((info)->base_addr		== 0	&&	\
	 (info)->limit			== 0	&&	\
	 (info)->contents		== 0	&&	\
	 (info)->read_exec_only		== 1	&&	\
	 (info)->seg_32bit		== 0	&&	\
	 (info)->limit_in_pages		== 0	&&	\
	 (info)->seg_not_present	== 1	&&	\
	 (info)->useable		== 0)

#ifdef CONFIG_X86_64
#define LDT_empty(info) (_LDT_empty(info) && ((info)->lm == 0))
#else
#define LDT_empty(info) (_LDT_empty(info))
#endif

static inline void clear_LDT(void)
{
	set_ldt(NULL, 0);
}

/*
 * load one particular LDT into the current CPU
 */
static inline void load_LDT_nolock(mm_context_t *pc)
{
	set_ldt(pc->ldt, pc->size);
}

static inline void load_LDT(mm_context_t *pc)
{
	preempt_disable();
	load_LDT_nolock(pc);
	preempt_enable();
}

static inline unsigned long get_desc_base(const struct desc_struct *desc)
{
	return desc->base0 | ((desc->base1) << 16) | ((desc->base2) << 24);
}

static inline unsigned long get_desc_limit(const struct desc_struct *desc)
{
	return desc->limit0 | (desc->limit << 16);
}

static inline void _set_gate(int gate, unsigned type, void *addr,
			     unsigned dpl, unsigned ist, unsigned seg)
{
	gate_desc s;
	pack_gate(&s, type, (unsigned long)addr, dpl, ist, seg);
	/*
	 * does not need to be atomic because it is only done once at
	 * setup time
	 */
	write_idt_entry(idt_table, gate, &s);
}

/*
 * This needs to use 'idt_table' rather than 'idt', and
 * thus use the _nonmapped_ version of the IDT, as the
 * Pentium F0 0F bugfix can have resulted in the mapped
 * IDT being write-protected.
 */
static inline void set_intr_gate(unsigned int n, void *addr)
{
	BUG_ON((unsigned)n > 0xFF);
	_set_gate(n, GATE_INTERRUPT, addr, 0, 0, __KERNEL_CS);
}

#define SYS_VECTOR_FREE		0
#define SYS_VECTOR_ALLOCED	1

extern int first_system_vector;
extern char system_vectors[];

static inline void alloc_system_vector(int vector)
{
	if (system_vectors[vector] == SYS_VECTOR_FREE) {
		system_vectors[vector] = SYS_VECTOR_ALLOCED;
		if (first_system_vector > vector)
			first_system_vector = vector;
	} else
		BUG();
}

static inline void alloc_intr_gate(unsigned int n, void *addr)
{
	alloc_system_vector(n);
	set_intr_gate(n, addr);
}

/*
 * This routine sets up an interrupt gate at directory privilege level 3.
 */
static inline void set_system_intr_gate(unsigned int n, void *addr)
{
	BUG_ON((unsigned)n > 0xFF);
	_set_gate(n, GATE_INTERRUPT, addr, 0x3, 0, __KERNEL_CS);
}

static inline void set_system_trap_gate(unsigned int n, void *addr)
{
	BUG_ON((unsigned)n > 0xFF);
	_set_gate(n, GATE_TRAP, addr, 0x3, 0, __KERNEL_CS);
}

static inline void set_trap_gate(unsigned int n, void *addr)
{
	BUG_ON((unsigned)n > 0xFF);
	_set_gate(n, GATE_TRAP, addr, 0, 0, __KERNEL_CS);
}

static inline void set_task_gate(unsigned int n, unsigned int gdt_entry)
{
	BUG_ON((unsigned)n > 0xFF);
	_set_gate(n, GATE_TASK, (void *)0, 0, 0, (gdt_entry<<3));
}

static inline void set_intr_gate_ist(int n, void *addr, unsigned ist)
{
	BUG_ON((unsigned)n > 0xFF);
	_set_gate(n, GATE_INTERRUPT, addr, 0, ist, __KERNEL_CS);
}

static inline void set_system_intr_gate_ist(int n, void *addr, unsigned ist)
{
	BUG_ON((unsigned)n > 0xFF);
	_set_gate(n, GATE_INTERRUPT, addr, 0x3, ist, __KERNEL_CS);
}

#else
/*
 * GET_DESC_BASE reads the descriptor base of the specified segment.
 *
 * Args:
 *    idx - descriptor index
 *    gdt - GDT pointer
 *    base - 32bit register to which the base will be written
 *    lo_w - lo word of the "base" register
 *    lo_b - lo byte of the "base" register
 *    hi_b - hi byte of the low word of the "base" register
 *
 * Example:
 *    GET_DESC_BASE(GDT_ENTRY_ESPFIX_SS, %ebx, %eax, %ax, %al, %ah)
 *    Will read the base address of GDT_ENTRY_ESPFIX_SS and put it into %eax.
 */
#define GET_DESC_BASE(idx, gdt, base, lo_w, lo_b, hi_b) \
	movb idx * 8 + 4(gdt), lo_b;			\
	movb idx * 8 + 7(gdt), hi_b;			\
	shll $16, base;					\
	movw idx * 8 + 2(gdt), lo_w;


#endif /* __ASSEMBLY__ */

#endif /* _ASM_X86_DESC_H */
Commit	Line	Data
1965aae3 PA	1	#ifndef _ASM_X86_DESC_H
1965aae3 PA	2	#define _ASM_X86_DESC_H
80fbb69a GOC	3
	4	#ifndef __ASSEMBLY__
	5	#include <asm/desc_defs.h>
	6	#include <asm/ldt.h>
881c2975	7	#include <asm/mmu.h>
54cd0eac	8	#include <linux/smp.h>
80fbb69a	9
1bd5718c RM	10	static inline void fill_ldt(struct desc_struct *desc,
1bd5718c RM	11	const struct user_desc *info)
80fbb69a GOC	12	{
	13	desc->limit0 = info->limit & 0x0ffff;
	14	desc->base0 = info->base_addr & 0x0000ffff;
	15
	16	desc->base1 = (info->base_addr & 0x00ff0000) >> 16;
	17	desc->type = (info->read_exec_only ^ 1) << 1;
	18	desc->type \|= info->contents << 2;
	19	desc->s = 1;
	20	desc->dpl = 0x3;
	21	desc->p = info->seg_not_present ^ 1;
	22	desc->limit = (info->limit & 0xf0000) >> 16;
	23	desc->avl = info->useable;
	24	desc->d = info->seg_32bit;
	25	desc->g = info->limit_in_pages;
	26	desc->base2 = (info->base_addr & 0xff000000) >> 24;
64f53a04 JF	27	/*
	28	* Don't allow setting of the lm bit. It is useless anyway
	29	* because 64bit system calls require __USER_CS:
	30	*/
	31	desc->l = 0;
80fbb69a GOC	32	}
80fbb69a GOC	33
881c2975 GOC	34	extern struct desc_ptr idt_descr;
881c2975 GOC	35	extern gate_desc idt_table[];
80fbb69a	36
a939098a GC	37	struct gdt_page {
	38	struct desc_struct gdt[GDT_ENTRIES];
	39	} __attribute__((aligned(PAGE_SIZE)));
	40	DECLARE_PER_CPU(struct gdt_page, gdt_page);
	41
	42	static inline struct desc_struct *get_cpu_gdt_table(unsigned int cpu)
	43	{
	44	return per_cpu(gdt_page, cpu).gdt;
	45	}
	46
54cd0eac	47	#ifdef CONFIG_X86_64
507f90c9 GOC	48
	49	static inline void pack_gate(gate_desc *gate, unsigned type, unsigned long func,
	50	unsigned dpl, unsigned ist, unsigned seg)
	51	{
	52	gate->offset_low = PTR_LOW(func);
	53	gate->segment = __KERNEL_CS;
	54	gate->ist = ist;
	55	gate->p = 1;
	56	gate->dpl = dpl;
	57	gate->zero0 = 0;
	58	gate->zero1 = 0;
	59	gate->type = type;
	60	gate->offset_middle = PTR_MIDDLE(func);
	61	gate->offset_high = PTR_HIGH(func);
	62	}
	63
54cd0eac	64	#else
507f90c9	65	static inline void pack_gate(gate_desc *gate, unsigned char type,
c1773a16 JP	66	unsigned long base, unsigned dpl, unsigned flags,
c1773a16 JP	67	unsigned short seg)
507f90c9 GOC	68	{
	69	gate->a = (seg << 16) \| (base & 0xffff);
	70	gate->b = (base & 0xffff0000) \|
	71	(((0x80 \| type \| (dpl << 5)) & 0xff) << 8);
	72	}
	73
54cd0eac GOC	74	#endif
54cd0eac GOC	75
746ff60f GOC	76	static inline int desc_empty(const void *ptr)
	77	{
	78	const u32 *desc = ptr;
	79	return !(desc[0] \| desc[1]);
	80	}
	81
54cd0eac GOC	82	#ifdef CONFIG_PARAVIRT
	83	#include <asm/paravirt.h>
	84	#else
	85	#define load_TR_desc() native_load_tr_desc()
	86	#define load_gdt(dtr) native_load_gdt(dtr)
	87	#define load_idt(dtr) native_load_idt(dtr)
c1773a16 JP	88	#define load_tr(tr) asm volatile("ltr %0"::"m" (tr))
c1773a16 JP	89	#define load_ldt(ldt) asm volatile("lldt %0"::"m" (ldt))
54cd0eac GOC	90
	91	#define store_gdt(dtr) native_store_gdt(dtr)
	92	#define store_idt(dtr) native_store_idt(dtr)
	93	#define store_tr(tr) (tr = native_store_tr())
c1773a16	94	#define store_ldt(ldt) asm("sldt %0":"=m" (ldt))
54cd0eac GOC	95
	96	#define load_TLS(t, cpu) native_load_tls(t, cpu)
	97	#define set_ldt native_set_ldt
	98
c1773a16 JP	99	#define write_ldt_entry(dt, entry, desc) \
	100	native_write_ldt_entry(dt, entry, desc)
	101	#define write_gdt_entry(dt, entry, desc, type) \
	102	native_write_gdt_entry(dt, entry, desc, type)
	103	#define write_idt_entry(dt, entry, g) \
	104	native_write_idt_entry(dt, entry, g)
38ffbe66 JF	105
	106	static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries)
	107	{
	108	}
	109
	110	static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries)
	111	{
	112	}
	113	#endif /* CONFIG_PARAVIRT */
54cd0eac GOC	114
	115	static inline void native_write_idt_entry(gate_desc *idt, int entry,
	116	const gate_desc *gate)
	117	{
	118	memcpy(&idt[entry], gate, sizeof(*gate));
	119	}
	120
	121	static inline void native_write_ldt_entry(struct desc_struct *ldt, int entry,
	122	const void *desc)
	123	{
	124	memcpy(&ldt[entry], desc, 8);
	125	}
	126
	127	static inline void native_write_gdt_entry(struct desc_struct *gdt, int entry,
	128	const void *desc, int type)
	129	{
	130	unsigned int size;
	131	switch (type) {
	132	case DESC_TSS:
	133	size = sizeof(tss_desc);
	134	break;
	135	case DESC_LDT:
	136	size = sizeof(ldt_desc);
	137	break;
	138	default:
	139	size = sizeof(struct desc_struct);
	140	break;
	141	}
	142	memcpy(&gdt[entry], desc, size);
	143	}
	144
54cd0eac GOC	145	static inline void pack_descriptor(struct desc_struct *desc, unsigned long base,
	146	unsigned long limit, unsigned char type,
	147	unsigned char flags)
	148	{
	149	desc->a = ((base & 0xffff) << 16) \| (limit & 0xffff);
	150	desc->b = (base & 0xff000000) \| ((base & 0xff0000) >> 16) \|
c1773a16 JP	151	(limit & 0x000f0000) \| ((type & 0xff) << 8) \|
c1773a16 JP	152	((flags & 0xf) << 20);
54cd0eac GOC	153	desc->p = 1;
	154	}
	155
54cd0eac	156
f6e0eba1 GOC	157	static inline void set_tssldt_descriptor(void *d, unsigned long addr,
f6e0eba1 GOC	158	unsigned type, unsigned size)
c81c6ca4 GOC	159	{
c81c6ca4 GOC	160	#ifdef CONFIG_X86_64
f6e0eba1 GOC	161	struct ldttss_desc64 *desc = d;
	162	memset(desc, 0, sizeof(*desc));
	163	desc->limit0 = size & 0xFFFF;
	164	desc->base0 = PTR_LOW(addr);
	165	desc->base1 = PTR_MIDDLE(addr) & 0xFF;
	166	desc->type = type;
	167	desc->p = 1;
	168	desc->limit1 = (size >> 16) & 0xF;
	169	desc->base2 = (PTR_MIDDLE(addr) >> 8) & 0xFF;
	170	desc->base3 = PTR_HIGH(addr);
c81c6ca4	171	#else
f6e0eba1	172	pack_descriptor((struct desc_struct *)d, addr, size, 0x80 \| type, 0);
c81c6ca4 GOC	173	#endif
	174	}
	175
	176	static inline void __set_tss_desc(unsigned cpu, unsigned int entry, void *addr)
	177	{
	178	struct desc_struct *d = get_cpu_gdt_table(cpu);
	179	tss_desc tss;
	180
	181	/*
	182	* sizeof(unsigned long) coming from an extra "long" at the end
	183	* of the iobitmap. See tss_struct definition in processor.h
	184	*
	185	* -1? seg base+limit should be pointing to the address of the
	186	* last valid byte
	187	*/
f6e0eba1	188	set_tssldt_descriptor(&tss, (unsigned long)addr, DESC_TSS,
c1773a16 JP	189	IO_BITMAP_OFFSET + IO_BITMAP_BYTES +
c1773a16 JP	190	sizeof(unsigned long) - 1);
c81c6ca4 GOC	191	write_gdt_entry(d, entry, &tss, DESC_TSS);
	192	}
	193
	194	#define set_tss_desc(cpu, addr) __set_tss_desc(cpu, GDT_ENTRY_TSS, addr)
	195
54cd0eac GOC	196	static inline void native_set_ldt(const void *addr, unsigned int entries)
	197	{
	198	if (likely(entries == 0))
c1773a16	199	asm volatile("lldt %w0"::"q" (0));
54cd0eac GOC	200	else {
	201	unsigned cpu = smp_processor_id();
	202	ldt_desc ldt;
	203
5ac37f87 MK	204	set_tssldt_descriptor(&ldt, (unsigned long)addr, DESC_LDT,
5ac37f87 MK	205	entries * LDT_ENTRY_SIZE - 1);
54cd0eac GOC	206	write_gdt_entry(get_cpu_gdt_table(cpu), GDT_ENTRY_LDT,
54cd0eac GOC	207	&ldt, DESC_LDT);
c1773a16	208	asm volatile("lldt %w0"::"q" (GDT_ENTRY_LDT*8));
54cd0eac GOC	209	}
	210	}
	211
	212	static inline void native_load_tr_desc(void)
	213	{
	214	asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8));
	215	}
	216
	217	static inline void native_load_gdt(const struct desc_ptr *dtr)
	218	{
	219	asm volatile("lgdt %0"::"m" (*dtr));
	220	}
	221
	222	static inline void native_load_idt(const struct desc_ptr *dtr)
	223	{
	224	asm volatile("lidt %0"::"m" (*dtr));
	225	}
	226
	227	static inline void native_store_gdt(struct desc_ptr *dtr)
	228	{
	229	asm volatile("sgdt %0":"=m" (*dtr));
	230	}
	231
	232	static inline void native_store_idt(struct desc_ptr *dtr)
	233	{
	234	asm volatile("sidt %0":"=m" (*dtr));
	235	}
	236
	237	static inline unsigned long native_store_tr(void)
	238	{
	239	unsigned long tr;
	240	asm volatile("str %0":"=r" (tr));
	241	return tr;
	242	}
	243
	244	static inline void native_load_tls(struct thread_struct *t, unsigned int cpu)
	245	{
	246	unsigned int i;
	247	struct desc_struct *gdt = get_cpu_gdt_table(cpu);
	248
	249	for (i = 0; i < GDT_ENTRY_TLS_ENTRIES; i++)
	250	gdt[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i];
	251	}
	252
c1773a16 JP	253	#define _LDT_empty(info) \
	254	((info)->base_addr == 0 && \
	255	(info)->limit == 0 && \
	256	(info)->contents == 0 && \
	257	(info)->read_exec_only == 1 && \
	258	(info)->seg_32bit == 0 && \
	259	(info)->limit_in_pages == 0 && \
	260	(info)->seg_not_present == 1 && \
	261	(info)->useable == 0)
881c2975 GOC	262
	263	#ifdef CONFIG_X86_64
	264	#define LDT_empty(info) (_LDT_empty(info) && ((info)->lm == 0))
	265	#else
	266	#define LDT_empty(info) (_LDT_empty(info))
	267	#endif
	268
	269	static inline void clear_LDT(void)
	270	{
	271	set_ldt(NULL, 0);
	272	}
	273
	274	/*
	275	* load one particular LDT into the current CPU
	276	*/
	277	static inline void load_LDT_nolock(mm_context_t *pc)
	278	{
	279	set_ldt(pc->ldt, pc->size);
	280	}
	281
	282	static inline void load_LDT(mm_context_t *pc)
	283	{
	284	preempt_disable();
	285	load_LDT_nolock(pc);
	286	preempt_enable();
	287	}
	288
1bd5718c	289	static inline unsigned long get_desc_base(const struct desc_struct *desc)
cc697852 GOC	290	{
	291	return desc->base0 \| ((desc->base1) << 16) \| ((desc->base2) << 24);
	292	}
1bd5718c RM	293
	294	static inline unsigned long get_desc_limit(const struct desc_struct *desc)
	295	{
	296	return desc->limit0 \| (desc->limit << 16);
	297	}
	298
507f90c9	299	static inline void _set_gate(int gate, unsigned type, void *addr,
c1773a16	300	unsigned dpl, unsigned ist, unsigned seg)
507f90c9 GOC	301	{
	302	gate_desc s;
	303	pack_gate(&s, type, (unsigned long)addr, dpl, ist, seg);
	304	/*
	305	* does not need to be atomic because it is only done once at
	306	* setup time
	307	*/
	308	write_idt_entry(idt_table, gate, &s);
	309	}
	310
	311	/*
	312	* This needs to use 'idt_table' rather than 'idt', and
	313	* thus use the _nonmapped_ version of the IDT, as the
	314	* Pentium F0 0F bugfix can have resulted in the mapped
	315	* IDT being write-protected.
	316	*/
	317	static inline void set_intr_gate(unsigned int n, void *addr)
	318	{
	319	BUG_ON((unsigned)n > 0xFF);
	320	_set_gate(n, GATE_INTERRUPT, addr, 0, 0, __KERNEL_CS);
	321	}
	322
305b92a2 AM	323	#define SYS_VECTOR_FREE 0
	324	#define SYS_VECTOR_ALLOCED 1
	325
	326	extern int first_system_vector;
	327	extern char system_vectors[];
	328
	329	static inline void alloc_system_vector(int vector)
	330	{
	331	if (system_vectors[vector] == SYS_VECTOR_FREE) {
	332	system_vectors[vector] = SYS_VECTOR_ALLOCED;
	333	if (first_system_vector > vector)
	334	first_system_vector = vector;
	335	} else
	336	BUG();
	337	}
	338
	339	static inline void alloc_intr_gate(unsigned int n, void *addr)
	340	{
	341	alloc_system_vector(n);
	342	set_intr_gate(n, addr);
	343	}
	344
507f90c9 GOC	345	/*
	346	* This routine sets up an interrupt gate at directory privilege level 3.
	347	*/
	348	static inline void set_system_intr_gate(unsigned int n, void *addr)
	349	{
	350	BUG_ON((unsigned)n > 0xFF);
	351	_set_gate(n, GATE_INTERRUPT, addr, 0x3, 0, __KERNEL_CS);
	352	}
	353
699d2937	354	static inline void set_system_trap_gate(unsigned int n, void *addr)
507f90c9 GOC	355	{
507f90c9 GOC	356	BUG_ON((unsigned)n > 0xFF);
699d2937	357	_set_gate(n, GATE_TRAP, addr, 0x3, 0, __KERNEL_CS);
507f90c9 GOC	358	}
507f90c9 GOC	359
699d2937	360	static inline void set_trap_gate(unsigned int n, void *addr)
507f90c9 GOC	361	{
507f90c9 GOC	362	BUG_ON((unsigned)n > 0xFF);
699d2937	363	_set_gate(n, GATE_TRAP, addr, 0, 0, __KERNEL_CS);
507f90c9 GOC	364	}
	365
	366	static inline void set_task_gate(unsigned int n, unsigned int gdt_entry)
	367	{
	368	BUG_ON((unsigned)n > 0xFF);
	369	_set_gate(n, GATE_TASK, (void *)0, 0, 0, (gdt_entry<<3));
	370	}
	371
	372	static inline void set_intr_gate_ist(int n, void *addr, unsigned ist)
	373	{
	374	BUG_ON((unsigned)n > 0xFF);
	375	_set_gate(n, GATE_INTERRUPT, addr, 0, ist, __KERNEL_CS);
	376	}
	377
699d2937	378	static inline void set_system_intr_gate_ist(int n, void *addr, unsigned ist)
507f90c9 GOC	379	{
	380	BUG_ON((unsigned)n > 0xFF);
	381	_set_gate(n, GATE_INTERRUPT, addr, 0x3, ist, __KERNEL_CS);
	382	}
cc697852	383
881c2975 GOC	384	#else
	385	/*
	386	* GET_DESC_BASE reads the descriptor base of the specified segment.
	387	*
	388	* Args:
	389	* idx - descriptor index
	390	* gdt - GDT pointer
	391	* base - 32bit register to which the base will be written
	392	* lo_w - lo word of the "base" register
	393	* lo_b - lo byte of the "base" register
	394	* hi_b - hi byte of the low word of the "base" register
	395	*
	396	* Example:
	397	* GET_DESC_BASE(GDT_ENTRY_ESPFIX_SS, %ebx, %eax, %ax, %al, %ah)
	398	* Will read the base address of GDT_ENTRY_ESPFIX_SS and put it into %eax.
	399	*/
	400	#define GET_DESC_BASE(idx, gdt, base, lo_w, lo_b, hi_b) \
c1773a16 JP	401	movb idx * 8 + 4(gdt), lo_b; \
	402	movb idx * 8 + 7(gdt), hi_b; \
	403	shll $16, base; \
	404	movw idx * 8 + 2(gdt), lo_w;
881c2975 GOC	405
	406
	407	#endif /* __ASSEMBLY__ */
	408
1965aae3	409	#endif /* _ASM_X86_DESC_H */