[deliverable/linux.git] / arch / x86 / include / asm / dma-mapping.h

#ifndef _ASM_X86_DMA_MAPPING_H
#define _ASM_X86_DMA_MAPPING_H

/*
 * IOMMU interface. See Documentation/PCI/PCI-DMA-mapping.txt and
 * Documentation/DMA-API.txt for documentation.
 */

#include <linux/kmemcheck.h>
#include <linux/scatterlist.h>
#include <linux/dma-debug.h>
#include <linux/dma-attrs.h>
#include <asm/io.h>
#include <asm/swiotlb.h>
#include <asm-generic/dma-coherent.h>

#ifdef CONFIG_ISA
# define ISA_DMA_BIT_MASK DMA_BIT_MASK(24)
#else
# define ISA_DMA_BIT_MASK DMA_BIT_MASK(32)
#endif

#define DMA_ERROR_CODE	0

extern int iommu_merge;
extern struct device x86_dma_fallback_dev;
extern int panic_on_overflow;

extern struct dma_map_ops *dma_ops;

static inline struct dma_map_ops *get_dma_ops(struct device *dev)
{
#ifdef CONFIG_X86_32
	return dma_ops;
#else
	if (unlikely(!dev) || !dev->archdata.dma_ops)
		return dma_ops;
	else
		return dev->archdata.dma_ops;
#endif
}

#include <asm-generic/dma-mapping-common.h>

/* Make sure we keep the same behaviour */
static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
{
	struct dma_map_ops *ops = get_dma_ops(dev);
	if (ops->mapping_error)
		return ops->mapping_error(dev, dma_addr);

	return (dma_addr == DMA_ERROR_CODE);
}

#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
#define dma_is_consistent(d, h)	(1)

extern int dma_supported(struct device *hwdev, u64 mask);
extern int dma_set_mask(struct device *dev, u64 mask);

extern void *dma_generic_alloc_coherent(struct device *dev, size_t size,
					dma_addr_t *dma_addr, gfp_t flag);

static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
{
	if (!dev->dma_mask)
		return 0;

	return addr + size - 1 <= *dev->dma_mask;
}

static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
{
	return paddr;
}

static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
{
	return daddr;
}

static inline void
dma_cache_sync(struct device *dev, void *vaddr, size_t size,
	enum dma_data_direction dir)
{
	flush_write_buffers();
}

static inline int dma_get_cache_alignment(void)
{
	/* no easy way to get cache size on all x86, so return the
	 * maximum possible, to be safe */
	return boot_cpu_data.x86_clflush_size;
}

static inline unsigned long dma_alloc_coherent_mask(struct device *dev,
						    gfp_t gfp)
{
	unsigned long dma_mask = 0;

	dma_mask = dev->coherent_dma_mask;
	if (!dma_mask)
		dma_mask = (gfp & GFP_DMA) ? DMA_BIT_MASK(24) : DMA_BIT_MASK(32);

	return dma_mask;
}

static inline gfp_t dma_alloc_coherent_gfp_flags(struct device *dev, gfp_t gfp)
{
	unsigned long dma_mask = dma_alloc_coherent_mask(dev, gfp);

	if (dma_mask <= DMA_BIT_MASK(24))
		gfp |= GFP_DMA;
#ifdef CONFIG_X86_64
	if (dma_mask <= DMA_BIT_MASK(32) && !(gfp & GFP_DMA))
		gfp |= GFP_DMA32;
#endif
       return gfp;
}

static inline void *
dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
		gfp_t gfp)
{
	struct dma_map_ops *ops = get_dma_ops(dev);
	void *memory;

	gfp &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);

	if (dma_alloc_from_coherent(dev, size, dma_handle, &memory))
		return memory;

	if (!dev)
		dev = &x86_dma_fallback_dev;

	if (!is_device_dma_capable(dev))
		return NULL;

	if (!ops->alloc_coherent)
		return NULL;

	memory = ops->alloc_coherent(dev, size, dma_handle,
				     dma_alloc_coherent_gfp_flags(dev, gfp));
	debug_dma_alloc_coherent(dev, size, *dma_handle, memory);

	return memory;
}

static inline void dma_free_coherent(struct device *dev, size_t size,
				     void *vaddr, dma_addr_t bus)
{
	struct dma_map_ops *ops = get_dma_ops(dev);

	WARN_ON(irqs_disabled());       /* for portability */

	if (dma_release_from_coherent(dev, get_order(size), vaddr))
		return;

	debug_dma_free_coherent(dev, size, vaddr, bus);
	if (ops->free_coherent)
		ops->free_coherent(dev, size, vaddr, bus);
}

#endif
Commit	Line	Data
1965aae3 PA	1	#ifndef _ASM_X86_DMA_MAPPING_H
1965aae3 PA	2	#define _ASM_X86_DMA_MAPPING_H
6f536635 GC	3
6f536635 GC	4	/*
5872fb94 RD	5	* IOMMU interface. See Documentation/PCI/PCI-DMA-mapping.txt and
5872fb94 RD	6	* Documentation/DMA-API.txt for documentation.
6f536635 GC	7	*/
6f536635 GC	8
d7002857	9	#include <linux/kmemcheck.h>
6f536635	10	#include <linux/scatterlist.h>
2118d0c5	11	#include <linux/dma-debug.h>
abe6602b	12	#include <linux/dma-attrs.h>
6f536635 GC	13	#include <asm/io.h>
6f536635 GC	14	#include <asm/swiotlb.h>
6c505ce3	15	#include <asm-generic/dma-coherent.h>
6f536635	16
eb647138 JB	17	#ifdef CONFIG_ISA
	18	# define ISA_DMA_BIT_MASK DMA_BIT_MASK(24)
	19	#else
	20	# define ISA_DMA_BIT_MASK DMA_BIT_MASK(32)
	21	#endif
	22
8fd524b3 FT	23	#define DMA_ERROR_CODE 0
8fd524b3 FT	24
b7107a3d	25	extern int iommu_merge;
6c505ce3	26	extern struct device x86_dma_fallback_dev;
b7107a3d	27	extern int panic_on_overflow;
7c183416	28
160c1d8e FT	29	extern struct dma_map_ops *dma_ops;
	30
	31	static inline struct dma_map_ops get_dma_ops(struct device dev)
c786df08	32	{
8d8bb39b FT	33	#ifdef CONFIG_X86_32
	34	return dma_ops;
	35	#else
	36	if (unlikely(!dev) \|\| !dev->archdata.dma_ops)
	37	return dma_ops;
	38	else
	39	return dev->archdata.dma_ops;
cfb80c9e	40	#endif
8d8bb39b FT	41	}
8d8bb39b FT	42
7c095e46 FT	43	#include <asm-generic/dma-mapping-common.h>
7c095e46 FT	44
8d8bb39b FT	45	/* Make sure we keep the same behaviour */
	46	static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
	47	{
160c1d8e	48	struct dma_map_ops *ops = get_dma_ops(dev);
8d8bb39b FT	49	if (ops->mapping_error)
8d8bb39b FT	50	return ops->mapping_error(dev, dma_addr);
c786df08	51
8fd524b3	52	return (dma_addr == DMA_ERROR_CODE);
c786df08 GC	53	}
c786df08 GC	54
8d396ded GC	55	#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
8d396ded GC	56	#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
6c505ce3	57	#define dma_is_consistent(d, h) (1)
8d396ded	58
802c1f66 GC	59	extern int dma_supported(struct device *hwdev, u64 mask);
	60	extern int dma_set_mask(struct device *dev, u64 mask);
	61
9f6ac577 FT	62	extern void dma_generic_alloc_coherent(struct device dev, size_t size,
	63	dma_addr_t *dma_addr, gfp_t flag);
	64
99becaca FT	65	static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
	66	{
	67	if (!dev->dma_mask)
	68	return 0;
	69
ac2b3e67	70	return addr + size - 1 <= *dev->dma_mask;
99becaca FT	71	}
99becaca FT	72
8d4f5339 FT	73	static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
	74	{
	75	return paddr;
	76	}
	77
	78	static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
	79	{
	80	return daddr;
	81	}
	82
3cb6a917 GC	83	static inline void
	84	dma_cache_sync(struct device dev, void vaddr, size_t size,
	85	enum dma_data_direction dir)
	86	{
	87	flush_write_buffers();
	88	}
ae17a63b	89
b7107a3d GC	90	static inline int dma_get_cache_alignment(void)
	91	{
	92	/* no easy way to get cache size on all x86, so return the
	93	* maximum possible, to be safe */
	94	return boot_cpu_data.x86_clflush_size;
	95	}
	96
823e7e8c FT	97	static inline unsigned long dma_alloc_coherent_mask(struct device *dev,
	98	gfp_t gfp)
	99	{
	100	unsigned long dma_mask = 0;
b7107a3d	101
823e7e8c FT	102	dma_mask = dev->coherent_dma_mask;
823e7e8c FT	103	if (!dma_mask)
2f4f27d4	104	dma_mask = (gfp & GFP_DMA) ? DMA_BIT_MASK(24) : DMA_BIT_MASK(32);
823e7e8c FT	105
	106	return dma_mask;
	107	}
	108
	109	static inline gfp_t dma_alloc_coherent_gfp_flags(struct device *dev, gfp_t gfp)
	110	{
	111	unsigned long dma_mask = dma_alloc_coherent_mask(dev, gfp);
	112
2f4f27d4	113	if (dma_mask <= DMA_BIT_MASK(24))
75bebb7f FT	114	gfp \|= GFP_DMA;
75bebb7f FT	115	#ifdef CONFIG_X86_64
284901a9	116	if (dma_mask <= DMA_BIT_MASK(32) && !(gfp & GFP_DMA))
823e7e8c FT	117	gfp \|= GFP_DMA32;
	118	#endif
	119	return gfp;
	120	}
	121
6c505ce3 JR	122	static inline void *
	123	dma_alloc_coherent(struct device dev, size_t size, dma_addr_t dma_handle,
	124	gfp_t gfp)
	125	{
160c1d8e	126	struct dma_map_ops *ops = get_dma_ops(dev);
6c505ce3 JR	127	void *memory;
6c505ce3 JR	128
8a53ad67 FT	129	gfp &= ~(__GFP_DMA \| __GFP_HIGHMEM \| __GFP_DMA32);
8a53ad67 FT	130
6c505ce3 JR	131	if (dma_alloc_from_coherent(dev, size, dma_handle, &memory))
	132	return memory;
	133
eb647138	134	if (!dev)
6c505ce3	135	dev = &x86_dma_fallback_dev;
6c505ce3	136
98216260	137	if (!is_device_dma_capable(dev))
de9f521f FT	138	return NULL;
de9f521f FT	139
823e7e8c FT	140	if (!ops->alloc_coherent)
	141	return NULL;
	142
2118d0c5 JR	143	memory = ops->alloc_coherent(dev, size, dma_handle,
	144	dma_alloc_coherent_gfp_flags(dev, gfp));
	145	debug_dma_alloc_coherent(dev, size, *dma_handle, memory);
	146
	147	return memory;
6c505ce3 JR	148	}
	149
	150	static inline void dma_free_coherent(struct device *dev, size_t size,
	151	void *vaddr, dma_addr_t bus)
	152	{
160c1d8e	153	struct dma_map_ops *ops = get_dma_ops(dev);
6c505ce3 JR	154
	155	WARN_ON(irqs_disabled()); /* for portability */
	156
	157	if (dma_release_from_coherent(dev, get_order(size), vaddr))
	158	return;
	159
2118d0c5	160	debug_dma_free_coherent(dev, size, vaddr, bus);
6c505ce3 JR	161	if (ops->free_coherent)
	162	ops->free_coherent(dev, size, vaddr, bus);
	163	}
b7107a3d	164
6f536635	165	#endif