Commit | Line | Data |
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1361b83a LT |
1 | /* |
2 | * Copyright (C) 1994 Linus Torvalds | |
3 | * | |
4 | * Pentium III FXSR, SSE support | |
5 | * General FPU state handling cleanups | |
6 | * Gareth Hughes <gareth@valinux.com>, May 2000 | |
7 | * x86-64 work by Andi Kleen 2002 | |
8 | */ | |
9 | ||
78f7f1e5 IM |
10 | #ifndef _ASM_X86_FPU_INTERNAL_H |
11 | #define _ASM_X86_FPU_INTERNAL_H | |
1361b83a | 12 | |
050902c0 | 13 | #include <linux/compat.h> |
952f07ec | 14 | #include <linux/sched.h> |
1361b83a | 15 | #include <linux/slab.h> |
f89e32e0 | 16 | |
1361b83a | 17 | #include <asm/user.h> |
df6b35f4 | 18 | #include <asm/fpu/api.h> |
669ebabb | 19 | #include <asm/fpu/xstate.h> |
1361b83a | 20 | |
6ffc152e IM |
21 | /* |
22 | * High level FPU state handling functions: | |
23 | */ | |
0c306bcf IM |
24 | extern void fpu__activate_curr(struct fpu *fpu); |
25 | extern void fpu__activate_stopped(struct fpu *fpu); | |
6ffc152e | 26 | extern void fpu__save(struct fpu *fpu); |
e1884d69 | 27 | extern void fpu__restore(struct fpu *fpu); |
82c0e45e | 28 | extern int fpu__restore_sig(void __user *buf, int ia32_frame); |
6ffc152e IM |
29 | extern void fpu__drop(struct fpu *fpu); |
30 | extern int fpu__copy(struct fpu *dst_fpu, struct fpu *src_fpu); | |
04c8e01d | 31 | extern void fpu__clear(struct fpu *fpu); |
b1b64dc3 IM |
32 | extern int fpu__exception_code(struct fpu *fpu, int trap_nr); |
33 | extern int dump_fpu(struct pt_regs *ptregs, struct user_i387_struct *fpstate); | |
6ffc152e | 34 | |
b1b64dc3 IM |
35 | /* |
36 | * Boot time FPU initialization functions: | |
37 | */ | |
38 | extern void fpu__init_cpu(void); | |
39 | extern void fpu__init_system_xstate(void); | |
40 | extern void fpu__init_cpu_xstate(void); | |
41 | extern void fpu__init_system(struct cpuinfo_x86 *c); | |
952f07ec IM |
42 | extern void fpu__init_check_bugs(void); |
43 | extern void fpu__resume_cpu(void); | |
44 | ||
e97131a8 IM |
45 | /* |
46 | * Debugging facility: | |
47 | */ | |
48 | #ifdef CONFIG_X86_DEBUG_FPU | |
49 | # define WARN_ON_FPU(x) WARN_ON_ONCE(x) | |
50 | #else | |
51 | # define WARN_ON_FPU(x) ({ 0; }) | |
52 | #endif | |
53 | ||
1c927eea | 54 | /* |
b1b64dc3 | 55 | * FPU related CPU feature flag helper routines: |
1c927eea | 56 | */ |
5d2bd700 SS |
57 | static __always_inline __pure bool use_eager_fpu(void) |
58 | { | |
c6b40691 | 59 | return static_cpu_has_safe(X86_FEATURE_EAGER_FPU); |
5d2bd700 SS |
60 | } |
61 | ||
1361b83a LT |
62 | static __always_inline __pure bool use_xsaveopt(void) |
63 | { | |
c6b40691 | 64 | return static_cpu_has_safe(X86_FEATURE_XSAVEOPT); |
1361b83a LT |
65 | } |
66 | ||
67 | static __always_inline __pure bool use_xsave(void) | |
68 | { | |
c6b40691 | 69 | return static_cpu_has_safe(X86_FEATURE_XSAVE); |
1361b83a LT |
70 | } |
71 | ||
72 | static __always_inline __pure bool use_fxsr(void) | |
73 | { | |
c6b40691 | 74 | return static_cpu_has_safe(X86_FEATURE_FXSR); |
1361b83a LT |
75 | } |
76 | ||
b1b64dc3 IM |
77 | /* |
78 | * fpstate handling functions: | |
79 | */ | |
80 | ||
81 | extern union fpregs_state init_fpstate; | |
82 | ||
83 | extern void fpstate_init(union fpregs_state *state); | |
84 | #ifdef CONFIG_MATH_EMULATION | |
85 | extern void fpstate_init_soft(struct swregs_state *soft); | |
86 | #else | |
87 | static inline void fpstate_init_soft(struct swregs_state *soft) {} | |
88 | #endif | |
89 | static inline void fpstate_init_fxstate(struct fxregs_state *fx) | |
90 | { | |
91 | fx->cwd = 0x37f; | |
92 | fx->mxcsr = MXCSR_DEFAULT; | |
93 | } | |
36e49e7f | 94 | extern void fpstate_sanitize_xstate(struct fpu *fpu); |
1361b83a | 95 | |
49b8c695 PA |
96 | #define user_insn(insn, output, input...) \ |
97 | ({ \ | |
98 | int err; \ | |
99 | asm volatile(ASM_STAC "\n" \ | |
100 | "1:" #insn "\n\t" \ | |
101 | "2: " ASM_CLAC "\n" \ | |
102 | ".section .fixup,\"ax\"\n" \ | |
103 | "3: movl $-1,%[err]\n" \ | |
104 | " jmp 2b\n" \ | |
105 | ".previous\n" \ | |
106 | _ASM_EXTABLE(1b, 3b) \ | |
107 | : [err] "=r" (err), output \ | |
108 | : "0"(0), input); \ | |
109 | err; \ | |
110 | }) | |
111 | ||
0ca5bd0d SS |
112 | #define check_insn(insn, output, input...) \ |
113 | ({ \ | |
114 | int err; \ | |
115 | asm volatile("1:" #insn "\n\t" \ | |
116 | "2:\n" \ | |
117 | ".section .fixup,\"ax\"\n" \ | |
118 | "3: movl $-1,%[err]\n" \ | |
119 | " jmp 2b\n" \ | |
120 | ".previous\n" \ | |
121 | _ASM_EXTABLE(1b, 3b) \ | |
122 | : [err] "=r" (err), output \ | |
123 | : "0"(0), input); \ | |
124 | err; \ | |
125 | }) | |
126 | ||
c47ada30 | 127 | static inline int copy_fregs_to_user(struct fregs_state __user *fx) |
1361b83a | 128 | { |
49b8c695 | 129 | return user_insn(fnsave %[fx]; fwait, [fx] "=m" (*fx), "m" (*fx)); |
1361b83a LT |
130 | } |
131 | ||
c47ada30 | 132 | static inline int copy_fxregs_to_user(struct fxregs_state __user *fx) |
1361b83a | 133 | { |
0ca5bd0d | 134 | if (config_enabled(CONFIG_X86_32)) |
49b8c695 | 135 | return user_insn(fxsave %[fx], [fx] "=m" (*fx), "m" (*fx)); |
0ca5bd0d | 136 | else if (config_enabled(CONFIG_AS_FXSAVEQ)) |
49b8c695 | 137 | return user_insn(fxsaveq %[fx], [fx] "=m" (*fx), "m" (*fx)); |
1361b83a | 138 | |
c6813144 | 139 | /* See comment in copy_fxregs_to_kernel() below. */ |
49b8c695 | 140 | return user_insn(rex64/fxsave (%[fx]), "=m" (*fx), [fx] "R" (fx)); |
1361b83a LT |
141 | } |
142 | ||
c47ada30 | 143 | static inline int copy_kernel_to_fxregs(struct fxregs_state *fx) |
1361b83a | 144 | { |
0ca5bd0d SS |
145 | if (config_enabled(CONFIG_X86_32)) |
146 | return check_insn(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx)); | |
147 | else if (config_enabled(CONFIG_AS_FXSAVEQ)) | |
148 | return check_insn(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx)); | |
1361b83a | 149 | |
c6813144 | 150 | /* See comment in copy_fxregs_to_kernel() below. */ |
0ca5bd0d SS |
151 | return check_insn(rex64/fxrstor (%[fx]), "=m" (*fx), [fx] "R" (fx), |
152 | "m" (*fx)); | |
1361b83a LT |
153 | } |
154 | ||
c47ada30 | 155 | static inline int copy_user_to_fxregs(struct fxregs_state __user *fx) |
e139e955 PA |
156 | { |
157 | if (config_enabled(CONFIG_X86_32)) | |
158 | return user_insn(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx)); | |
159 | else if (config_enabled(CONFIG_AS_FXSAVEQ)) | |
160 | return user_insn(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx)); | |
161 | ||
c6813144 | 162 | /* See comment in copy_fxregs_to_kernel() below. */ |
e139e955 PA |
163 | return user_insn(rex64/fxrstor (%[fx]), "=m" (*fx), [fx] "R" (fx), |
164 | "m" (*fx)); | |
165 | } | |
166 | ||
c47ada30 | 167 | static inline int copy_kernel_to_fregs(struct fregs_state *fx) |
1361b83a | 168 | { |
0ca5bd0d | 169 | return check_insn(frstor %[fx], "=m" (*fx), [fx] "m" (*fx)); |
e139e955 PA |
170 | } |
171 | ||
c47ada30 | 172 | static inline int copy_user_to_fregs(struct fregs_state __user *fx) |
e139e955 PA |
173 | { |
174 | return user_insn(frstor %[fx], "=m" (*fx), [fx] "m" (*fx)); | |
1361b83a LT |
175 | } |
176 | ||
c6813144 | 177 | static inline void copy_fxregs_to_kernel(struct fpu *fpu) |
1361b83a | 178 | { |
0ca5bd0d | 179 | if (config_enabled(CONFIG_X86_32)) |
7366ed77 | 180 | asm volatile( "fxsave %[fx]" : [fx] "=m" (fpu->state.fxsave)); |
0ca5bd0d | 181 | else if (config_enabled(CONFIG_AS_FXSAVEQ)) |
7366ed77 | 182 | asm volatile("fxsaveq %[fx]" : [fx] "=m" (fpu->state.fxsave)); |
0ca5bd0d SS |
183 | else { |
184 | /* Using "rex64; fxsave %0" is broken because, if the memory | |
185 | * operand uses any extended registers for addressing, a second | |
186 | * REX prefix will be generated (to the assembler, rex64 | |
187 | * followed by semicolon is a separate instruction), and hence | |
188 | * the 64-bitness is lost. | |
189 | * | |
190 | * Using "fxsaveq %0" would be the ideal choice, but is only | |
191 | * supported starting with gas 2.16. | |
192 | * | |
193 | * Using, as a workaround, the properly prefixed form below | |
194 | * isn't accepted by any binutils version so far released, | |
195 | * complaining that the same type of prefix is used twice if | |
196 | * an extended register is needed for addressing (fix submitted | |
197 | * to mainline 2005-11-21). | |
198 | * | |
7366ed77 | 199 | * asm volatile("rex64/fxsave %0" : "=m" (fpu->state.fxsave)); |
0ca5bd0d SS |
200 | * |
201 | * This, however, we can work around by forcing the compiler to | |
202 | * select an addressing mode that doesn't require extended | |
203 | * registers. | |
204 | */ | |
205 | asm volatile( "rex64/fxsave (%[fx])" | |
7366ed77 IM |
206 | : "=m" (fpu->state.fxsave) |
207 | : [fx] "R" (&fpu->state.fxsave)); | |
0ca5bd0d | 208 | } |
1361b83a LT |
209 | } |
210 | ||
1361b83a LT |
211 | /* |
212 | * These must be called with preempt disabled. Returns | |
4f836347 IM |
213 | * 'true' if the FPU state is still intact and we can |
214 | * keep registers active. | |
215 | * | |
216 | * The legacy FNSAVE instruction cleared all FPU state | |
217 | * unconditionally, so registers are essentially destroyed. | |
218 | * Modern FPU state can be kept in registers, if there are | |
1bc6b056 | 219 | * no pending FP exceptions. |
1361b83a | 220 | */ |
4f836347 | 221 | static inline int copy_fpregs_to_fpstate(struct fpu *fpu) |
1361b83a | 222 | { |
1bc6b056 | 223 | if (likely(use_xsave())) { |
c6813144 | 224 | copy_xregs_to_kernel(&fpu->state.xsave); |
1bc6b056 IM |
225 | return 1; |
226 | } | |
1361b83a | 227 | |
1bc6b056 | 228 | if (likely(use_fxsr())) { |
c6813144 | 229 | copy_fxregs_to_kernel(fpu); |
1bc6b056 | 230 | return 1; |
1361b83a LT |
231 | } |
232 | ||
233 | /* | |
1bc6b056 IM |
234 | * Legacy FPU register saving, FNSAVE always clears FPU registers, |
235 | * so we have to mark them inactive: | |
1361b83a | 236 | */ |
7366ed77 | 237 | asm volatile("fnsave %[fx]; fwait" : [fx] "=m" (fpu->state.fsave)); |
4f836347 | 238 | |
4f836347 | 239 | return 0; |
1361b83a LT |
240 | } |
241 | ||
0e75c54f | 242 | static inline int __copy_fpstate_to_fpregs(struct fpu *fpu) |
1361b83a LT |
243 | { |
244 | if (use_xsave()) | |
c6813144 | 245 | return copy_kernel_to_xregs(&fpu->state.xsave, -1); |
0ca5bd0d | 246 | else if (use_fxsr()) |
c6813144 | 247 | return copy_kernel_to_fxregs(&fpu->state.fxsave); |
1361b83a | 248 | else |
c6813144 | 249 | return copy_kernel_to_fregs(&fpu->state.fsave); |
1361b83a LT |
250 | } |
251 | ||
0e75c54f | 252 | static inline int copy_fpstate_to_fpregs(struct fpu *fpu) |
1361b83a | 253 | { |
6ca7a8a1 BP |
254 | /* |
255 | * AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception is | |
256 | * pending. Clear the x87 state here by setting it to fixed values. | |
257 | * "m" is a random variable that should be in L1. | |
258 | */ | |
9b13a93d | 259 | if (unlikely(static_cpu_has_bug_safe(X86_BUG_FXSAVE_LEAK))) { |
26bef131 LT |
260 | asm volatile( |
261 | "fnclex\n\t" | |
262 | "emms\n\t" | |
263 | "fildl %P[addr]" /* set F?P to defined value */ | |
d5cea9b0 | 264 | : : [addr] "m" (fpu->fpregs_active)); |
26bef131 | 265 | } |
1361b83a | 266 | |
0e75c54f | 267 | return __copy_fpstate_to_fpregs(fpu); |
1361b83a LT |
268 | } |
269 | ||
b1b64dc3 IM |
270 | extern int copy_fpstate_to_sigframe(void __user *buf, void __user *fx, int size); |
271 | ||
272 | /* | |
273 | * FPU context switch related helper methods: | |
274 | */ | |
275 | ||
276 | DECLARE_PER_CPU(struct fpu *, fpu_fpregs_owner_ctx); | |
277 | ||
278 | /* | |
279 | * Must be run with preemption disabled: this clears the fpu_fpregs_owner_ctx, | |
280 | * on this CPU. | |
281 | * | |
282 | * This will disable any lazy FPU state restore of the current FPU state, | |
283 | * but if the current thread owns the FPU, it will still be saved by. | |
284 | */ | |
285 | static inline void __cpu_disable_lazy_restore(unsigned int cpu) | |
286 | { | |
287 | per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; | |
288 | } | |
289 | ||
290 | static inline int fpu_want_lazy_restore(struct fpu *fpu, unsigned int cpu) | |
291 | { | |
292 | return fpu == this_cpu_read_stable(fpu_fpregs_owner_ctx) && cpu == fpu->last_cpu; | |
293 | } | |
294 | ||
295 | ||
32b49b3c IM |
296 | /* |
297 | * Wrap lazy FPU TS handling in a 'hw fpregs activation/deactivation' | |
298 | * idiom, which is then paired with the sw-flag (fpregs_active) later on: | |
299 | */ | |
300 | ||
301 | static inline void __fpregs_activate_hw(void) | |
302 | { | |
303 | if (!use_eager_fpu()) | |
304 | clts(); | |
305 | } | |
306 | ||
307 | static inline void __fpregs_deactivate_hw(void) | |
308 | { | |
309 | if (!use_eager_fpu()) | |
310 | stts(); | |
311 | } | |
312 | ||
313 | /* Must be paired with an 'stts' (fpregs_deactivate_hw()) after! */ | |
723c58e4 | 314 | static inline void __fpregs_deactivate(struct fpu *fpu) |
1361b83a | 315 | { |
e97131a8 IM |
316 | WARN_ON_FPU(!fpu->fpregs_active); |
317 | ||
d5cea9b0 | 318 | fpu->fpregs_active = 0; |
36b544dc | 319 | this_cpu_write(fpu_fpregs_owner_ctx, NULL); |
1361b83a LT |
320 | } |
321 | ||
32b49b3c | 322 | /* Must be paired with a 'clts' (fpregs_activate_hw()) before! */ |
dfaea4e6 | 323 | static inline void __fpregs_activate(struct fpu *fpu) |
1361b83a | 324 | { |
e97131a8 IM |
325 | WARN_ON_FPU(fpu->fpregs_active); |
326 | ||
d5cea9b0 | 327 | fpu->fpregs_active = 1; |
c0311f63 | 328 | this_cpu_write(fpu_fpregs_owner_ctx, fpu); |
1361b83a LT |
329 | } |
330 | ||
952f07ec IM |
331 | /* |
332 | * The question "does this thread have fpu access?" | |
333 | * is slightly racy, since preemption could come in | |
334 | * and revoke it immediately after the test. | |
335 | * | |
336 | * However, even in that very unlikely scenario, | |
337 | * we can just assume we have FPU access - typically | |
338 | * to save the FP state - we'll just take a #NM | |
339 | * fault and get the FPU access back. | |
340 | */ | |
3c6dffa9 | 341 | static inline int fpregs_active(void) |
952f07ec IM |
342 | { |
343 | return current->thread.fpu.fpregs_active; | |
344 | } | |
345 | ||
1361b83a LT |
346 | /* |
347 | * Encapsulate the CR0.TS handling together with the | |
348 | * software flag. | |
349 | * | |
350 | * These generally need preemption protection to work, | |
351 | * do try to avoid using these on their own. | |
352 | */ | |
66af8e27 | 353 | static inline void fpregs_activate(struct fpu *fpu) |
1361b83a | 354 | { |
32b49b3c | 355 | __fpregs_activate_hw(); |
66af8e27 | 356 | __fpregs_activate(fpu); |
1361b83a LT |
357 | } |
358 | ||
66af8e27 | 359 | static inline void fpregs_deactivate(struct fpu *fpu) |
1361b83a | 360 | { |
66af8e27 | 361 | __fpregs_deactivate(fpu); |
32b49b3c | 362 | __fpregs_deactivate_hw(); |
1361b83a LT |
363 | } |
364 | ||
365 | /* | |
366 | * FPU state switching for scheduling. | |
367 | * | |
368 | * This is a two-stage process: | |
369 | * | |
370 | * - switch_fpu_prepare() saves the old state and | |
371 | * sets the new state of the CR0.TS bit. This is | |
372 | * done within the context of the old process. | |
373 | * | |
374 | * - switch_fpu_finish() restores the new state as | |
375 | * necessary. | |
376 | */ | |
377 | typedef struct { int preload; } fpu_switch_t; | |
378 | ||
cb8818b6 IM |
379 | static inline fpu_switch_t |
380 | switch_fpu_prepare(struct fpu *old_fpu, struct fpu *new_fpu, int cpu) | |
1361b83a LT |
381 | { |
382 | fpu_switch_t fpu; | |
383 | ||
304bceda SS |
384 | /* |
385 | * If the task has used the math, pre-load the FPU on xsave processors | |
386 | * or if the past 5 consecutive context-switches used math. | |
387 | */ | |
c5bedc68 | 388 | fpu.preload = new_fpu->fpstate_active && |
cb8818b6 | 389 | (use_eager_fpu() || new_fpu->counter > 5); |
1361ef29 | 390 | |
d5cea9b0 | 391 | if (old_fpu->fpregs_active) { |
4f836347 | 392 | if (!copy_fpregs_to_fpstate(old_fpu)) |
cb8818b6 | 393 | old_fpu->last_cpu = -1; |
1361ef29 | 394 | else |
cb8818b6 | 395 | old_fpu->last_cpu = cpu; |
1361ef29 | 396 | |
36b544dc | 397 | /* But leave fpu_fpregs_owner_ctx! */ |
d5cea9b0 | 398 | old_fpu->fpregs_active = 0; |
1361b83a LT |
399 | |
400 | /* Don't change CR0.TS if we just switch! */ | |
401 | if (fpu.preload) { | |
cb8818b6 | 402 | new_fpu->counter++; |
dfaea4e6 | 403 | __fpregs_activate(new_fpu); |
7366ed77 | 404 | prefetch(&new_fpu->state); |
32b49b3c IM |
405 | } else { |
406 | __fpregs_deactivate_hw(); | |
407 | } | |
1361b83a | 408 | } else { |
cb8818b6 IM |
409 | old_fpu->counter = 0; |
410 | old_fpu->last_cpu = -1; | |
1361b83a | 411 | if (fpu.preload) { |
cb8818b6 | 412 | new_fpu->counter++; |
66ddc2cb | 413 | if (fpu_want_lazy_restore(new_fpu, cpu)) |
1361b83a LT |
414 | fpu.preload = 0; |
415 | else | |
7366ed77 | 416 | prefetch(&new_fpu->state); |
232f62cd | 417 | fpregs_activate(new_fpu); |
1361b83a LT |
418 | } |
419 | } | |
420 | return fpu; | |
421 | } | |
422 | ||
b1b64dc3 IM |
423 | /* |
424 | * Misc helper functions: | |
425 | */ | |
426 | ||
1361b83a LT |
427 | /* |
428 | * By the time this gets called, we've already cleared CR0.TS and | |
429 | * given the process the FPU if we are going to preload the FPU | |
430 | * state - all we need to do is to conditionally restore the register | |
431 | * state itself. | |
432 | */ | |
384a23f9 | 433 | static inline void switch_fpu_finish(struct fpu *new_fpu, fpu_switch_t fpu_switch) |
1361b83a | 434 | { |
384a23f9 | 435 | if (fpu_switch.preload) { |
e97131a8 IM |
436 | if (unlikely(copy_fpstate_to_fpregs(new_fpu))) { |
437 | WARN_ON_FPU(1); | |
fbce7782 | 438 | fpu__clear(new_fpu); |
e97131a8 | 439 | } |
1361b83a LT |
440 | } |
441 | } | |
442 | ||
1361b83a | 443 | /* |
fb14b4ea | 444 | * Needs to be preemption-safe. |
1361b83a | 445 | * |
377ffbcc | 446 | * NOTE! user_fpu_begin() must be used only immediately before restoring |
fb14b4ea ON |
447 | * the save state. It does not do any saving/restoring on its own. In |
448 | * lazy FPU mode, it is just an optimization to avoid a #NM exception, | |
449 | * the task can lose the FPU right after preempt_enable(). | |
1361b83a | 450 | */ |
1361b83a LT |
451 | static inline void user_fpu_begin(void) |
452 | { | |
4540d3fa IM |
453 | struct fpu *fpu = ¤t->thread.fpu; |
454 | ||
1361b83a | 455 | preempt_disable(); |
3c6dffa9 | 456 | if (!fpregs_active()) |
232f62cd | 457 | fpregs_activate(fpu); |
1361b83a LT |
458 | preempt_enable(); |
459 | } | |
460 | ||
b1b64dc3 IM |
461 | /* |
462 | * MXCSR and XCR definitions: | |
463 | */ | |
464 | ||
465 | extern unsigned int mxcsr_feature_mask; | |
466 | ||
467 | #define XCR_XFEATURE_ENABLED_MASK 0x00000000 | |
468 | ||
469 | static inline u64 xgetbv(u32 index) | |
470 | { | |
471 | u32 eax, edx; | |
472 | ||
473 | asm volatile(".byte 0x0f,0x01,0xd0" /* xgetbv */ | |
474 | : "=a" (eax), "=d" (edx) | |
475 | : "c" (index)); | |
476 | return eax + ((u64)edx << 32); | |
477 | } | |
478 | ||
479 | static inline void xsetbv(u32 index, u64 value) | |
480 | { | |
481 | u32 eax = value; | |
482 | u32 edx = value >> 32; | |
483 | ||
484 | asm volatile(".byte 0x0f,0x01,0xd1" /* xsetbv */ | |
485 | : : "a" (eax), "d" (edx), "c" (index)); | |
486 | } | |
487 | ||
78f7f1e5 | 488 | #endif /* _ASM_X86_FPU_INTERNAL_H */ |