Commit | Line | Data |
---|---|---|
1361b83a LT |
1 | /* |
2 | * Copyright (C) 1994 Linus Torvalds | |
3 | * | |
4 | * Pentium III FXSR, SSE support | |
5 | * General FPU state handling cleanups | |
6 | * Gareth Hughes <gareth@valinux.com>, May 2000 | |
7 | * x86-64 work by Andi Kleen 2002 | |
8 | */ | |
9 | ||
78f7f1e5 IM |
10 | #ifndef _ASM_X86_FPU_INTERNAL_H |
11 | #define _ASM_X86_FPU_INTERNAL_H | |
1361b83a | 12 | |
050902c0 | 13 | #include <linux/compat.h> |
952f07ec | 14 | #include <linux/sched.h> |
1361b83a | 15 | #include <linux/slab.h> |
f89e32e0 | 16 | |
1361b83a | 17 | #include <asm/user.h> |
df6b35f4 | 18 | #include <asm/fpu/api.h> |
669ebabb | 19 | #include <asm/fpu/xstate.h> |
1361b83a | 20 | |
6ffc152e IM |
21 | /* |
22 | * High level FPU state handling functions: | |
23 | */ | |
0c306bcf IM |
24 | extern void fpu__activate_curr(struct fpu *fpu); |
25 | extern void fpu__activate_stopped(struct fpu *fpu); | |
6ffc152e | 26 | extern void fpu__save(struct fpu *fpu); |
e1884d69 | 27 | extern void fpu__restore(struct fpu *fpu); |
82c0e45e | 28 | extern int fpu__restore_sig(void __user *buf, int ia32_frame); |
6ffc152e IM |
29 | extern void fpu__drop(struct fpu *fpu); |
30 | extern int fpu__copy(struct fpu *dst_fpu, struct fpu *src_fpu); | |
04c8e01d | 31 | extern void fpu__clear(struct fpu *fpu); |
b1b64dc3 IM |
32 | extern int fpu__exception_code(struct fpu *fpu, int trap_nr); |
33 | extern int dump_fpu(struct pt_regs *ptregs, struct user_i387_struct *fpstate); | |
6ffc152e | 34 | |
b1b64dc3 IM |
35 | /* |
36 | * Boot time FPU initialization functions: | |
37 | */ | |
38 | extern void fpu__init_cpu(void); | |
39 | extern void fpu__init_system_xstate(void); | |
40 | extern void fpu__init_cpu_xstate(void); | |
41 | extern void fpu__init_system(struct cpuinfo_x86 *c); | |
952f07ec IM |
42 | extern void fpu__init_check_bugs(void); |
43 | extern void fpu__resume_cpu(void); | |
44 | ||
e97131a8 IM |
45 | /* |
46 | * Debugging facility: | |
47 | */ | |
48 | #ifdef CONFIG_X86_DEBUG_FPU | |
49 | # define WARN_ON_FPU(x) WARN_ON_ONCE(x) | |
50 | #else | |
51 | # define WARN_ON_FPU(x) ({ 0; }) | |
52 | #endif | |
53 | ||
1c927eea | 54 | /* |
b1b64dc3 | 55 | * FPU related CPU feature flag helper routines: |
1c927eea | 56 | */ |
5d2bd700 SS |
57 | static __always_inline __pure bool use_eager_fpu(void) |
58 | { | |
c6b40691 | 59 | return static_cpu_has_safe(X86_FEATURE_EAGER_FPU); |
5d2bd700 SS |
60 | } |
61 | ||
1361b83a LT |
62 | static __always_inline __pure bool use_xsaveopt(void) |
63 | { | |
c6b40691 | 64 | return static_cpu_has_safe(X86_FEATURE_XSAVEOPT); |
1361b83a LT |
65 | } |
66 | ||
67 | static __always_inline __pure bool use_xsave(void) | |
68 | { | |
c6b40691 | 69 | return static_cpu_has_safe(X86_FEATURE_XSAVE); |
1361b83a LT |
70 | } |
71 | ||
72 | static __always_inline __pure bool use_fxsr(void) | |
73 | { | |
c6b40691 | 74 | return static_cpu_has_safe(X86_FEATURE_FXSR); |
1361b83a LT |
75 | } |
76 | ||
b1b64dc3 IM |
77 | /* |
78 | * fpstate handling functions: | |
79 | */ | |
80 | ||
81 | extern union fpregs_state init_fpstate; | |
82 | ||
83 | extern void fpstate_init(union fpregs_state *state); | |
84 | #ifdef CONFIG_MATH_EMULATION | |
85 | extern void fpstate_init_soft(struct swregs_state *soft); | |
86 | #else | |
87 | static inline void fpstate_init_soft(struct swregs_state *soft) {} | |
88 | #endif | |
89 | static inline void fpstate_init_fxstate(struct fxregs_state *fx) | |
90 | { | |
91 | fx->cwd = 0x37f; | |
92 | fx->mxcsr = MXCSR_DEFAULT; | |
93 | } | |
36e49e7f | 94 | extern void fpstate_sanitize_xstate(struct fpu *fpu); |
1361b83a | 95 | |
49b8c695 PA |
96 | #define user_insn(insn, output, input...) \ |
97 | ({ \ | |
98 | int err; \ | |
99 | asm volatile(ASM_STAC "\n" \ | |
100 | "1:" #insn "\n\t" \ | |
101 | "2: " ASM_CLAC "\n" \ | |
102 | ".section .fixup,\"ax\"\n" \ | |
103 | "3: movl $-1,%[err]\n" \ | |
104 | " jmp 2b\n" \ | |
105 | ".previous\n" \ | |
106 | _ASM_EXTABLE(1b, 3b) \ | |
107 | : [err] "=r" (err), output \ | |
108 | : "0"(0), input); \ | |
109 | err; \ | |
110 | }) | |
111 | ||
0ca5bd0d SS |
112 | #define check_insn(insn, output, input...) \ |
113 | ({ \ | |
114 | int err; \ | |
115 | asm volatile("1:" #insn "\n\t" \ | |
116 | "2:\n" \ | |
117 | ".section .fixup,\"ax\"\n" \ | |
118 | "3: movl $-1,%[err]\n" \ | |
119 | " jmp 2b\n" \ | |
120 | ".previous\n" \ | |
121 | _ASM_EXTABLE(1b, 3b) \ | |
122 | : [err] "=r" (err), output \ | |
123 | : "0"(0), input); \ | |
124 | err; \ | |
125 | }) | |
126 | ||
c47ada30 | 127 | static inline int copy_fregs_to_user(struct fregs_state __user *fx) |
1361b83a | 128 | { |
49b8c695 | 129 | return user_insn(fnsave %[fx]; fwait, [fx] "=m" (*fx), "m" (*fx)); |
1361b83a LT |
130 | } |
131 | ||
c47ada30 | 132 | static inline int copy_fxregs_to_user(struct fxregs_state __user *fx) |
1361b83a | 133 | { |
0ca5bd0d | 134 | if (config_enabled(CONFIG_X86_32)) |
49b8c695 | 135 | return user_insn(fxsave %[fx], [fx] "=m" (*fx), "m" (*fx)); |
0ca5bd0d | 136 | else if (config_enabled(CONFIG_AS_FXSAVEQ)) |
49b8c695 | 137 | return user_insn(fxsaveq %[fx], [fx] "=m" (*fx), "m" (*fx)); |
1361b83a | 138 | |
c6813144 | 139 | /* See comment in copy_fxregs_to_kernel() below. */ |
49b8c695 | 140 | return user_insn(rex64/fxsave (%[fx]), "=m" (*fx), [fx] "R" (fx)); |
1361b83a LT |
141 | } |
142 | ||
c47ada30 | 143 | static inline int copy_kernel_to_fxregs(struct fxregs_state *fx) |
1361b83a | 144 | { |
0ca5bd0d SS |
145 | if (config_enabled(CONFIG_X86_32)) |
146 | return check_insn(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx)); | |
147 | else if (config_enabled(CONFIG_AS_FXSAVEQ)) | |
148 | return check_insn(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx)); | |
1361b83a | 149 | |
c6813144 | 150 | /* See comment in copy_fxregs_to_kernel() below. */ |
0ca5bd0d SS |
151 | return check_insn(rex64/fxrstor (%[fx]), "=m" (*fx), [fx] "R" (fx), |
152 | "m" (*fx)); | |
1361b83a LT |
153 | } |
154 | ||
c47ada30 | 155 | static inline int copy_user_to_fxregs(struct fxregs_state __user *fx) |
e139e955 PA |
156 | { |
157 | if (config_enabled(CONFIG_X86_32)) | |
158 | return user_insn(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx)); | |
159 | else if (config_enabled(CONFIG_AS_FXSAVEQ)) | |
160 | return user_insn(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx)); | |
161 | ||
c6813144 | 162 | /* See comment in copy_fxregs_to_kernel() below. */ |
e139e955 PA |
163 | return user_insn(rex64/fxrstor (%[fx]), "=m" (*fx), [fx] "R" (fx), |
164 | "m" (*fx)); | |
165 | } | |
166 | ||
c47ada30 | 167 | static inline int copy_kernel_to_fregs(struct fregs_state *fx) |
1361b83a | 168 | { |
0ca5bd0d | 169 | return check_insn(frstor %[fx], "=m" (*fx), [fx] "m" (*fx)); |
e139e955 PA |
170 | } |
171 | ||
c47ada30 | 172 | static inline int copy_user_to_fregs(struct fregs_state __user *fx) |
e139e955 PA |
173 | { |
174 | return user_insn(frstor %[fx], "=m" (*fx), [fx] "m" (*fx)); | |
1361b83a LT |
175 | } |
176 | ||
c6813144 | 177 | static inline void copy_fxregs_to_kernel(struct fpu *fpu) |
1361b83a | 178 | { |
0ca5bd0d | 179 | if (config_enabled(CONFIG_X86_32)) |
7366ed77 | 180 | asm volatile( "fxsave %[fx]" : [fx] "=m" (fpu->state.fxsave)); |
0ca5bd0d | 181 | else if (config_enabled(CONFIG_AS_FXSAVEQ)) |
7366ed77 | 182 | asm volatile("fxsaveq %[fx]" : [fx] "=m" (fpu->state.fxsave)); |
0ca5bd0d SS |
183 | else { |
184 | /* Using "rex64; fxsave %0" is broken because, if the memory | |
185 | * operand uses any extended registers for addressing, a second | |
186 | * REX prefix will be generated (to the assembler, rex64 | |
187 | * followed by semicolon is a separate instruction), and hence | |
188 | * the 64-bitness is lost. | |
189 | * | |
190 | * Using "fxsaveq %0" would be the ideal choice, but is only | |
191 | * supported starting with gas 2.16. | |
192 | * | |
193 | * Using, as a workaround, the properly prefixed form below | |
194 | * isn't accepted by any binutils version so far released, | |
195 | * complaining that the same type of prefix is used twice if | |
196 | * an extended register is needed for addressing (fix submitted | |
197 | * to mainline 2005-11-21). | |
198 | * | |
7366ed77 | 199 | * asm volatile("rex64/fxsave %0" : "=m" (fpu->state.fxsave)); |
0ca5bd0d SS |
200 | * |
201 | * This, however, we can work around by forcing the compiler to | |
202 | * select an addressing mode that doesn't require extended | |
203 | * registers. | |
204 | */ | |
205 | asm volatile( "rex64/fxsave (%[fx])" | |
7366ed77 IM |
206 | : "=m" (fpu->state.fxsave) |
207 | : [fx] "R" (&fpu->state.fxsave)); | |
0ca5bd0d | 208 | } |
1361b83a LT |
209 | } |
210 | ||
fd169b05 IM |
211 | /* These macros all use (%edi)/(%rdi) as the single memory argument. */ |
212 | #define XSAVE ".byte " REX_PREFIX "0x0f,0xae,0x27" | |
213 | #define XSAVEOPT ".byte " REX_PREFIX "0x0f,0xae,0x37" | |
214 | #define XSAVES ".byte " REX_PREFIX "0x0f,0xc7,0x2f" | |
215 | #define XRSTOR ".byte " REX_PREFIX "0x0f,0xae,0x2f" | |
216 | #define XRSTORS ".byte " REX_PREFIX "0x0f,0xc7,0x1f" | |
217 | ||
218 | /* xstate instruction fault handler: */ | |
219 | #define xstate_fault(__err) \ | |
220 | \ | |
221 | ".section .fixup,\"ax\"\n" \ | |
222 | \ | |
87b6559d | 223 | "3: movl $-2,%[_err]\n" \ |
fd169b05 IM |
224 | " jmp 2b\n" \ |
225 | \ | |
226 | ".previous\n" \ | |
227 | \ | |
228 | _ASM_EXTABLE(1b, 3b) \ | |
87b6559d | 229 | : [_err] "=r" (__err) |
fd169b05 IM |
230 | |
231 | /* | |
232 | * This function is called only during boot time when x86 caps are not set | |
233 | * up and alternative can not be used yet. | |
234 | */ | |
87dafd41 | 235 | static inline int copy_xregs_to_kernel_booting(struct xregs_state *xstate) |
fd169b05 IM |
236 | { |
237 | u64 mask = -1; | |
238 | u32 lmask = mask; | |
239 | u32 hmask = mask >> 32; | |
240 | int err = 0; | |
241 | ||
242 | WARN_ON(system_state != SYSTEM_BOOTING); | |
243 | ||
244 | if (boot_cpu_has(X86_FEATURE_XSAVES)) | |
245 | asm volatile("1:"XSAVES"\n\t" | |
246 | "2:\n\t" | |
247 | xstate_fault(err) | |
87b6559d IM |
248 | : "D" (xstate), "m" (*xstate), "a" (lmask), "d" (hmask), "0" (err) |
249 | : "memory"); | |
fd169b05 IM |
250 | else |
251 | asm volatile("1:"XSAVE"\n\t" | |
252 | "2:\n\t" | |
253 | xstate_fault(err) | |
87b6559d IM |
254 | : "D" (xstate), "m" (*xstate), "a" (lmask), "d" (hmask), "0" (err) |
255 | : "memory"); | |
fd169b05 IM |
256 | return err; |
257 | } | |
258 | ||
259 | /* | |
260 | * This function is called only during boot time when x86 caps are not set | |
261 | * up and alternative can not be used yet. | |
262 | */ | |
87dafd41 | 263 | static inline int copy_kernel_to_xregs_booting(struct xregs_state *xstate, u64 mask) |
fd169b05 IM |
264 | { |
265 | u32 lmask = mask; | |
266 | u32 hmask = mask >> 32; | |
267 | int err = 0; | |
268 | ||
269 | WARN_ON(system_state != SYSTEM_BOOTING); | |
270 | ||
271 | if (boot_cpu_has(X86_FEATURE_XSAVES)) | |
272 | asm volatile("1:"XRSTORS"\n\t" | |
273 | "2:\n\t" | |
274 | xstate_fault(err) | |
87b6559d IM |
275 | : "D" (xstate), "m" (*xstate), "a" (lmask), "d" (hmask), "0" (err) |
276 | : "memory"); | |
fd169b05 IM |
277 | else |
278 | asm volatile("1:"XRSTOR"\n\t" | |
279 | "2:\n\t" | |
280 | xstate_fault(err) | |
87b6559d IM |
281 | : "D" (xstate), "m" (*xstate), "a" (lmask), "d" (hmask), "0" (err) |
282 | : "memory"); | |
fd169b05 IM |
283 | return err; |
284 | } | |
285 | ||
286 | /* | |
287 | * Save processor xstate to xsave area. | |
288 | */ | |
87dafd41 | 289 | static inline int copy_xregs_to_kernel(struct xregs_state *xstate) |
fd169b05 IM |
290 | { |
291 | u64 mask = -1; | |
292 | u32 lmask = mask; | |
293 | u32 hmask = mask >> 32; | |
294 | int err = 0; | |
295 | ||
296 | WARN_ON(!alternatives_patched); | |
297 | ||
298 | /* | |
299 | * If xsaves is enabled, xsaves replaces xsaveopt because | |
300 | * it supports compact format and supervisor states in addition to | |
301 | * modified optimization in xsaveopt. | |
302 | * | |
303 | * Otherwise, if xsaveopt is enabled, xsaveopt replaces xsave | |
304 | * because xsaveopt supports modified optimization which is not | |
305 | * supported by xsave. | |
306 | * | |
307 | * If none of xsaves and xsaveopt is enabled, use xsave. | |
308 | */ | |
309 | alternative_input_2( | |
310 | "1:"XSAVE, | |
311 | XSAVEOPT, | |
312 | X86_FEATURE_XSAVEOPT, | |
313 | XSAVES, | |
314 | X86_FEATURE_XSAVES, | |
87dafd41 | 315 | [xstate] "D" (xstate), "a" (lmask), "d" (hmask) : |
fd169b05 IM |
316 | "memory"); |
317 | asm volatile("2:\n\t" | |
318 | xstate_fault(err) | |
319 | : "0" (0) | |
320 | : "memory"); | |
321 | ||
322 | return err; | |
323 | } | |
324 | ||
325 | /* | |
326 | * Restore processor xstate from xsave area. | |
327 | */ | |
87dafd41 | 328 | static inline int copy_kernel_to_xregs(struct xregs_state *xstate, u64 mask) |
fd169b05 IM |
329 | { |
330 | int err = 0; | |
331 | u32 lmask = mask; | |
332 | u32 hmask = mask >> 32; | |
333 | ||
334 | /* | |
335 | * Use xrstors to restore context if it is enabled. xrstors supports | |
336 | * compacted format of xsave area which is not supported by xrstor. | |
337 | */ | |
338 | alternative_input( | |
339 | "1: " XRSTOR, | |
340 | XRSTORS, | |
341 | X86_FEATURE_XSAVES, | |
87dafd41 | 342 | "D" (xstate), "m" (*xstate), "a" (lmask), "d" (hmask) |
fd169b05 IM |
343 | : "memory"); |
344 | ||
345 | asm volatile("2:\n" | |
346 | xstate_fault(err) | |
347 | : "0" (0) | |
348 | : "memory"); | |
349 | ||
350 | return err; | |
351 | } | |
352 | ||
353 | /* | |
354 | * Save xstate to user space xsave area. | |
355 | * | |
356 | * We don't use modified optimization because xrstor/xrstors might track | |
357 | * a different application. | |
358 | * | |
359 | * We don't use compacted format xsave area for | |
360 | * backward compatibility for old applications which don't understand | |
361 | * compacted format of xsave area. | |
362 | */ | |
363 | static inline int copy_xregs_to_user(struct xregs_state __user *buf) | |
364 | { | |
365 | int err; | |
366 | ||
367 | /* | |
368 | * Clear the xsave header first, so that reserved fields are | |
369 | * initialized to zero. | |
370 | */ | |
371 | err = __clear_user(&buf->header, sizeof(buf->header)); | |
372 | if (unlikely(err)) | |
373 | return -EFAULT; | |
374 | ||
375 | __asm__ __volatile__(ASM_STAC "\n" | |
376 | "1:"XSAVE"\n" | |
377 | "2: " ASM_CLAC "\n" | |
378 | xstate_fault(err) | |
379 | : "D" (buf), "a" (-1), "d" (-1), "0" (0) | |
380 | : "memory"); | |
381 | return err; | |
382 | } | |
383 | ||
384 | /* | |
385 | * Restore xstate from user space xsave area. | |
386 | */ | |
387 | static inline int copy_user_to_xregs(struct xregs_state __user *buf, u64 mask) | |
388 | { | |
389 | int err = 0; | |
390 | struct xregs_state *xstate = ((__force struct xregs_state *)buf); | |
391 | u32 lmask = mask; | |
392 | u32 hmask = mask >> 32; | |
393 | ||
394 | __asm__ __volatile__(ASM_STAC "\n" | |
395 | "1:"XRSTOR"\n" | |
396 | "2: " ASM_CLAC "\n" | |
397 | xstate_fault(err) | |
398 | : "D" (xstate), "a" (lmask), "d" (hmask), "0" (0) | |
399 | : "memory"); /* memory required? */ | |
400 | return err; | |
401 | } | |
402 | ||
1361b83a LT |
403 | /* |
404 | * These must be called with preempt disabled. Returns | |
4f836347 IM |
405 | * 'true' if the FPU state is still intact and we can |
406 | * keep registers active. | |
407 | * | |
408 | * The legacy FNSAVE instruction cleared all FPU state | |
409 | * unconditionally, so registers are essentially destroyed. | |
410 | * Modern FPU state can be kept in registers, if there are | |
1bc6b056 | 411 | * no pending FP exceptions. |
1361b83a | 412 | */ |
4f836347 | 413 | static inline int copy_fpregs_to_fpstate(struct fpu *fpu) |
1361b83a | 414 | { |
1bc6b056 | 415 | if (likely(use_xsave())) { |
c6813144 | 416 | copy_xregs_to_kernel(&fpu->state.xsave); |
1bc6b056 IM |
417 | return 1; |
418 | } | |
1361b83a | 419 | |
1bc6b056 | 420 | if (likely(use_fxsr())) { |
c6813144 | 421 | copy_fxregs_to_kernel(fpu); |
1bc6b056 | 422 | return 1; |
1361b83a LT |
423 | } |
424 | ||
425 | /* | |
1bc6b056 IM |
426 | * Legacy FPU register saving, FNSAVE always clears FPU registers, |
427 | * so we have to mark them inactive: | |
1361b83a | 428 | */ |
87dafd41 | 429 | asm volatile("fnsave %[fp]; fwait" : [fp] "=m" (fpu->state.fsave)); |
4f836347 | 430 | |
4f836347 | 431 | return 0; |
1361b83a LT |
432 | } |
433 | ||
0e75c54f | 434 | static inline int __copy_fpstate_to_fpregs(struct fpu *fpu) |
1361b83a LT |
435 | { |
436 | if (use_xsave()) | |
c6813144 | 437 | return copy_kernel_to_xregs(&fpu->state.xsave, -1); |
0ca5bd0d | 438 | else if (use_fxsr()) |
c6813144 | 439 | return copy_kernel_to_fxregs(&fpu->state.fxsave); |
1361b83a | 440 | else |
c6813144 | 441 | return copy_kernel_to_fregs(&fpu->state.fsave); |
1361b83a LT |
442 | } |
443 | ||
0e75c54f | 444 | static inline int copy_fpstate_to_fpregs(struct fpu *fpu) |
1361b83a | 445 | { |
6ca7a8a1 BP |
446 | /* |
447 | * AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception is | |
448 | * pending. Clear the x87 state here by setting it to fixed values. | |
449 | * "m" is a random variable that should be in L1. | |
450 | */ | |
9b13a93d | 451 | if (unlikely(static_cpu_has_bug_safe(X86_BUG_FXSAVE_LEAK))) { |
26bef131 LT |
452 | asm volatile( |
453 | "fnclex\n\t" | |
454 | "emms\n\t" | |
455 | "fildl %P[addr]" /* set F?P to defined value */ | |
d5cea9b0 | 456 | : : [addr] "m" (fpu->fpregs_active)); |
26bef131 | 457 | } |
1361b83a | 458 | |
0e75c54f | 459 | return __copy_fpstate_to_fpregs(fpu); |
1361b83a LT |
460 | } |
461 | ||
87dafd41 | 462 | extern int copy_fpstate_to_sigframe(void __user *buf, void __user *fp, int size); |
b1b64dc3 IM |
463 | |
464 | /* | |
465 | * FPU context switch related helper methods: | |
466 | */ | |
467 | ||
468 | DECLARE_PER_CPU(struct fpu *, fpu_fpregs_owner_ctx); | |
469 | ||
470 | /* | |
471 | * Must be run with preemption disabled: this clears the fpu_fpregs_owner_ctx, | |
472 | * on this CPU. | |
473 | * | |
474 | * This will disable any lazy FPU state restore of the current FPU state, | |
475 | * but if the current thread owns the FPU, it will still be saved by. | |
476 | */ | |
477 | static inline void __cpu_disable_lazy_restore(unsigned int cpu) | |
478 | { | |
479 | per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; | |
480 | } | |
481 | ||
482 | static inline int fpu_want_lazy_restore(struct fpu *fpu, unsigned int cpu) | |
483 | { | |
484 | return fpu == this_cpu_read_stable(fpu_fpregs_owner_ctx) && cpu == fpu->last_cpu; | |
485 | } | |
486 | ||
487 | ||
32b49b3c IM |
488 | /* |
489 | * Wrap lazy FPU TS handling in a 'hw fpregs activation/deactivation' | |
490 | * idiom, which is then paired with the sw-flag (fpregs_active) later on: | |
491 | */ | |
492 | ||
493 | static inline void __fpregs_activate_hw(void) | |
494 | { | |
495 | if (!use_eager_fpu()) | |
496 | clts(); | |
497 | } | |
498 | ||
499 | static inline void __fpregs_deactivate_hw(void) | |
500 | { | |
501 | if (!use_eager_fpu()) | |
502 | stts(); | |
503 | } | |
504 | ||
505 | /* Must be paired with an 'stts' (fpregs_deactivate_hw()) after! */ | |
723c58e4 | 506 | static inline void __fpregs_deactivate(struct fpu *fpu) |
1361b83a | 507 | { |
e97131a8 IM |
508 | WARN_ON_FPU(!fpu->fpregs_active); |
509 | ||
d5cea9b0 | 510 | fpu->fpregs_active = 0; |
36b544dc | 511 | this_cpu_write(fpu_fpregs_owner_ctx, NULL); |
1361b83a LT |
512 | } |
513 | ||
32b49b3c | 514 | /* Must be paired with a 'clts' (fpregs_activate_hw()) before! */ |
dfaea4e6 | 515 | static inline void __fpregs_activate(struct fpu *fpu) |
1361b83a | 516 | { |
e97131a8 IM |
517 | WARN_ON_FPU(fpu->fpregs_active); |
518 | ||
d5cea9b0 | 519 | fpu->fpregs_active = 1; |
c0311f63 | 520 | this_cpu_write(fpu_fpregs_owner_ctx, fpu); |
1361b83a LT |
521 | } |
522 | ||
952f07ec IM |
523 | /* |
524 | * The question "does this thread have fpu access?" | |
525 | * is slightly racy, since preemption could come in | |
526 | * and revoke it immediately after the test. | |
527 | * | |
528 | * However, even in that very unlikely scenario, | |
529 | * we can just assume we have FPU access - typically | |
530 | * to save the FP state - we'll just take a #NM | |
531 | * fault and get the FPU access back. | |
532 | */ | |
3c6dffa9 | 533 | static inline int fpregs_active(void) |
952f07ec IM |
534 | { |
535 | return current->thread.fpu.fpregs_active; | |
536 | } | |
537 | ||
1361b83a LT |
538 | /* |
539 | * Encapsulate the CR0.TS handling together with the | |
540 | * software flag. | |
541 | * | |
542 | * These generally need preemption protection to work, | |
543 | * do try to avoid using these on their own. | |
544 | */ | |
66af8e27 | 545 | static inline void fpregs_activate(struct fpu *fpu) |
1361b83a | 546 | { |
32b49b3c | 547 | __fpregs_activate_hw(); |
66af8e27 | 548 | __fpregs_activate(fpu); |
1361b83a LT |
549 | } |
550 | ||
66af8e27 | 551 | static inline void fpregs_deactivate(struct fpu *fpu) |
1361b83a | 552 | { |
66af8e27 | 553 | __fpregs_deactivate(fpu); |
32b49b3c | 554 | __fpregs_deactivate_hw(); |
1361b83a LT |
555 | } |
556 | ||
557 | /* | |
558 | * FPU state switching for scheduling. | |
559 | * | |
560 | * This is a two-stage process: | |
561 | * | |
562 | * - switch_fpu_prepare() saves the old state and | |
563 | * sets the new state of the CR0.TS bit. This is | |
564 | * done within the context of the old process. | |
565 | * | |
566 | * - switch_fpu_finish() restores the new state as | |
567 | * necessary. | |
568 | */ | |
569 | typedef struct { int preload; } fpu_switch_t; | |
570 | ||
cb8818b6 IM |
571 | static inline fpu_switch_t |
572 | switch_fpu_prepare(struct fpu *old_fpu, struct fpu *new_fpu, int cpu) | |
1361b83a LT |
573 | { |
574 | fpu_switch_t fpu; | |
575 | ||
304bceda SS |
576 | /* |
577 | * If the task has used the math, pre-load the FPU on xsave processors | |
578 | * or if the past 5 consecutive context-switches used math. | |
579 | */ | |
c5bedc68 | 580 | fpu.preload = new_fpu->fpstate_active && |
cb8818b6 | 581 | (use_eager_fpu() || new_fpu->counter > 5); |
1361ef29 | 582 | |
d5cea9b0 | 583 | if (old_fpu->fpregs_active) { |
4f836347 | 584 | if (!copy_fpregs_to_fpstate(old_fpu)) |
cb8818b6 | 585 | old_fpu->last_cpu = -1; |
1361ef29 | 586 | else |
cb8818b6 | 587 | old_fpu->last_cpu = cpu; |
1361ef29 | 588 | |
36b544dc | 589 | /* But leave fpu_fpregs_owner_ctx! */ |
d5cea9b0 | 590 | old_fpu->fpregs_active = 0; |
1361b83a LT |
591 | |
592 | /* Don't change CR0.TS if we just switch! */ | |
593 | if (fpu.preload) { | |
cb8818b6 | 594 | new_fpu->counter++; |
dfaea4e6 | 595 | __fpregs_activate(new_fpu); |
7366ed77 | 596 | prefetch(&new_fpu->state); |
32b49b3c IM |
597 | } else { |
598 | __fpregs_deactivate_hw(); | |
599 | } | |
1361b83a | 600 | } else { |
cb8818b6 IM |
601 | old_fpu->counter = 0; |
602 | old_fpu->last_cpu = -1; | |
1361b83a | 603 | if (fpu.preload) { |
cb8818b6 | 604 | new_fpu->counter++; |
66ddc2cb | 605 | if (fpu_want_lazy_restore(new_fpu, cpu)) |
1361b83a LT |
606 | fpu.preload = 0; |
607 | else | |
7366ed77 | 608 | prefetch(&new_fpu->state); |
232f62cd | 609 | fpregs_activate(new_fpu); |
1361b83a LT |
610 | } |
611 | } | |
612 | return fpu; | |
613 | } | |
614 | ||
b1b64dc3 IM |
615 | /* |
616 | * Misc helper functions: | |
617 | */ | |
618 | ||
1361b83a LT |
619 | /* |
620 | * By the time this gets called, we've already cleared CR0.TS and | |
621 | * given the process the FPU if we are going to preload the FPU | |
622 | * state - all we need to do is to conditionally restore the register | |
623 | * state itself. | |
624 | */ | |
384a23f9 | 625 | static inline void switch_fpu_finish(struct fpu *new_fpu, fpu_switch_t fpu_switch) |
1361b83a | 626 | { |
384a23f9 | 627 | if (fpu_switch.preload) { |
e97131a8 IM |
628 | if (unlikely(copy_fpstate_to_fpregs(new_fpu))) { |
629 | WARN_ON_FPU(1); | |
fbce7782 | 630 | fpu__clear(new_fpu); |
e97131a8 | 631 | } |
1361b83a LT |
632 | } |
633 | } | |
634 | ||
1361b83a | 635 | /* |
fb14b4ea | 636 | * Needs to be preemption-safe. |
1361b83a | 637 | * |
377ffbcc | 638 | * NOTE! user_fpu_begin() must be used only immediately before restoring |
fb14b4ea ON |
639 | * the save state. It does not do any saving/restoring on its own. In |
640 | * lazy FPU mode, it is just an optimization to avoid a #NM exception, | |
641 | * the task can lose the FPU right after preempt_enable(). | |
1361b83a | 642 | */ |
1361b83a LT |
643 | static inline void user_fpu_begin(void) |
644 | { | |
4540d3fa IM |
645 | struct fpu *fpu = ¤t->thread.fpu; |
646 | ||
1361b83a | 647 | preempt_disable(); |
3c6dffa9 | 648 | if (!fpregs_active()) |
232f62cd | 649 | fpregs_activate(fpu); |
1361b83a LT |
650 | preempt_enable(); |
651 | } | |
652 | ||
b1b64dc3 IM |
653 | /* |
654 | * MXCSR and XCR definitions: | |
655 | */ | |
656 | ||
657 | extern unsigned int mxcsr_feature_mask; | |
658 | ||
659 | #define XCR_XFEATURE_ENABLED_MASK 0x00000000 | |
660 | ||
661 | static inline u64 xgetbv(u32 index) | |
662 | { | |
663 | u32 eax, edx; | |
664 | ||
665 | asm volatile(".byte 0x0f,0x01,0xd0" /* xgetbv */ | |
666 | : "=a" (eax), "=d" (edx) | |
667 | : "c" (index)); | |
668 | return eax + ((u64)edx << 32); | |
669 | } | |
670 | ||
671 | static inline void xsetbv(u32 index, u64 value) | |
672 | { | |
673 | u32 eax = value; | |
674 | u32 edx = value >> 32; | |
675 | ||
676 | asm volatile(".byte 0x0f,0x01,0xd1" /* xsetbv */ | |
677 | : : "a" (eax), "d" (edx), "c" (index)); | |
678 | } | |
679 | ||
78f7f1e5 | 680 | #endif /* _ASM_X86_FPU_INTERNAL_H */ |