Commit | Line | Data |
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1361b83a LT |
1 | /* |
2 | * Copyright (C) 1994 Linus Torvalds | |
3 | * | |
4 | * Pentium III FXSR, SSE support | |
5 | * General FPU state handling cleanups | |
6 | * Gareth Hughes <gareth@valinux.com>, May 2000 | |
7 | * x86-64 work by Andi Kleen 2002 | |
8 | */ | |
9 | ||
78f7f1e5 IM |
10 | #ifndef _ASM_X86_FPU_INTERNAL_H |
11 | #define _ASM_X86_FPU_INTERNAL_H | |
1361b83a | 12 | |
050902c0 | 13 | #include <linux/compat.h> |
952f07ec | 14 | #include <linux/sched.h> |
1361b83a | 15 | #include <linux/slab.h> |
f89e32e0 | 16 | |
1361b83a | 17 | #include <asm/user.h> |
df6b35f4 | 18 | #include <asm/fpu/api.h> |
669ebabb | 19 | #include <asm/fpu/xstate.h> |
1361b83a | 20 | |
6ffc152e IM |
21 | /* |
22 | * High level FPU state handling functions: | |
23 | */ | |
0c306bcf | 24 | extern void fpu__activate_curr(struct fpu *fpu); |
05602812 | 25 | extern void fpu__activate_fpstate_read(struct fpu *fpu); |
6a81d7eb | 26 | extern void fpu__activate_fpstate_write(struct fpu *fpu); |
6ffc152e | 27 | extern void fpu__save(struct fpu *fpu); |
e1884d69 | 28 | extern void fpu__restore(struct fpu *fpu); |
82c0e45e | 29 | extern int fpu__restore_sig(void __user *buf, int ia32_frame); |
6ffc152e IM |
30 | extern void fpu__drop(struct fpu *fpu); |
31 | extern int fpu__copy(struct fpu *dst_fpu, struct fpu *src_fpu); | |
04c8e01d | 32 | extern void fpu__clear(struct fpu *fpu); |
b1b64dc3 IM |
33 | extern int fpu__exception_code(struct fpu *fpu, int trap_nr); |
34 | extern int dump_fpu(struct pt_regs *ptregs, struct user_i387_struct *fpstate); | |
6ffc152e | 35 | |
b1b64dc3 IM |
36 | /* |
37 | * Boot time FPU initialization functions: | |
38 | */ | |
39 | extern void fpu__init_cpu(void); | |
40 | extern void fpu__init_system_xstate(void); | |
41 | extern void fpu__init_cpu_xstate(void); | |
42 | extern void fpu__init_system(struct cpuinfo_x86 *c); | |
952f07ec IM |
43 | extern void fpu__init_check_bugs(void); |
44 | extern void fpu__resume_cpu(void); | |
45 | ||
e97131a8 IM |
46 | /* |
47 | * Debugging facility: | |
48 | */ | |
49 | #ifdef CONFIG_X86_DEBUG_FPU | |
50 | # define WARN_ON_FPU(x) WARN_ON_ONCE(x) | |
51 | #else | |
52 | # define WARN_ON_FPU(x) ({ 0; }) | |
53 | #endif | |
54 | ||
1c927eea | 55 | /* |
b1b64dc3 | 56 | * FPU related CPU feature flag helper routines: |
1c927eea | 57 | */ |
5d2bd700 SS |
58 | static __always_inline __pure bool use_eager_fpu(void) |
59 | { | |
c6b40691 | 60 | return static_cpu_has_safe(X86_FEATURE_EAGER_FPU); |
5d2bd700 SS |
61 | } |
62 | ||
1361b83a LT |
63 | static __always_inline __pure bool use_xsaveopt(void) |
64 | { | |
c6b40691 | 65 | return static_cpu_has_safe(X86_FEATURE_XSAVEOPT); |
1361b83a LT |
66 | } |
67 | ||
68 | static __always_inline __pure bool use_xsave(void) | |
69 | { | |
c6b40691 | 70 | return static_cpu_has_safe(X86_FEATURE_XSAVE); |
1361b83a LT |
71 | } |
72 | ||
73 | static __always_inline __pure bool use_fxsr(void) | |
74 | { | |
c6b40691 | 75 | return static_cpu_has_safe(X86_FEATURE_FXSR); |
1361b83a LT |
76 | } |
77 | ||
b1b64dc3 IM |
78 | /* |
79 | * fpstate handling functions: | |
80 | */ | |
81 | ||
82 | extern union fpregs_state init_fpstate; | |
83 | ||
84 | extern void fpstate_init(union fpregs_state *state); | |
85 | #ifdef CONFIG_MATH_EMULATION | |
86 | extern void fpstate_init_soft(struct swregs_state *soft); | |
87 | #else | |
88 | static inline void fpstate_init_soft(struct swregs_state *soft) {} | |
89 | #endif | |
90 | static inline void fpstate_init_fxstate(struct fxregs_state *fx) | |
91 | { | |
92 | fx->cwd = 0x37f; | |
93 | fx->mxcsr = MXCSR_DEFAULT; | |
94 | } | |
36e49e7f | 95 | extern void fpstate_sanitize_xstate(struct fpu *fpu); |
1361b83a | 96 | |
49b8c695 PA |
97 | #define user_insn(insn, output, input...) \ |
98 | ({ \ | |
99 | int err; \ | |
100 | asm volatile(ASM_STAC "\n" \ | |
101 | "1:" #insn "\n\t" \ | |
102 | "2: " ASM_CLAC "\n" \ | |
103 | ".section .fixup,\"ax\"\n" \ | |
104 | "3: movl $-1,%[err]\n" \ | |
105 | " jmp 2b\n" \ | |
106 | ".previous\n" \ | |
107 | _ASM_EXTABLE(1b, 3b) \ | |
108 | : [err] "=r" (err), output \ | |
109 | : "0"(0), input); \ | |
110 | err; \ | |
111 | }) | |
112 | ||
0ca5bd0d SS |
113 | #define check_insn(insn, output, input...) \ |
114 | ({ \ | |
115 | int err; \ | |
116 | asm volatile("1:" #insn "\n\t" \ | |
117 | "2:\n" \ | |
118 | ".section .fixup,\"ax\"\n" \ | |
119 | "3: movl $-1,%[err]\n" \ | |
120 | " jmp 2b\n" \ | |
121 | ".previous\n" \ | |
122 | _ASM_EXTABLE(1b, 3b) \ | |
123 | : [err] "=r" (err), output \ | |
124 | : "0"(0), input); \ | |
125 | err; \ | |
126 | }) | |
127 | ||
c47ada30 | 128 | static inline int copy_fregs_to_user(struct fregs_state __user *fx) |
1361b83a | 129 | { |
49b8c695 | 130 | return user_insn(fnsave %[fx]; fwait, [fx] "=m" (*fx), "m" (*fx)); |
1361b83a LT |
131 | } |
132 | ||
c47ada30 | 133 | static inline int copy_fxregs_to_user(struct fxregs_state __user *fx) |
1361b83a | 134 | { |
0ca5bd0d | 135 | if (config_enabled(CONFIG_X86_32)) |
49b8c695 | 136 | return user_insn(fxsave %[fx], [fx] "=m" (*fx), "m" (*fx)); |
0ca5bd0d | 137 | else if (config_enabled(CONFIG_AS_FXSAVEQ)) |
49b8c695 | 138 | return user_insn(fxsaveq %[fx], [fx] "=m" (*fx), "m" (*fx)); |
1361b83a | 139 | |
c6813144 | 140 | /* See comment in copy_fxregs_to_kernel() below. */ |
49b8c695 | 141 | return user_insn(rex64/fxsave (%[fx]), "=m" (*fx), [fx] "R" (fx)); |
1361b83a LT |
142 | } |
143 | ||
9ccc27a5 | 144 | static inline void copy_kernel_to_fxregs(struct fxregs_state *fx) |
1361b83a | 145 | { |
43b287b3 IM |
146 | int err; |
147 | ||
148 | if (config_enabled(CONFIG_X86_32)) { | |
149 | err = check_insn(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx)); | |
150 | } else { | |
151 | if (config_enabled(CONFIG_AS_FXSAVEQ)) { | |
152 | err = check_insn(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx)); | |
153 | } else { | |
154 | /* See comment in copy_fxregs_to_kernel() below. */ | |
155 | err = check_insn(rex64/fxrstor (%[fx]), "=m" (*fx), [fx] "R" (fx), "m" (*fx)); | |
156 | } | |
157 | } | |
158 | /* Copying from a kernel buffer to FPU registers should never fail: */ | |
159 | WARN_ON_FPU(err); | |
1361b83a LT |
160 | } |
161 | ||
c47ada30 | 162 | static inline int copy_user_to_fxregs(struct fxregs_state __user *fx) |
e139e955 PA |
163 | { |
164 | if (config_enabled(CONFIG_X86_32)) | |
165 | return user_insn(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx)); | |
166 | else if (config_enabled(CONFIG_AS_FXSAVEQ)) | |
167 | return user_insn(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx)); | |
168 | ||
c6813144 | 169 | /* See comment in copy_fxregs_to_kernel() below. */ |
e139e955 PA |
170 | return user_insn(rex64/fxrstor (%[fx]), "=m" (*fx), [fx] "R" (fx), |
171 | "m" (*fx)); | |
172 | } | |
173 | ||
9ccc27a5 | 174 | static inline void copy_kernel_to_fregs(struct fregs_state *fx) |
1361b83a | 175 | { |
43b287b3 IM |
176 | int err = check_insn(frstor %[fx], "=m" (*fx), [fx] "m" (*fx)); |
177 | ||
178 | WARN_ON_FPU(err); | |
e139e955 PA |
179 | } |
180 | ||
c47ada30 | 181 | static inline int copy_user_to_fregs(struct fregs_state __user *fx) |
e139e955 PA |
182 | { |
183 | return user_insn(frstor %[fx], "=m" (*fx), [fx] "m" (*fx)); | |
1361b83a LT |
184 | } |
185 | ||
c6813144 | 186 | static inline void copy_fxregs_to_kernel(struct fpu *fpu) |
1361b83a | 187 | { |
0ca5bd0d | 188 | if (config_enabled(CONFIG_X86_32)) |
7366ed77 | 189 | asm volatile( "fxsave %[fx]" : [fx] "=m" (fpu->state.fxsave)); |
0ca5bd0d | 190 | else if (config_enabled(CONFIG_AS_FXSAVEQ)) |
7366ed77 | 191 | asm volatile("fxsaveq %[fx]" : [fx] "=m" (fpu->state.fxsave)); |
0ca5bd0d SS |
192 | else { |
193 | /* Using "rex64; fxsave %0" is broken because, if the memory | |
194 | * operand uses any extended registers for addressing, a second | |
195 | * REX prefix will be generated (to the assembler, rex64 | |
196 | * followed by semicolon is a separate instruction), and hence | |
197 | * the 64-bitness is lost. | |
198 | * | |
199 | * Using "fxsaveq %0" would be the ideal choice, but is only | |
200 | * supported starting with gas 2.16. | |
201 | * | |
202 | * Using, as a workaround, the properly prefixed form below | |
203 | * isn't accepted by any binutils version so far released, | |
204 | * complaining that the same type of prefix is used twice if | |
205 | * an extended register is needed for addressing (fix submitted | |
206 | * to mainline 2005-11-21). | |
207 | * | |
7366ed77 | 208 | * asm volatile("rex64/fxsave %0" : "=m" (fpu->state.fxsave)); |
0ca5bd0d SS |
209 | * |
210 | * This, however, we can work around by forcing the compiler to | |
211 | * select an addressing mode that doesn't require extended | |
212 | * registers. | |
213 | */ | |
214 | asm volatile( "rex64/fxsave (%[fx])" | |
7366ed77 IM |
215 | : "=m" (fpu->state.fxsave) |
216 | : [fx] "R" (&fpu->state.fxsave)); | |
0ca5bd0d | 217 | } |
1361b83a LT |
218 | } |
219 | ||
fd169b05 IM |
220 | /* These macros all use (%edi)/(%rdi) as the single memory argument. */ |
221 | #define XSAVE ".byte " REX_PREFIX "0x0f,0xae,0x27" | |
222 | #define XSAVEOPT ".byte " REX_PREFIX "0x0f,0xae,0x37" | |
223 | #define XSAVES ".byte " REX_PREFIX "0x0f,0xc7,0x2f" | |
224 | #define XRSTOR ".byte " REX_PREFIX "0x0f,0xae,0x2f" | |
225 | #define XRSTORS ".byte " REX_PREFIX "0x0f,0xc7,0x1f" | |
226 | ||
227 | /* xstate instruction fault handler: */ | |
228 | #define xstate_fault(__err) \ | |
229 | \ | |
230 | ".section .fixup,\"ax\"\n" \ | |
231 | \ | |
87b6559d | 232 | "3: movl $-2,%[_err]\n" \ |
fd169b05 IM |
233 | " jmp 2b\n" \ |
234 | \ | |
235 | ".previous\n" \ | |
236 | \ | |
237 | _ASM_EXTABLE(1b, 3b) \ | |
87b6559d | 238 | : [_err] "=r" (__err) |
fd169b05 IM |
239 | |
240 | /* | |
241 | * This function is called only during boot time when x86 caps are not set | |
242 | * up and alternative can not be used yet. | |
243 | */ | |
8c05f05e | 244 | static inline void copy_xregs_to_kernel_booting(struct xregs_state *xstate) |
fd169b05 IM |
245 | { |
246 | u64 mask = -1; | |
247 | u32 lmask = mask; | |
248 | u32 hmask = mask >> 32; | |
249 | int err = 0; | |
250 | ||
251 | WARN_ON(system_state != SYSTEM_BOOTING); | |
252 | ||
253 | if (boot_cpu_has(X86_FEATURE_XSAVES)) | |
254 | asm volatile("1:"XSAVES"\n\t" | |
255 | "2:\n\t" | |
256 | xstate_fault(err) | |
87b6559d IM |
257 | : "D" (xstate), "m" (*xstate), "a" (lmask), "d" (hmask), "0" (err) |
258 | : "memory"); | |
fd169b05 IM |
259 | else |
260 | asm volatile("1:"XSAVE"\n\t" | |
261 | "2:\n\t" | |
262 | xstate_fault(err) | |
87b6559d IM |
263 | : "D" (xstate), "m" (*xstate), "a" (lmask), "d" (hmask), "0" (err) |
264 | : "memory"); | |
8c05f05e IM |
265 | |
266 | /* We should never fault when copying to a kernel buffer: */ | |
267 | WARN_ON_FPU(err); | |
fd169b05 IM |
268 | } |
269 | ||
270 | /* | |
271 | * This function is called only during boot time when x86 caps are not set | |
272 | * up and alternative can not be used yet. | |
273 | */ | |
d65fcd60 | 274 | static inline void copy_kernel_to_xregs_booting(struct xregs_state *xstate) |
fd169b05 | 275 | { |
d65fcd60 | 276 | u64 mask = -1; |
fd169b05 IM |
277 | u32 lmask = mask; |
278 | u32 hmask = mask >> 32; | |
279 | int err = 0; | |
280 | ||
281 | WARN_ON(system_state != SYSTEM_BOOTING); | |
282 | ||
283 | if (boot_cpu_has(X86_FEATURE_XSAVES)) | |
284 | asm volatile("1:"XRSTORS"\n\t" | |
285 | "2:\n\t" | |
286 | xstate_fault(err) | |
87b6559d IM |
287 | : "D" (xstate), "m" (*xstate), "a" (lmask), "d" (hmask), "0" (err) |
288 | : "memory"); | |
fd169b05 IM |
289 | else |
290 | asm volatile("1:"XRSTOR"\n\t" | |
291 | "2:\n\t" | |
292 | xstate_fault(err) | |
87b6559d IM |
293 | : "D" (xstate), "m" (*xstate), "a" (lmask), "d" (hmask), "0" (err) |
294 | : "memory"); | |
8c05f05e IM |
295 | |
296 | /* We should never fault when copying from a kernel buffer: */ | |
297 | WARN_ON_FPU(err); | |
fd169b05 IM |
298 | } |
299 | ||
300 | /* | |
301 | * Save processor xstate to xsave area. | |
302 | */ | |
8c05f05e | 303 | static inline void copy_xregs_to_kernel(struct xregs_state *xstate) |
fd169b05 IM |
304 | { |
305 | u64 mask = -1; | |
306 | u32 lmask = mask; | |
307 | u32 hmask = mask >> 32; | |
308 | int err = 0; | |
309 | ||
310 | WARN_ON(!alternatives_patched); | |
311 | ||
312 | /* | |
313 | * If xsaves is enabled, xsaves replaces xsaveopt because | |
314 | * it supports compact format and supervisor states in addition to | |
315 | * modified optimization in xsaveopt. | |
316 | * | |
317 | * Otherwise, if xsaveopt is enabled, xsaveopt replaces xsave | |
318 | * because xsaveopt supports modified optimization which is not | |
319 | * supported by xsave. | |
320 | * | |
321 | * If none of xsaves and xsaveopt is enabled, use xsave. | |
322 | */ | |
323 | alternative_input_2( | |
324 | "1:"XSAVE, | |
325 | XSAVEOPT, | |
326 | X86_FEATURE_XSAVEOPT, | |
327 | XSAVES, | |
328 | X86_FEATURE_XSAVES, | |
87dafd41 | 329 | [xstate] "D" (xstate), "a" (lmask), "d" (hmask) : |
fd169b05 IM |
330 | "memory"); |
331 | asm volatile("2:\n\t" | |
332 | xstate_fault(err) | |
685c9616 | 333 | : "0" (err) |
fd169b05 IM |
334 | : "memory"); |
335 | ||
8c05f05e IM |
336 | /* We should never fault when copying to a kernel buffer: */ |
337 | WARN_ON_FPU(err); | |
fd169b05 IM |
338 | } |
339 | ||
340 | /* | |
341 | * Restore processor xstate from xsave area. | |
342 | */ | |
8c05f05e | 343 | static inline void copy_kernel_to_xregs(struct xregs_state *xstate, u64 mask) |
fd169b05 | 344 | { |
fd169b05 IM |
345 | u32 lmask = mask; |
346 | u32 hmask = mask >> 32; | |
685c9616 | 347 | int err = 0; |
fd169b05 IM |
348 | |
349 | /* | |
350 | * Use xrstors to restore context if it is enabled. xrstors supports | |
351 | * compacted format of xsave area which is not supported by xrstor. | |
352 | */ | |
353 | alternative_input( | |
354 | "1: " XRSTOR, | |
355 | XRSTORS, | |
356 | X86_FEATURE_XSAVES, | |
87dafd41 | 357 | "D" (xstate), "m" (*xstate), "a" (lmask), "d" (hmask) |
fd169b05 IM |
358 | : "memory"); |
359 | ||
360 | asm volatile("2:\n" | |
361 | xstate_fault(err) | |
685c9616 | 362 | : "0" (err) |
fd169b05 IM |
363 | : "memory"); |
364 | ||
8c05f05e IM |
365 | /* We should never fault when copying from a kernel buffer: */ |
366 | WARN_ON_FPU(err); | |
fd169b05 IM |
367 | } |
368 | ||
369 | /* | |
370 | * Save xstate to user space xsave area. | |
371 | * | |
372 | * We don't use modified optimization because xrstor/xrstors might track | |
373 | * a different application. | |
374 | * | |
375 | * We don't use compacted format xsave area for | |
376 | * backward compatibility for old applications which don't understand | |
377 | * compacted format of xsave area. | |
378 | */ | |
379 | static inline int copy_xregs_to_user(struct xregs_state __user *buf) | |
380 | { | |
381 | int err; | |
382 | ||
383 | /* | |
384 | * Clear the xsave header first, so that reserved fields are | |
385 | * initialized to zero. | |
386 | */ | |
387 | err = __clear_user(&buf->header, sizeof(buf->header)); | |
388 | if (unlikely(err)) | |
389 | return -EFAULT; | |
390 | ||
391 | __asm__ __volatile__(ASM_STAC "\n" | |
392 | "1:"XSAVE"\n" | |
393 | "2: " ASM_CLAC "\n" | |
394 | xstate_fault(err) | |
685c9616 | 395 | : "D" (buf), "a" (-1), "d" (-1), "0" (err) |
fd169b05 IM |
396 | : "memory"); |
397 | return err; | |
398 | } | |
399 | ||
400 | /* | |
401 | * Restore xstate from user space xsave area. | |
402 | */ | |
403 | static inline int copy_user_to_xregs(struct xregs_state __user *buf, u64 mask) | |
404 | { | |
fd169b05 IM |
405 | struct xregs_state *xstate = ((__force struct xregs_state *)buf); |
406 | u32 lmask = mask; | |
407 | u32 hmask = mask >> 32; | |
685c9616 | 408 | int err = 0; |
fd169b05 IM |
409 | |
410 | __asm__ __volatile__(ASM_STAC "\n" | |
411 | "1:"XRSTOR"\n" | |
412 | "2: " ASM_CLAC "\n" | |
413 | xstate_fault(err) | |
685c9616 | 414 | : "D" (xstate), "a" (lmask), "d" (hmask), "0" (err) |
fd169b05 IM |
415 | : "memory"); /* memory required? */ |
416 | return err; | |
417 | } | |
418 | ||
1361b83a LT |
419 | /* |
420 | * These must be called with preempt disabled. Returns | |
4f836347 IM |
421 | * 'true' if the FPU state is still intact and we can |
422 | * keep registers active. | |
423 | * | |
424 | * The legacy FNSAVE instruction cleared all FPU state | |
425 | * unconditionally, so registers are essentially destroyed. | |
426 | * Modern FPU state can be kept in registers, if there are | |
1bc6b056 | 427 | * no pending FP exceptions. |
1361b83a | 428 | */ |
4f836347 | 429 | static inline int copy_fpregs_to_fpstate(struct fpu *fpu) |
1361b83a | 430 | { |
1bc6b056 | 431 | if (likely(use_xsave())) { |
c6813144 | 432 | copy_xregs_to_kernel(&fpu->state.xsave); |
1bc6b056 IM |
433 | return 1; |
434 | } | |
1361b83a | 435 | |
1bc6b056 | 436 | if (likely(use_fxsr())) { |
c6813144 | 437 | copy_fxregs_to_kernel(fpu); |
1bc6b056 | 438 | return 1; |
1361b83a LT |
439 | } |
440 | ||
441 | /* | |
1bc6b056 IM |
442 | * Legacy FPU register saving, FNSAVE always clears FPU registers, |
443 | * so we have to mark them inactive: | |
1361b83a | 444 | */ |
87dafd41 | 445 | asm volatile("fnsave %[fp]; fwait" : [fp] "=m" (fpu->state.fsave)); |
4f836347 | 446 | |
4f836347 | 447 | return 0; |
1361b83a LT |
448 | } |
449 | ||
003e2e8b | 450 | static inline void __copy_kernel_to_fpregs(union fpregs_state *fpstate) |
1361b83a | 451 | { |
8c05f05e | 452 | if (use_xsave()) { |
003e2e8b | 453 | copy_kernel_to_xregs(&fpstate->xsave, -1); |
8c05f05e IM |
454 | } else { |
455 | if (use_fxsr()) | |
003e2e8b | 456 | copy_kernel_to_fxregs(&fpstate->fxsave); |
8c05f05e | 457 | else |
003e2e8b | 458 | copy_kernel_to_fregs(&fpstate->fsave); |
8c05f05e | 459 | } |
1361b83a LT |
460 | } |
461 | ||
003e2e8b | 462 | static inline void copy_kernel_to_fpregs(union fpregs_state *fpstate) |
1361b83a | 463 | { |
6ca7a8a1 BP |
464 | /* |
465 | * AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception is | |
466 | * pending. Clear the x87 state here by setting it to fixed values. | |
467 | * "m" is a random variable that should be in L1. | |
468 | */ | |
9b13a93d | 469 | if (unlikely(static_cpu_has_bug_safe(X86_BUG_FXSAVE_LEAK))) { |
26bef131 LT |
470 | asm volatile( |
471 | "fnclex\n\t" | |
472 | "emms\n\t" | |
473 | "fildl %P[addr]" /* set F?P to defined value */ | |
003e2e8b | 474 | : : [addr] "m" (fpstate)); |
26bef131 | 475 | } |
1361b83a | 476 | |
003e2e8b | 477 | __copy_kernel_to_fpregs(fpstate); |
1361b83a LT |
478 | } |
479 | ||
87dafd41 | 480 | extern int copy_fpstate_to_sigframe(void __user *buf, void __user *fp, int size); |
b1b64dc3 IM |
481 | |
482 | /* | |
483 | * FPU context switch related helper methods: | |
484 | */ | |
485 | ||
486 | DECLARE_PER_CPU(struct fpu *, fpu_fpregs_owner_ctx); | |
487 | ||
488 | /* | |
489 | * Must be run with preemption disabled: this clears the fpu_fpregs_owner_ctx, | |
490 | * on this CPU. | |
491 | * | |
492 | * This will disable any lazy FPU state restore of the current FPU state, | |
493 | * but if the current thread owns the FPU, it will still be saved by. | |
494 | */ | |
495 | static inline void __cpu_disable_lazy_restore(unsigned int cpu) | |
496 | { | |
497 | per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; | |
498 | } | |
499 | ||
500 | static inline int fpu_want_lazy_restore(struct fpu *fpu, unsigned int cpu) | |
501 | { | |
502 | return fpu == this_cpu_read_stable(fpu_fpregs_owner_ctx) && cpu == fpu->last_cpu; | |
503 | } | |
504 | ||
505 | ||
32b49b3c IM |
506 | /* |
507 | * Wrap lazy FPU TS handling in a 'hw fpregs activation/deactivation' | |
508 | * idiom, which is then paired with the sw-flag (fpregs_active) later on: | |
509 | */ | |
510 | ||
511 | static inline void __fpregs_activate_hw(void) | |
512 | { | |
513 | if (!use_eager_fpu()) | |
514 | clts(); | |
515 | } | |
516 | ||
517 | static inline void __fpregs_deactivate_hw(void) | |
518 | { | |
519 | if (!use_eager_fpu()) | |
520 | stts(); | |
521 | } | |
522 | ||
523 | /* Must be paired with an 'stts' (fpregs_deactivate_hw()) after! */ | |
723c58e4 | 524 | static inline void __fpregs_deactivate(struct fpu *fpu) |
1361b83a | 525 | { |
e97131a8 IM |
526 | WARN_ON_FPU(!fpu->fpregs_active); |
527 | ||
d5cea9b0 | 528 | fpu->fpregs_active = 0; |
36b544dc | 529 | this_cpu_write(fpu_fpregs_owner_ctx, NULL); |
1361b83a LT |
530 | } |
531 | ||
32b49b3c | 532 | /* Must be paired with a 'clts' (fpregs_activate_hw()) before! */ |
dfaea4e6 | 533 | static inline void __fpregs_activate(struct fpu *fpu) |
1361b83a | 534 | { |
e97131a8 IM |
535 | WARN_ON_FPU(fpu->fpregs_active); |
536 | ||
d5cea9b0 | 537 | fpu->fpregs_active = 1; |
c0311f63 | 538 | this_cpu_write(fpu_fpregs_owner_ctx, fpu); |
1361b83a LT |
539 | } |
540 | ||
952f07ec IM |
541 | /* |
542 | * The question "does this thread have fpu access?" | |
543 | * is slightly racy, since preemption could come in | |
544 | * and revoke it immediately after the test. | |
545 | * | |
546 | * However, even in that very unlikely scenario, | |
547 | * we can just assume we have FPU access - typically | |
548 | * to save the FP state - we'll just take a #NM | |
549 | * fault and get the FPU access back. | |
550 | */ | |
3c6dffa9 | 551 | static inline int fpregs_active(void) |
952f07ec IM |
552 | { |
553 | return current->thread.fpu.fpregs_active; | |
554 | } | |
555 | ||
1361b83a LT |
556 | /* |
557 | * Encapsulate the CR0.TS handling together with the | |
558 | * software flag. | |
559 | * | |
560 | * These generally need preemption protection to work, | |
561 | * do try to avoid using these on their own. | |
562 | */ | |
66af8e27 | 563 | static inline void fpregs_activate(struct fpu *fpu) |
1361b83a | 564 | { |
32b49b3c | 565 | __fpregs_activate_hw(); |
66af8e27 | 566 | __fpregs_activate(fpu); |
1361b83a LT |
567 | } |
568 | ||
66af8e27 | 569 | static inline void fpregs_deactivate(struct fpu *fpu) |
1361b83a | 570 | { |
66af8e27 | 571 | __fpregs_deactivate(fpu); |
32b49b3c | 572 | __fpregs_deactivate_hw(); |
1361b83a LT |
573 | } |
574 | ||
575 | /* | |
576 | * FPU state switching for scheduling. | |
577 | * | |
578 | * This is a two-stage process: | |
579 | * | |
580 | * - switch_fpu_prepare() saves the old state and | |
581 | * sets the new state of the CR0.TS bit. This is | |
582 | * done within the context of the old process. | |
583 | * | |
584 | * - switch_fpu_finish() restores the new state as | |
585 | * necessary. | |
586 | */ | |
587 | typedef struct { int preload; } fpu_switch_t; | |
588 | ||
cb8818b6 IM |
589 | static inline fpu_switch_t |
590 | switch_fpu_prepare(struct fpu *old_fpu, struct fpu *new_fpu, int cpu) | |
1361b83a LT |
591 | { |
592 | fpu_switch_t fpu; | |
593 | ||
304bceda SS |
594 | /* |
595 | * If the task has used the math, pre-load the FPU on xsave processors | |
596 | * or if the past 5 consecutive context-switches used math. | |
597 | */ | |
c5bedc68 | 598 | fpu.preload = new_fpu->fpstate_active && |
cb8818b6 | 599 | (use_eager_fpu() || new_fpu->counter > 5); |
1361ef29 | 600 | |
d5cea9b0 | 601 | if (old_fpu->fpregs_active) { |
4f836347 | 602 | if (!copy_fpregs_to_fpstate(old_fpu)) |
cb8818b6 | 603 | old_fpu->last_cpu = -1; |
1361ef29 | 604 | else |
cb8818b6 | 605 | old_fpu->last_cpu = cpu; |
1361ef29 | 606 | |
36b544dc | 607 | /* But leave fpu_fpregs_owner_ctx! */ |
d5cea9b0 | 608 | old_fpu->fpregs_active = 0; |
1361b83a LT |
609 | |
610 | /* Don't change CR0.TS if we just switch! */ | |
611 | if (fpu.preload) { | |
cb8818b6 | 612 | new_fpu->counter++; |
dfaea4e6 | 613 | __fpregs_activate(new_fpu); |
7366ed77 | 614 | prefetch(&new_fpu->state); |
32b49b3c IM |
615 | } else { |
616 | __fpregs_deactivate_hw(); | |
617 | } | |
1361b83a | 618 | } else { |
cb8818b6 IM |
619 | old_fpu->counter = 0; |
620 | old_fpu->last_cpu = -1; | |
1361b83a | 621 | if (fpu.preload) { |
cb8818b6 | 622 | new_fpu->counter++; |
66ddc2cb | 623 | if (fpu_want_lazy_restore(new_fpu, cpu)) |
1361b83a LT |
624 | fpu.preload = 0; |
625 | else | |
7366ed77 | 626 | prefetch(&new_fpu->state); |
232f62cd | 627 | fpregs_activate(new_fpu); |
1361b83a LT |
628 | } |
629 | } | |
630 | return fpu; | |
631 | } | |
632 | ||
b1b64dc3 IM |
633 | /* |
634 | * Misc helper functions: | |
635 | */ | |
636 | ||
1361b83a LT |
637 | /* |
638 | * By the time this gets called, we've already cleared CR0.TS and | |
639 | * given the process the FPU if we are going to preload the FPU | |
640 | * state - all we need to do is to conditionally restore the register | |
641 | * state itself. | |
642 | */ | |
384a23f9 | 643 | static inline void switch_fpu_finish(struct fpu *new_fpu, fpu_switch_t fpu_switch) |
1361b83a | 644 | { |
9ccc27a5 | 645 | if (fpu_switch.preload) |
003e2e8b | 646 | copy_kernel_to_fpregs(&new_fpu->state); |
1361b83a LT |
647 | } |
648 | ||
1361b83a | 649 | /* |
fb14b4ea | 650 | * Needs to be preemption-safe. |
1361b83a | 651 | * |
377ffbcc | 652 | * NOTE! user_fpu_begin() must be used only immediately before restoring |
fb14b4ea ON |
653 | * the save state. It does not do any saving/restoring on its own. In |
654 | * lazy FPU mode, it is just an optimization to avoid a #NM exception, | |
655 | * the task can lose the FPU right after preempt_enable(). | |
1361b83a | 656 | */ |
1361b83a LT |
657 | static inline void user_fpu_begin(void) |
658 | { | |
4540d3fa IM |
659 | struct fpu *fpu = ¤t->thread.fpu; |
660 | ||
1361b83a | 661 | preempt_disable(); |
3c6dffa9 | 662 | if (!fpregs_active()) |
232f62cd | 663 | fpregs_activate(fpu); |
1361b83a LT |
664 | preempt_enable(); |
665 | } | |
666 | ||
b1b64dc3 IM |
667 | /* |
668 | * MXCSR and XCR definitions: | |
669 | */ | |
670 | ||
671 | extern unsigned int mxcsr_feature_mask; | |
672 | ||
673 | #define XCR_XFEATURE_ENABLED_MASK 0x00000000 | |
674 | ||
675 | static inline u64 xgetbv(u32 index) | |
676 | { | |
677 | u32 eax, edx; | |
678 | ||
679 | asm volatile(".byte 0x0f,0x01,0xd0" /* xgetbv */ | |
680 | : "=a" (eax), "=d" (edx) | |
681 | : "c" (index)); | |
682 | return eax + ((u64)edx << 32); | |
683 | } | |
684 | ||
685 | static inline void xsetbv(u32 index, u64 value) | |
686 | { | |
687 | u32 eax = value; | |
688 | u32 edx = value >> 32; | |
689 | ||
690 | asm volatile(".byte 0x0f,0x01,0xd1" /* xsetbv */ | |
691 | : : "a" (eax), "d" (edx), "c" (index)); | |
692 | } | |
693 | ||
78f7f1e5 | 694 | #endif /* _ASM_X86_FPU_INTERNAL_H */ |