Commit | Line | Data |
---|---|---|
1361b83a LT |
1 | /* |
2 | * Copyright (C) 1994 Linus Torvalds | |
3 | * | |
4 | * Pentium III FXSR, SSE support | |
5 | * General FPU state handling cleanups | |
6 | * Gareth Hughes <gareth@valinux.com>, May 2000 | |
7 | * x86-64 work by Andi Kleen 2002 | |
8 | */ | |
9 | ||
78f7f1e5 IM |
10 | #ifndef _ASM_X86_FPU_INTERNAL_H |
11 | #define _ASM_X86_FPU_INTERNAL_H | |
1361b83a | 12 | |
050902c0 | 13 | #include <linux/compat.h> |
952f07ec | 14 | #include <linux/sched.h> |
1361b83a | 15 | #include <linux/slab.h> |
f89e32e0 | 16 | |
1361b83a | 17 | #include <asm/user.h> |
df6b35f4 | 18 | #include <asm/fpu/api.h> |
669ebabb | 19 | #include <asm/fpu/xstate.h> |
1361b83a | 20 | |
df639752 IM |
21 | #define MXCSR_DEFAULT 0x1f80 |
22 | ||
72a671ce | 23 | extern unsigned int mxcsr_feature_mask; |
1361b83a | 24 | |
c47ada30 | 25 | extern union fpregs_state init_fpstate; |
6f575023 | 26 | |
04c8e01d | 27 | extern void fpu__init_cpu(void); |
55cc4678 IM |
28 | extern void fpu__init_system_xstate(void); |
29 | extern void fpu__init_cpu_xstate(void); | |
dd863880 | 30 | extern void fpu__init_system(struct cpuinfo_x86 *c); |
55cc4678 | 31 | |
c47ada30 | 32 | extern void fpstate_init(union fpregs_state *state); |
0aba6978 | 33 | #ifdef CONFIG_MATH_EMULATION |
c47ada30 | 34 | extern void fpstate_init_soft(struct swregs_state *soft); |
0aba6978 | 35 | #else |
c47ada30 | 36 | static inline void fpstate_init_soft(struct swregs_state *soft) {} |
0aba6978 | 37 | #endif |
c47ada30 | 38 | static inline void fpstate_init_fxstate(struct fxregs_state *fx) |
0aba6978 IM |
39 | { |
40 | fx->cwd = 0x37f; | |
41 | fx->mxcsr = MXCSR_DEFAULT; | |
42 | } | |
952f07ec | 43 | |
e1cebad4 IM |
44 | extern int dump_fpu(struct pt_regs *, struct user_i387_struct *); |
45 | extern int fpu__exception_code(struct fpu *fpu, int trap_nr); | |
6ffc152e IM |
46 | |
47 | /* | |
48 | * High level FPU state handling functions: | |
49 | */ | |
0c306bcf IM |
50 | extern void fpu__activate_curr(struct fpu *fpu); |
51 | extern void fpu__activate_stopped(struct fpu *fpu); | |
6ffc152e | 52 | extern void fpu__save(struct fpu *fpu); |
e1884d69 | 53 | extern void fpu__restore(struct fpu *fpu); |
82c0e45e | 54 | extern int fpu__restore_sig(void __user *buf, int ia32_frame); |
6ffc152e IM |
55 | extern void fpu__drop(struct fpu *fpu); |
56 | extern int fpu__copy(struct fpu *dst_fpu, struct fpu *src_fpu); | |
04c8e01d | 57 | extern void fpu__clear(struct fpu *fpu); |
6ffc152e | 58 | |
952f07ec IM |
59 | extern void fpu__init_check_bugs(void); |
60 | extern void fpu__resume_cpu(void); | |
61 | ||
e97131a8 IM |
62 | /* |
63 | * Debugging facility: | |
64 | */ | |
65 | #ifdef CONFIG_X86_DEBUG_FPU | |
66 | # define WARN_ON_FPU(x) WARN_ON_ONCE(x) | |
67 | #else | |
68 | # define WARN_ON_FPU(x) ({ 0; }) | |
69 | #endif | |
70 | ||
36b544dc | 71 | DECLARE_PER_CPU(struct fpu *, fpu_fpregs_owner_ctx); |
1361b83a | 72 | |
1c927eea | 73 | /* |
36b544dc | 74 | * Must be run with preemption disabled: this clears the fpu_fpregs_owner_ctx, |
1c927eea RR |
75 | * on this CPU. |
76 | * | |
77 | * This will disable any lazy FPU state restore of the current FPU state, | |
78 | * but if the current thread owns the FPU, it will still be saved by. | |
79 | */ | |
80 | static inline void __cpu_disable_lazy_restore(unsigned int cpu) | |
81 | { | |
36b544dc | 82 | per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; |
1c927eea RR |
83 | } |
84 | ||
66ddc2cb | 85 | static inline int fpu_want_lazy_restore(struct fpu *fpu, unsigned int cpu) |
1c927eea | 86 | { |
66ddc2cb | 87 | return fpu == this_cpu_read_stable(fpu_fpregs_owner_ctx) && cpu == fpu->last_cpu; |
1c927eea RR |
88 | } |
89 | ||
1361b83a LT |
90 | #define X87_FSW_ES (1 << 7) /* Exception Summary */ |
91 | ||
5d2bd700 SS |
92 | static __always_inline __pure bool use_eager_fpu(void) |
93 | { | |
c6b40691 | 94 | return static_cpu_has_safe(X86_FEATURE_EAGER_FPU); |
5d2bd700 SS |
95 | } |
96 | ||
1361b83a LT |
97 | static __always_inline __pure bool use_xsaveopt(void) |
98 | { | |
c6b40691 | 99 | return static_cpu_has_safe(X86_FEATURE_XSAVEOPT); |
1361b83a LT |
100 | } |
101 | ||
102 | static __always_inline __pure bool use_xsave(void) | |
103 | { | |
c6b40691 | 104 | return static_cpu_has_safe(X86_FEATURE_XSAVE); |
1361b83a LT |
105 | } |
106 | ||
107 | static __always_inline __pure bool use_fxsr(void) | |
108 | { | |
c6b40691 | 109 | return static_cpu_has_safe(X86_FEATURE_FXSR); |
1361b83a LT |
110 | } |
111 | ||
36e49e7f | 112 | extern void fpstate_sanitize_xstate(struct fpu *fpu); |
1361b83a | 113 | |
49b8c695 PA |
114 | #define user_insn(insn, output, input...) \ |
115 | ({ \ | |
116 | int err; \ | |
117 | asm volatile(ASM_STAC "\n" \ | |
118 | "1:" #insn "\n\t" \ | |
119 | "2: " ASM_CLAC "\n" \ | |
120 | ".section .fixup,\"ax\"\n" \ | |
121 | "3: movl $-1,%[err]\n" \ | |
122 | " jmp 2b\n" \ | |
123 | ".previous\n" \ | |
124 | _ASM_EXTABLE(1b, 3b) \ | |
125 | : [err] "=r" (err), output \ | |
126 | : "0"(0), input); \ | |
127 | err; \ | |
128 | }) | |
129 | ||
0ca5bd0d SS |
130 | #define check_insn(insn, output, input...) \ |
131 | ({ \ | |
132 | int err; \ | |
133 | asm volatile("1:" #insn "\n\t" \ | |
134 | "2:\n" \ | |
135 | ".section .fixup,\"ax\"\n" \ | |
136 | "3: movl $-1,%[err]\n" \ | |
137 | " jmp 2b\n" \ | |
138 | ".previous\n" \ | |
139 | _ASM_EXTABLE(1b, 3b) \ | |
140 | : [err] "=r" (err), output \ | |
141 | : "0"(0), input); \ | |
142 | err; \ | |
143 | }) | |
144 | ||
c47ada30 | 145 | static inline int copy_fregs_to_user(struct fregs_state __user *fx) |
1361b83a | 146 | { |
49b8c695 | 147 | return user_insn(fnsave %[fx]; fwait, [fx] "=m" (*fx), "m" (*fx)); |
1361b83a LT |
148 | } |
149 | ||
c47ada30 | 150 | static inline int copy_fxregs_to_user(struct fxregs_state __user *fx) |
1361b83a | 151 | { |
0ca5bd0d | 152 | if (config_enabled(CONFIG_X86_32)) |
49b8c695 | 153 | return user_insn(fxsave %[fx], [fx] "=m" (*fx), "m" (*fx)); |
0ca5bd0d | 154 | else if (config_enabled(CONFIG_AS_FXSAVEQ)) |
49b8c695 | 155 | return user_insn(fxsaveq %[fx], [fx] "=m" (*fx), "m" (*fx)); |
1361b83a | 156 | |
c6813144 | 157 | /* See comment in copy_fxregs_to_kernel() below. */ |
49b8c695 | 158 | return user_insn(rex64/fxsave (%[fx]), "=m" (*fx), [fx] "R" (fx)); |
1361b83a LT |
159 | } |
160 | ||
c47ada30 | 161 | static inline int copy_kernel_to_fxregs(struct fxregs_state *fx) |
1361b83a | 162 | { |
0ca5bd0d SS |
163 | if (config_enabled(CONFIG_X86_32)) |
164 | return check_insn(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx)); | |
165 | else if (config_enabled(CONFIG_AS_FXSAVEQ)) | |
166 | return check_insn(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx)); | |
1361b83a | 167 | |
c6813144 | 168 | /* See comment in copy_fxregs_to_kernel() below. */ |
0ca5bd0d SS |
169 | return check_insn(rex64/fxrstor (%[fx]), "=m" (*fx), [fx] "R" (fx), |
170 | "m" (*fx)); | |
1361b83a LT |
171 | } |
172 | ||
c47ada30 | 173 | static inline int copy_user_to_fxregs(struct fxregs_state __user *fx) |
e139e955 PA |
174 | { |
175 | if (config_enabled(CONFIG_X86_32)) | |
176 | return user_insn(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx)); | |
177 | else if (config_enabled(CONFIG_AS_FXSAVEQ)) | |
178 | return user_insn(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx)); | |
179 | ||
c6813144 | 180 | /* See comment in copy_fxregs_to_kernel() below. */ |
e139e955 PA |
181 | return user_insn(rex64/fxrstor (%[fx]), "=m" (*fx), [fx] "R" (fx), |
182 | "m" (*fx)); | |
183 | } | |
184 | ||
c47ada30 | 185 | static inline int copy_kernel_to_fregs(struct fregs_state *fx) |
1361b83a | 186 | { |
0ca5bd0d | 187 | return check_insn(frstor %[fx], "=m" (*fx), [fx] "m" (*fx)); |
e139e955 PA |
188 | } |
189 | ||
c47ada30 | 190 | static inline int copy_user_to_fregs(struct fregs_state __user *fx) |
e139e955 PA |
191 | { |
192 | return user_insn(frstor %[fx], "=m" (*fx), [fx] "m" (*fx)); | |
1361b83a LT |
193 | } |
194 | ||
c6813144 | 195 | static inline void copy_fxregs_to_kernel(struct fpu *fpu) |
1361b83a | 196 | { |
0ca5bd0d | 197 | if (config_enabled(CONFIG_X86_32)) |
7366ed77 | 198 | asm volatile( "fxsave %[fx]" : [fx] "=m" (fpu->state.fxsave)); |
0ca5bd0d | 199 | else if (config_enabled(CONFIG_AS_FXSAVEQ)) |
7366ed77 | 200 | asm volatile("fxsaveq %[fx]" : [fx] "=m" (fpu->state.fxsave)); |
0ca5bd0d SS |
201 | else { |
202 | /* Using "rex64; fxsave %0" is broken because, if the memory | |
203 | * operand uses any extended registers for addressing, a second | |
204 | * REX prefix will be generated (to the assembler, rex64 | |
205 | * followed by semicolon is a separate instruction), and hence | |
206 | * the 64-bitness is lost. | |
207 | * | |
208 | * Using "fxsaveq %0" would be the ideal choice, but is only | |
209 | * supported starting with gas 2.16. | |
210 | * | |
211 | * Using, as a workaround, the properly prefixed form below | |
212 | * isn't accepted by any binutils version so far released, | |
213 | * complaining that the same type of prefix is used twice if | |
214 | * an extended register is needed for addressing (fix submitted | |
215 | * to mainline 2005-11-21). | |
216 | * | |
7366ed77 | 217 | * asm volatile("rex64/fxsave %0" : "=m" (fpu->state.fxsave)); |
0ca5bd0d SS |
218 | * |
219 | * This, however, we can work around by forcing the compiler to | |
220 | * select an addressing mode that doesn't require extended | |
221 | * registers. | |
222 | */ | |
223 | asm volatile( "rex64/fxsave (%[fx])" | |
7366ed77 IM |
224 | : "=m" (fpu->state.fxsave) |
225 | : [fx] "R" (&fpu->state.fxsave)); | |
0ca5bd0d | 226 | } |
1361b83a LT |
227 | } |
228 | ||
1361b83a LT |
229 | /* |
230 | * These must be called with preempt disabled. Returns | |
4f836347 IM |
231 | * 'true' if the FPU state is still intact and we can |
232 | * keep registers active. | |
233 | * | |
234 | * The legacy FNSAVE instruction cleared all FPU state | |
235 | * unconditionally, so registers are essentially destroyed. | |
236 | * Modern FPU state can be kept in registers, if there are | |
1bc6b056 | 237 | * no pending FP exceptions. |
1361b83a | 238 | */ |
4f836347 | 239 | static inline int copy_fpregs_to_fpstate(struct fpu *fpu) |
1361b83a | 240 | { |
1bc6b056 | 241 | if (likely(use_xsave())) { |
c6813144 | 242 | copy_xregs_to_kernel(&fpu->state.xsave); |
1bc6b056 IM |
243 | return 1; |
244 | } | |
1361b83a | 245 | |
1bc6b056 | 246 | if (likely(use_fxsr())) { |
c6813144 | 247 | copy_fxregs_to_kernel(fpu); |
1bc6b056 | 248 | return 1; |
1361b83a LT |
249 | } |
250 | ||
251 | /* | |
1bc6b056 IM |
252 | * Legacy FPU register saving, FNSAVE always clears FPU registers, |
253 | * so we have to mark them inactive: | |
1361b83a | 254 | */ |
7366ed77 | 255 | asm volatile("fnsave %[fx]; fwait" : [fx] "=m" (fpu->state.fsave)); |
4f836347 | 256 | |
4f836347 | 257 | return 0; |
1361b83a LT |
258 | } |
259 | ||
0e75c54f | 260 | static inline int __copy_fpstate_to_fpregs(struct fpu *fpu) |
1361b83a LT |
261 | { |
262 | if (use_xsave()) | |
c6813144 | 263 | return copy_kernel_to_xregs(&fpu->state.xsave, -1); |
0ca5bd0d | 264 | else if (use_fxsr()) |
c6813144 | 265 | return copy_kernel_to_fxregs(&fpu->state.fxsave); |
1361b83a | 266 | else |
c6813144 | 267 | return copy_kernel_to_fregs(&fpu->state.fsave); |
1361b83a LT |
268 | } |
269 | ||
0e75c54f | 270 | static inline int copy_fpstate_to_fpregs(struct fpu *fpu) |
1361b83a | 271 | { |
6ca7a8a1 BP |
272 | /* |
273 | * AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception is | |
274 | * pending. Clear the x87 state here by setting it to fixed values. | |
275 | * "m" is a random variable that should be in L1. | |
276 | */ | |
9b13a93d | 277 | if (unlikely(static_cpu_has_bug_safe(X86_BUG_FXSAVE_LEAK))) { |
26bef131 LT |
278 | asm volatile( |
279 | "fnclex\n\t" | |
280 | "emms\n\t" | |
281 | "fildl %P[addr]" /* set F?P to defined value */ | |
d5cea9b0 | 282 | : : [addr] "m" (fpu->fpregs_active)); |
26bef131 | 283 | } |
1361b83a | 284 | |
0e75c54f | 285 | return __copy_fpstate_to_fpregs(fpu); |
1361b83a LT |
286 | } |
287 | ||
32b49b3c IM |
288 | /* |
289 | * Wrap lazy FPU TS handling in a 'hw fpregs activation/deactivation' | |
290 | * idiom, which is then paired with the sw-flag (fpregs_active) later on: | |
291 | */ | |
292 | ||
293 | static inline void __fpregs_activate_hw(void) | |
294 | { | |
295 | if (!use_eager_fpu()) | |
296 | clts(); | |
297 | } | |
298 | ||
299 | static inline void __fpregs_deactivate_hw(void) | |
300 | { | |
301 | if (!use_eager_fpu()) | |
302 | stts(); | |
303 | } | |
304 | ||
305 | /* Must be paired with an 'stts' (fpregs_deactivate_hw()) after! */ | |
723c58e4 | 306 | static inline void __fpregs_deactivate(struct fpu *fpu) |
1361b83a | 307 | { |
e97131a8 IM |
308 | WARN_ON_FPU(!fpu->fpregs_active); |
309 | ||
d5cea9b0 | 310 | fpu->fpregs_active = 0; |
36b544dc | 311 | this_cpu_write(fpu_fpregs_owner_ctx, NULL); |
1361b83a LT |
312 | } |
313 | ||
32b49b3c | 314 | /* Must be paired with a 'clts' (fpregs_activate_hw()) before! */ |
dfaea4e6 | 315 | static inline void __fpregs_activate(struct fpu *fpu) |
1361b83a | 316 | { |
e97131a8 IM |
317 | WARN_ON_FPU(fpu->fpregs_active); |
318 | ||
d5cea9b0 | 319 | fpu->fpregs_active = 1; |
c0311f63 | 320 | this_cpu_write(fpu_fpregs_owner_ctx, fpu); |
1361b83a LT |
321 | } |
322 | ||
952f07ec IM |
323 | /* |
324 | * The question "does this thread have fpu access?" | |
325 | * is slightly racy, since preemption could come in | |
326 | * and revoke it immediately after the test. | |
327 | * | |
328 | * However, even in that very unlikely scenario, | |
329 | * we can just assume we have FPU access - typically | |
330 | * to save the FP state - we'll just take a #NM | |
331 | * fault and get the FPU access back. | |
332 | */ | |
3c6dffa9 | 333 | static inline int fpregs_active(void) |
952f07ec IM |
334 | { |
335 | return current->thread.fpu.fpregs_active; | |
336 | } | |
337 | ||
1361b83a LT |
338 | /* |
339 | * Encapsulate the CR0.TS handling together with the | |
340 | * software flag. | |
341 | * | |
342 | * These generally need preemption protection to work, | |
343 | * do try to avoid using these on their own. | |
344 | */ | |
66af8e27 | 345 | static inline void fpregs_activate(struct fpu *fpu) |
1361b83a | 346 | { |
32b49b3c | 347 | __fpregs_activate_hw(); |
66af8e27 | 348 | __fpregs_activate(fpu); |
1361b83a LT |
349 | } |
350 | ||
66af8e27 | 351 | static inline void fpregs_deactivate(struct fpu *fpu) |
1361b83a | 352 | { |
66af8e27 | 353 | __fpregs_deactivate(fpu); |
32b49b3c | 354 | __fpregs_deactivate_hw(); |
1361b83a LT |
355 | } |
356 | ||
befc61ad IM |
357 | /* |
358 | * Definitions for the eXtended Control Register instructions | |
359 | */ | |
360 | ||
361 | #define XCR_XFEATURE_ENABLED_MASK 0x00000000 | |
362 | ||
363 | static inline u64 xgetbv(u32 index) | |
364 | { | |
365 | u32 eax, edx; | |
366 | ||
367 | asm volatile(".byte 0x0f,0x01,0xd0" /* xgetbv */ | |
368 | : "=a" (eax), "=d" (edx) | |
369 | : "c" (index)); | |
370 | return eax + ((u64)edx << 32); | |
371 | } | |
372 | ||
373 | static inline void xsetbv(u32 index, u64 value) | |
374 | { | |
375 | u32 eax = value; | |
376 | u32 edx = value >> 32; | |
377 | ||
378 | asm volatile(".byte 0x0f,0x01,0xd1" /* xsetbv */ | |
379 | : : "a" (eax), "d" (edx), "c" (index)); | |
380 | } | |
381 | ||
1361b83a LT |
382 | /* |
383 | * FPU state switching for scheduling. | |
384 | * | |
385 | * This is a two-stage process: | |
386 | * | |
387 | * - switch_fpu_prepare() saves the old state and | |
388 | * sets the new state of the CR0.TS bit. This is | |
389 | * done within the context of the old process. | |
390 | * | |
391 | * - switch_fpu_finish() restores the new state as | |
392 | * necessary. | |
393 | */ | |
394 | typedef struct { int preload; } fpu_switch_t; | |
395 | ||
cb8818b6 IM |
396 | static inline fpu_switch_t |
397 | switch_fpu_prepare(struct fpu *old_fpu, struct fpu *new_fpu, int cpu) | |
1361b83a LT |
398 | { |
399 | fpu_switch_t fpu; | |
400 | ||
304bceda SS |
401 | /* |
402 | * If the task has used the math, pre-load the FPU on xsave processors | |
403 | * or if the past 5 consecutive context-switches used math. | |
404 | */ | |
c5bedc68 | 405 | fpu.preload = new_fpu->fpstate_active && |
cb8818b6 | 406 | (use_eager_fpu() || new_fpu->counter > 5); |
1361ef29 | 407 | |
d5cea9b0 | 408 | if (old_fpu->fpregs_active) { |
4f836347 | 409 | if (!copy_fpregs_to_fpstate(old_fpu)) |
cb8818b6 | 410 | old_fpu->last_cpu = -1; |
1361ef29 | 411 | else |
cb8818b6 | 412 | old_fpu->last_cpu = cpu; |
1361ef29 | 413 | |
36b544dc | 414 | /* But leave fpu_fpregs_owner_ctx! */ |
d5cea9b0 | 415 | old_fpu->fpregs_active = 0; |
1361b83a LT |
416 | |
417 | /* Don't change CR0.TS if we just switch! */ | |
418 | if (fpu.preload) { | |
cb8818b6 | 419 | new_fpu->counter++; |
dfaea4e6 | 420 | __fpregs_activate(new_fpu); |
7366ed77 | 421 | prefetch(&new_fpu->state); |
32b49b3c IM |
422 | } else { |
423 | __fpregs_deactivate_hw(); | |
424 | } | |
1361b83a | 425 | } else { |
cb8818b6 IM |
426 | old_fpu->counter = 0; |
427 | old_fpu->last_cpu = -1; | |
1361b83a | 428 | if (fpu.preload) { |
cb8818b6 | 429 | new_fpu->counter++; |
66ddc2cb | 430 | if (fpu_want_lazy_restore(new_fpu, cpu)) |
1361b83a LT |
431 | fpu.preload = 0; |
432 | else | |
7366ed77 | 433 | prefetch(&new_fpu->state); |
232f62cd | 434 | fpregs_activate(new_fpu); |
1361b83a LT |
435 | } |
436 | } | |
437 | return fpu; | |
438 | } | |
439 | ||
440 | /* | |
441 | * By the time this gets called, we've already cleared CR0.TS and | |
442 | * given the process the FPU if we are going to preload the FPU | |
443 | * state - all we need to do is to conditionally restore the register | |
444 | * state itself. | |
445 | */ | |
384a23f9 | 446 | static inline void switch_fpu_finish(struct fpu *new_fpu, fpu_switch_t fpu_switch) |
1361b83a | 447 | { |
384a23f9 | 448 | if (fpu_switch.preload) { |
e97131a8 IM |
449 | if (unlikely(copy_fpstate_to_fpregs(new_fpu))) { |
450 | WARN_ON_FPU(1); | |
fbce7782 | 451 | fpu__clear(new_fpu); |
e97131a8 | 452 | } |
1361b83a LT |
453 | } |
454 | } | |
455 | ||
456 | /* | |
457 | * Signal frame handlers... | |
458 | */ | |
c8e14041 | 459 | extern int copy_fpstate_to_sigframe(void __user *buf, void __user *fx, int size); |
1361b83a LT |
460 | |
461 | /* | |
fb14b4ea | 462 | * Needs to be preemption-safe. |
1361b83a | 463 | * |
377ffbcc | 464 | * NOTE! user_fpu_begin() must be used only immediately before restoring |
fb14b4ea ON |
465 | * the save state. It does not do any saving/restoring on its own. In |
466 | * lazy FPU mode, it is just an optimization to avoid a #NM exception, | |
467 | * the task can lose the FPU right after preempt_enable(). | |
1361b83a | 468 | */ |
1361b83a LT |
469 | static inline void user_fpu_begin(void) |
470 | { | |
4540d3fa IM |
471 | struct fpu *fpu = ¤t->thread.fpu; |
472 | ||
1361b83a | 473 | preempt_disable(); |
3c6dffa9 | 474 | if (!fpregs_active()) |
232f62cd | 475 | fpregs_activate(fpu); |
1361b83a LT |
476 | preempt_enable(); |
477 | } | |
478 | ||
78f7f1e5 | 479 | #endif /* _ASM_X86_FPU_INTERNAL_H */ |