[deliverable/linux.git] / arch / x86 / include / asm / fpu-internal.h

/*
 * Copyright (C) 1994 Linus Torvalds
 *
 * Pentium III FXSR, SSE support
 * General FPU state handling cleanups
 *	Gareth Hughes <gareth@valinux.com>, May 2000
 * x86-64 work by Andi Kleen 2002
 */

#ifndef _FPU_INTERNAL_H
#define _FPU_INTERNAL_H

#include <linux/kernel_stat.h>
#include <linux/regset.h>
#include <linux/compat.h>
#include <linux/slab.h>
#include <asm/asm.h>
#include <asm/cpufeature.h>
#include <asm/processor.h>
#include <asm/sigcontext.h>
#include <asm/user.h>
#include <asm/uaccess.h>
#include <asm/xsave.h>

#ifdef CONFIG_X86_64
# include <asm/sigcontext32.h>
# include <asm/user32.h>
int ia32_setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
			compat_sigset_t *set, struct pt_regs *regs);
int ia32_setup_frame(int sig, struct k_sigaction *ka,
		     compat_sigset_t *set, struct pt_regs *regs);
#else
# define user_i387_ia32_struct	user_i387_struct
# define user32_fxsr_struct	user_fxsr_struct
# define ia32_setup_frame	__setup_frame
# define ia32_setup_rt_frame	__setup_rt_frame
#endif

extern unsigned int mxcsr_feature_mask;
extern void fpu_init(void);
extern void eager_fpu_init(void);

DECLARE_PER_CPU(struct task_struct *, fpu_owner_task);

extern void convert_from_fxsr(struct user_i387_ia32_struct *env,
			      struct task_struct *tsk);
extern void convert_to_fxsr(struct task_struct *tsk,
			    const struct user_i387_ia32_struct *env);

extern user_regset_active_fn fpregs_active, xfpregs_active;
extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get,
				xstateregs_get;
extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set,
				 xstateregs_set;

/*
 * xstateregs_active == fpregs_active. Please refer to the comment
 * at the definition of fpregs_active.
 */
#define xstateregs_active	fpregs_active

#ifdef CONFIG_MATH_EMULATION
# define HAVE_HWFP		(boot_cpu_data.hard_math)
extern void finit_soft_fpu(struct i387_soft_struct *soft);
#else
# define HAVE_HWFP		1
static inline void finit_soft_fpu(struct i387_soft_struct *soft) {}
#endif

static inline int is_ia32_compat_frame(void)
{
	return config_enabled(CONFIG_IA32_EMULATION) &&
	       test_thread_flag(TIF_IA32);
}

static inline int is_ia32_frame(void)
{
	return config_enabled(CONFIG_X86_32) || is_ia32_compat_frame();
}

static inline int is_x32_frame(void)
{
	return config_enabled(CONFIG_X86_X32_ABI) && test_thread_flag(TIF_X32);
}

#define X87_FSW_ES (1 << 7)	/* Exception Summary */

static __always_inline __pure bool use_eager_fpu(void)
{
	return static_cpu_has(X86_FEATURE_EAGER_FPU);
}

static __always_inline __pure bool use_xsaveopt(void)
{
	return static_cpu_has(X86_FEATURE_XSAVEOPT);
}

static __always_inline __pure bool use_xsave(void)
{
	return static_cpu_has(X86_FEATURE_XSAVE);
}

static __always_inline __pure bool use_fxsr(void)
{
        return static_cpu_has(X86_FEATURE_FXSR);
}

static inline void fx_finit(struct i387_fxsave_struct *fx)
{
	memset(fx, 0, xstate_size);
	fx->cwd = 0x37f;
	fx->mxcsr = MXCSR_DEFAULT;
}

extern void __sanitize_i387_state(struct task_struct *);

static inline void sanitize_i387_state(struct task_struct *tsk)
{
	if (!use_xsaveopt())
		return;
	__sanitize_i387_state(tsk);
}

#define check_insn(insn, output, input...)				\
({									\
	int err;							\
	asm volatile("1:" #insn "\n\t"					\
		     "2:\n"						\
		     ".section .fixup,\"ax\"\n"				\
		     "3:  movl $-1,%[err]\n"				\
		     "    jmp  2b\n"					\
		     ".previous\n"					\
		     _ASM_EXTABLE(1b, 3b)				\
		     : [err] "=r" (err), output				\
		     : "0"(0), input);					\
	err;								\
})

static inline int fsave_user(struct i387_fsave_struct __user *fx)
{
	return check_insn(fnsave %[fx]; fwait,  [fx] "=m" (*fx), "m" (*fx));
}

static inline int fxsave_user(struct i387_fxsave_struct __user *fx)
{
	if (config_enabled(CONFIG_X86_32))
		return check_insn(fxsave %[fx], [fx] "=m" (*fx), "m" (*fx));
	else if (config_enabled(CONFIG_AS_FXSAVEQ))
		return check_insn(fxsaveq %[fx], [fx] "=m" (*fx), "m" (*fx));

	/* See comment in fpu_fxsave() below. */
	return check_insn(rex64/fxsave (%[fx]), "=m" (*fx), [fx] "R" (fx));
}

static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
{
	if (config_enabled(CONFIG_X86_32))
		return check_insn(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx));
	else if (config_enabled(CONFIG_AS_FXSAVEQ))
		return check_insn(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx));

	/* See comment in fpu_fxsave() below. */
	return check_insn(rex64/fxrstor (%[fx]), "=m" (*fx), [fx] "R" (fx),
			  "m" (*fx));
}

static inline int frstor_checking(struct i387_fsave_struct *fx)
{
	return check_insn(frstor %[fx], "=m" (*fx), [fx] "m" (*fx));
}

static inline void fpu_fxsave(struct fpu *fpu)
{
	if (config_enabled(CONFIG_X86_32))
		asm volatile( "fxsave %[fx]" : [fx] "=m" (fpu->state->fxsave));
	else if (config_enabled(CONFIG_AS_FXSAVEQ))
		asm volatile("fxsaveq %0" : "=m" (fpu->state->fxsave));
	else {
		/* Using "rex64; fxsave %0" is broken because, if the memory
		 * operand uses any extended registers for addressing, a second
		 * REX prefix will be generated (to the assembler, rex64
		 * followed by semicolon is a separate instruction), and hence
		 * the 64-bitness is lost.
		 *
		 * Using "fxsaveq %0" would be the ideal choice, but is only
		 * supported starting with gas 2.16.
		 *
		 * Using, as a workaround, the properly prefixed form below
		 * isn't accepted by any binutils version so far released,
		 * complaining that the same type of prefix is used twice if
		 * an extended register is needed for addressing (fix submitted
		 * to mainline 2005-11-21).
		 *
		 *  asm volatile("rex64/fxsave %0" : "=m" (fpu->state->fxsave));
		 *
		 * This, however, we can work around by forcing the compiler to
		 * select an addressing mode that doesn't require extended
		 * registers.
		 */
		asm volatile( "rex64/fxsave (%[fx])"
			     : "=m" (fpu->state->fxsave)
			     : [fx] "R" (&fpu->state->fxsave));
	}
}

/*
 * These must be called with preempt disabled. Returns
 * 'true' if the FPU state is still intact.
 */
static inline int fpu_save_init(struct fpu *fpu)
{
	if (use_xsave()) {
		fpu_xsave(fpu);

		/*
		 * xsave header may indicate the init state of the FP.
		 */
		if (!(fpu->state->xsave.xsave_hdr.xstate_bv & XSTATE_FP))
			return 1;
	} else if (use_fxsr()) {
		fpu_fxsave(fpu);
	} else {
		asm volatile("fnsave %[fx]; fwait"
			     : [fx] "=m" (fpu->state->fsave));
		return 0;
	}

	/*
	 * If exceptions are pending, we need to clear them so
	 * that we don't randomly get exceptions later.
	 *
	 * FIXME! Is this perhaps only true for the old-style
	 * irq13 case? Maybe we could leave the x87 state
	 * intact otherwise?
	 */
	if (unlikely(fpu->state->fxsave.swd & X87_FSW_ES)) {
		asm volatile("fnclex");
		return 0;
	}
	return 1;
}

static inline int __save_init_fpu(struct task_struct *tsk)
{
	return fpu_save_init(&tsk->thread.fpu);
}

static inline int fpu_restore_checking(struct fpu *fpu)
{
	if (use_xsave())
		return fpu_xrstor_checking(&fpu->state->xsave);
	else if (use_fxsr())
		return fxrstor_checking(&fpu->state->fxsave);
	else
		return frstor_checking(&fpu->state->fsave);
}

static inline int restore_fpu_checking(struct task_struct *tsk)
{
	/* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
	   is pending.  Clear the x87 state here by setting it to fixed
	   values. "m" is a random variable that should be in L1 */
	alternative_input(
		ASM_NOP8 ASM_NOP2,
		"emms\n\t"		/* clear stack tags */
		"fildl %P[addr]",	/* set F?P to defined value */
		X86_FEATURE_FXSAVE_LEAK,
		[addr] "m" (tsk->thread.fpu.has_fpu));

	return fpu_restore_checking(&tsk->thread.fpu);
}

/*
 * Software FPU state helpers. Careful: these need to
 * be preemption protection *and* they need to be
 * properly paired with the CR0.TS changes!
 */
static inline int __thread_has_fpu(struct task_struct *tsk)
{
	return tsk->thread.fpu.has_fpu;
}

/* Must be paired with an 'stts' after! */
static inline void __thread_clear_has_fpu(struct task_struct *tsk)
{
	tsk->thread.fpu.has_fpu = 0;
	this_cpu_write(fpu_owner_task, NULL);
}

/* Must be paired with a 'clts' before! */
static inline void __thread_set_has_fpu(struct task_struct *tsk)
{
	tsk->thread.fpu.has_fpu = 1;
	this_cpu_write(fpu_owner_task, tsk);
}

/*
 * Encapsulate the CR0.TS handling together with the
 * software flag.
 *
 * These generally need preemption protection to work,
 * do try to avoid using these on their own.
 */
static inline void __thread_fpu_end(struct task_struct *tsk)
{
	__thread_clear_has_fpu(tsk);
	if (!use_eager_fpu())
		stts();
}

static inline void __thread_fpu_begin(struct task_struct *tsk)
{
	if (!use_eager_fpu())
		clts();
	__thread_set_has_fpu(tsk);
}

static inline void __drop_fpu(struct task_struct *tsk)
{
	if (__thread_has_fpu(tsk)) {
		/* Ignore delayed exceptions from user space */
		asm volatile("1: fwait\n"
			     "2:\n"
			     _ASM_EXTABLE(1b, 2b));
		__thread_fpu_end(tsk);
	}
}

static inline void drop_fpu(struct task_struct *tsk)
{
	/*
	 * Forget coprocessor state..
	 */
	preempt_disable();
	tsk->fpu_counter = 0;
	__drop_fpu(tsk);
	clear_used_math();
	preempt_enable();
}

static inline void drop_init_fpu(struct task_struct *tsk)
{
	if (!use_eager_fpu())
		drop_fpu(tsk);
	else {
		if (use_xsave())
			xrstor_state(init_xstate_buf, -1);
		else
			fxrstor_checking(&init_xstate_buf->i387);
	}
}

/*
 * FPU state switching for scheduling.
 *
 * This is a two-stage process:
 *
 *  - switch_fpu_prepare() saves the old state and
 *    sets the new state of the CR0.TS bit. This is
 *    done within the context of the old process.
 *
 *  - switch_fpu_finish() restores the new state as
 *    necessary.
 */
typedef struct { int preload; } fpu_switch_t;

/*
 * FIXME! We could do a totally lazy restore, but we need to
 * add a per-cpu "this was the task that last touched the FPU
 * on this CPU" variable, and the task needs to have a "I last
 * touched the FPU on this CPU" and check them.
 *
 * We don't do that yet, so "fpu_lazy_restore()" always returns
 * false, but some day..
 */
static inline int fpu_lazy_restore(struct task_struct *new, unsigned int cpu)
{
	return new == this_cpu_read_stable(fpu_owner_task) &&
		cpu == new->thread.fpu.last_cpu;
}

static inline fpu_switch_t switch_fpu_prepare(struct task_struct *old, struct task_struct *new, int cpu)
{
	fpu_switch_t fpu;

	/*
	 * If the task has used the math, pre-load the FPU on xsave processors
	 * or if the past 5 consecutive context-switches used math.
	 */
	fpu.preload = tsk_used_math(new) && (use_eager_fpu() ||
					     new->fpu_counter > 5);
	if (__thread_has_fpu(old)) {
		if (!__save_init_fpu(old))
			cpu = ~0;
		old->thread.fpu.last_cpu = cpu;
		old->thread.fpu.has_fpu = 0;	/* But leave fpu_owner_task! */

		/* Don't change CR0.TS if we just switch! */
		if (fpu.preload) {
			new->fpu_counter++;
			__thread_set_has_fpu(new);
			prefetch(new->thread.fpu.state);
		} else if (!use_eager_fpu())
			stts();
	} else {
		old->fpu_counter = 0;
		old->thread.fpu.last_cpu = ~0;
		if (fpu.preload) {
			new->fpu_counter++;
			if (!use_eager_fpu() && fpu_lazy_restore(new, cpu))
				fpu.preload = 0;
			else
				prefetch(new->thread.fpu.state);
			__thread_fpu_begin(new);
		}
	}
	return fpu;
}

/*
 * By the time this gets called, we've already cleared CR0.TS and
 * given the process the FPU if we are going to preload the FPU
 * state - all we need to do is to conditionally restore the register
 * state itself.
 */
static inline void switch_fpu_finish(struct task_struct *new, fpu_switch_t fpu)
{
	if (fpu.preload) {
		if (unlikely(restore_fpu_checking(new)))
			drop_init_fpu(new);
	}
}

/*
 * Signal frame handlers...
 */
extern int save_xstate_sig(void __user *buf, void __user *fx, int size);
extern int __restore_xstate_sig(void __user *buf, void __user *fx, int size);

static inline int xstate_sigframe_size(void)
{
	return use_xsave() ? xstate_size + FP_XSTATE_MAGIC2_SIZE : xstate_size;
}

static inline int restore_xstate_sig(void __user *buf, int ia32_frame)
{
	void __user *buf_fx = buf;
	int size = xstate_sigframe_size();

	if (ia32_frame && use_fxsr()) {
		buf_fx = buf + sizeof(struct i387_fsave_struct);
		size += sizeof(struct i387_fsave_struct);
	}

	return __restore_xstate_sig(buf, buf_fx, size);
}

/*
 * Need to be preemption-safe.
 *
 * NOTE! user_fpu_begin() must be used only immediately before restoring
 * it. This function does not do any save/restore on their own.
 */
static inline void user_fpu_begin(void)
{
	preempt_disable();
	if (!user_has_fpu())
		__thread_fpu_begin(current);
	preempt_enable();
}

static inline void __save_fpu(struct task_struct *tsk)
{
	if (use_xsave())
		xsave_state(&tsk->thread.fpu.state->xsave, -1);
	else
		fpu_fxsave(&tsk->thread.fpu);
}

/*
 * These disable preemption on their own and are safe
 */
static inline void save_init_fpu(struct task_struct *tsk)
{
	WARN_ON_ONCE(!__thread_has_fpu(tsk));

	if (use_eager_fpu()) {
		__save_fpu(tsk);
		return;
	}

	preempt_disable();
	__save_init_fpu(tsk);
	__thread_fpu_end(tsk);
	preempt_enable();
}

/*
 * i387 state interaction
 */
static inline unsigned short get_fpu_cwd(struct task_struct *tsk)
{
	if (cpu_has_fxsr) {
		return tsk->thread.fpu.state->fxsave.cwd;
	} else {
		return (unsigned short)tsk->thread.fpu.state->fsave.cwd;
	}
}

static inline unsigned short get_fpu_swd(struct task_struct *tsk)
{
	if (cpu_has_fxsr) {
		return tsk->thread.fpu.state->fxsave.swd;
	} else {
		return (unsigned short)tsk->thread.fpu.state->fsave.swd;
	}
}

static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk)
{
	if (cpu_has_xmm) {
		return tsk->thread.fpu.state->fxsave.mxcsr;
	} else {
		return MXCSR_DEFAULT;
	}
}

static bool fpu_allocated(struct fpu *fpu)
{
	return fpu->state != NULL;
}

static inline int fpu_alloc(struct fpu *fpu)
{
	if (fpu_allocated(fpu))
		return 0;
	fpu->state = kmem_cache_alloc(task_xstate_cachep, GFP_KERNEL);
	if (!fpu->state)
		return -ENOMEM;
	WARN_ON((unsigned long)fpu->state & 15);
	return 0;
}

static inline void fpu_free(struct fpu *fpu)
{
	if (fpu->state) {
		kmem_cache_free(task_xstate_cachep, fpu->state);
		fpu->state = NULL;
	}
}

static inline void fpu_copy(struct task_struct *dst, struct task_struct *src)
{
	if (use_eager_fpu()) {
		memset(&dst->thread.fpu.state->xsave, 0, xstate_size);
		__save_fpu(dst);
	} else {
		struct fpu *dfpu = &dst->thread.fpu;
		struct fpu *sfpu = &src->thread.fpu;

		unlazy_fpu(src);
		memcpy(dfpu->state, sfpu->state, xstate_size);
	}
}

static inline unsigned long
alloc_mathframe(unsigned long sp, int ia32_frame, unsigned long *buf_fx,
		unsigned long *size)
{
	unsigned long frame_size = xstate_sigframe_size();

	*buf_fx = sp = round_down(sp - frame_size, 64);
	if (ia32_frame && use_fxsr()) {
		frame_size += sizeof(struct i387_fsave_struct);
		sp -= sizeof(struct i387_fsave_struct);
	}

	*size = frame_size;
	return sp;
}

#endif
Commit	Line	Data
1361b83a LT	1	/*
	2	* Copyright (C) 1994 Linus Torvalds
	3	*
	4	* Pentium III FXSR, SSE support
	5	* General FPU state handling cleanups
	6	* Gareth Hughes <gareth@valinux.com>, May 2000
	7	* x86-64 work by Andi Kleen 2002
	8	*/
	9
	10	#ifndef _FPU_INTERNAL_H
	11	#define _FPU_INTERNAL_H
	12
	13	#include <linux/kernel_stat.h>
	14	#include <linux/regset.h>
050902c0	15	#include <linux/compat.h>
1361b83a LT	16	#include <linux/slab.h>
	17	#include <asm/asm.h>
	18	#include <asm/cpufeature.h>
	19	#include <asm/processor.h>
	20	#include <asm/sigcontext.h>
	21	#include <asm/user.h>
	22	#include <asm/uaccess.h>
	23	#include <asm/xsave.h>
	24
72a671ce SS	25	#ifdef CONFIG_X86_64
	26	# include <asm/sigcontext32.h>
	27	# include <asm/user32.h>
	28	int ia32_setup_rt_frame(int sig, struct k_sigaction ka, siginfo_t info,
	29	compat_sigset_t set, struct pt_regs regs);
	30	int ia32_setup_frame(int sig, struct k_sigaction *ka,
	31	compat_sigset_t set, struct pt_regs regs);
	32	#else
	33	# define user_i387_ia32_struct user_i387_struct
	34	# define user32_fxsr_struct user_fxsr_struct
	35	# define ia32_setup_frame __setup_frame
	36	# define ia32_setup_rt_frame __setup_rt_frame
	37	#endif
	38
	39	extern unsigned int mxcsr_feature_mask;
1361b83a	40	extern void fpu_init(void);
5d2bd700	41	extern void eager_fpu_init(void);
1361b83a LT	42
	43	DECLARE_PER_CPU(struct task_struct *, fpu_owner_task);
	44
72a671ce SS	45	extern void convert_from_fxsr(struct user_i387_ia32_struct *env,
	46	struct task_struct *tsk);
	47	extern void convert_to_fxsr(struct task_struct *tsk,
	48	const struct user_i387_ia32_struct *env);
	49
1361b83a LT	50	extern user_regset_active_fn fpregs_active, xfpregs_active;
	51	extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get,
	52	xstateregs_get;
	53	extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set,
	54	xstateregs_set;
	55
1361b83a LT	56	/*
	57	* xstateregs_active == fpregs_active. Please refer to the comment
	58	* at the definition of fpregs_active.
	59	*/
	60	#define xstateregs_active fpregs_active
	61
1361b83a	62	#ifdef CONFIG_MATH_EMULATION
72a671ce	63	# define HAVE_HWFP (boot_cpu_data.hard_math)
1361b83a LT	64	extern void finit_soft_fpu(struct i387_soft_struct *soft);
1361b83a LT	65	#else
72a671ce	66	# define HAVE_HWFP 1
1361b83a LT	67	static inline void finit_soft_fpu(struct i387_soft_struct *soft) {}
	68	#endif
	69
050902c0 SS	70	static inline int is_ia32_compat_frame(void)
	71	{
	72	return config_enabled(CONFIG_IA32_EMULATION) &&
	73	test_thread_flag(TIF_IA32);
	74	}
	75
	76	static inline int is_ia32_frame(void)
	77	{
	78	return config_enabled(CONFIG_X86_32) \|\| is_ia32_compat_frame();
	79	}
	80
	81	static inline int is_x32_frame(void)
	82	{
	83	return config_enabled(CONFIG_X86_X32_ABI) && test_thread_flag(TIF_X32);
	84	}
	85
1361b83a LT	86	#define X87_FSW_ES (1 << 7) /* Exception Summary */
1361b83a LT	87
5d2bd700 SS	88	static __always_inline __pure bool use_eager_fpu(void)
	89	{
	90	return static_cpu_has(X86_FEATURE_EAGER_FPU);
	91	}
	92
1361b83a LT	93	static __always_inline __pure bool use_xsaveopt(void)
	94	{
	95	return static_cpu_has(X86_FEATURE_XSAVEOPT);
	96	}
	97
	98	static __always_inline __pure bool use_xsave(void)
	99	{
	100	return static_cpu_has(X86_FEATURE_XSAVE);
	101	}
	102
	103	static __always_inline __pure bool use_fxsr(void)
	104	{
	105	return static_cpu_has(X86_FEATURE_FXSR);
	106	}
	107
5d2bd700 SS	108	static inline void fx_finit(struct i387_fxsave_struct *fx)
	109	{
	110	memset(fx, 0, xstate_size);
	111	fx->cwd = 0x37f;
a8615af4	112	fx->mxcsr = MXCSR_DEFAULT;
5d2bd700 SS	113	}
5d2bd700 SS	114
1361b83a LT	115	extern void __sanitize_i387_state(struct task_struct *);
	116
	117	static inline void sanitize_i387_state(struct task_struct *tsk)
	118	{
	119	if (!use_xsaveopt())
	120	return;
	121	__sanitize_i387_state(tsk);
	122	}
	123
0ca5bd0d SS	124	#define check_insn(insn, output, input...) \
	125	({ \
	126	int err; \
	127	asm volatile("1:" #insn "\n\t" \
	128	"2:\n" \
	129	".section .fixup,\"ax\"\n" \
	130	"3: movl $-1,%[err]\n" \
	131	" jmp 2b\n" \
	132	".previous\n" \
	133	_ASM_EXTABLE(1b, 3b) \
	134	: [err] "=r" (err), output \
	135	: "0"(0), input); \
	136	err; \
	137	})
	138
	139	static inline int fsave_user(struct i387_fsave_struct __user *fx)
1361b83a	140	{
0ca5bd0d	141	return check_insn(fnsave %[fx]; fwait, [fx] "=m" (fx), "m" (fx));
1361b83a LT	142	}
	143
	144	static inline int fxsave_user(struct i387_fxsave_struct __user *fx)
	145	{
0ca5bd0d SS	146	if (config_enabled(CONFIG_X86_32))
	147	return check_insn(fxsave %[fx], [fx] "=m" (fx), "m" (fx));
	148	else if (config_enabled(CONFIG_AS_FXSAVEQ))
	149	return check_insn(fxsaveq %[fx], [fx] "=m" (fx), "m" (fx));
	150
	151	/* See comment in fpu_fxsave() below. */
	152	return check_insn(rex64/fxsave (%[fx]), "=m" (*fx), [fx] "R" (fx));
	153	}
	154
	155	static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
	156	{
	157	if (config_enabled(CONFIG_X86_32))
	158	return check_insn(fxrstor %[fx], "=m" (fx), [fx] "m" (fx));
	159	else if (config_enabled(CONFIG_AS_FXSAVEQ))
	160	return check_insn(fxrstorq %[fx], "=m" (fx), [fx] "m" (fx));
	161
	162	/* See comment in fpu_fxsave() below. */
	163	return check_insn(rex64/fxrstor (%[fx]), "=m" (*fx), [fx] "R" (fx),
	164	"m" (*fx));
	165	}
	166
	167	static inline int frstor_checking(struct i387_fsave_struct *fx)
	168	{
	169	return check_insn(frstor %[fx], "=m" (fx), [fx] "m" (fx));
1361b83a LT	170	}
	171
	172	static inline void fpu_fxsave(struct fpu *fpu)
	173	{
0ca5bd0d SS	174	if (config_enabled(CONFIG_X86_32))
	175	asm volatile( "fxsave %[fx]" : [fx] "=m" (fpu->state->fxsave));
	176	else if (config_enabled(CONFIG_AS_FXSAVEQ))
	177	asm volatile("fxsaveq %0" : "=m" (fpu->state->fxsave));
	178	else {
	179	/* Using "rex64; fxsave %0" is broken because, if the memory
	180	* operand uses any extended registers for addressing, a second
	181	* REX prefix will be generated (to the assembler, rex64
	182	* followed by semicolon is a separate instruction), and hence
	183	* the 64-bitness is lost.
	184	*
	185	* Using "fxsaveq %0" would be the ideal choice, but is only
	186	* supported starting with gas 2.16.
	187	*
	188	* Using, as a workaround, the properly prefixed form below
	189	* isn't accepted by any binutils version so far released,
	190	* complaining that the same type of prefix is used twice if
	191	* an extended register is needed for addressing (fix submitted
	192	* to mainline 2005-11-21).
	193	*
	194	* asm volatile("rex64/fxsave %0" : "=m" (fpu->state->fxsave));
	195	*
	196	* This, however, we can work around by forcing the compiler to
	197	* select an addressing mode that doesn't require extended
	198	* registers.
	199	*/
	200	asm volatile( "rex64/fxsave (%[fx])"
	201	: "=m" (fpu->state->fxsave)
	202	: [fx] "R" (&fpu->state->fxsave));
	203	}
1361b83a	204	}
1361b83a LT	205
	206	/*
	207	* These must be called with preempt disabled. Returns
	208	* 'true' if the FPU state is still intact.
	209	*/
	210	static inline int fpu_save_init(struct fpu *fpu)
	211	{
	212	if (use_xsave()) {
	213	fpu_xsave(fpu);
	214
	215	/*
	216	* xsave header may indicate the init state of the FP.
	217	*/
	218	if (!(fpu->state->xsave.xsave_hdr.xstate_bv & XSTATE_FP))
	219	return 1;
	220	} else if (use_fxsr()) {
	221	fpu_fxsave(fpu);
	222	} else {
	223	asm volatile("fnsave %[fx]; fwait"
	224	: [fx] "=m" (fpu->state->fsave));
	225	return 0;
	226	}
	227
	228	/*
	229	* If exceptions are pending, we need to clear them so
	230	* that we don't randomly get exceptions later.
	231	*
	232	* FIXME! Is this perhaps only true for the old-style
	233	* irq13 case? Maybe we could leave the x87 state
	234	* intact otherwise?
	235	*/
	236	if (unlikely(fpu->state->fxsave.swd & X87_FSW_ES)) {
	237	asm volatile("fnclex");
	238	return 0;
	239	}
	240	return 1;
	241	}
	242
	243	static inline int __save_init_fpu(struct task_struct *tsk)
	244	{
	245	return fpu_save_init(&tsk->thread.fpu);
	246	}
	247
1361b83a LT	248	static inline int fpu_restore_checking(struct fpu *fpu)
	249	{
	250	if (use_xsave())
0ca5bd0d SS	251	return fpu_xrstor_checking(&fpu->state->xsave);
	252	else if (use_fxsr())
	253	return fxrstor_checking(&fpu->state->fxsave);
1361b83a	254	else
0ca5bd0d	255	return frstor_checking(&fpu->state->fsave);
1361b83a LT	256	}
	257
	258	static inline int restore_fpu_checking(struct task_struct *tsk)
	259	{
	260	/* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
	261	is pending. Clear the x87 state here by setting it to fixed
	262	values. "m" is a random variable that should be in L1 */
	263	alternative_input(
	264	ASM_NOP8 ASM_NOP2,
	265	"emms\n\t" /* clear stack tags */
	266	"fildl %P[addr]", /* set F?P to defined value */
	267	X86_FEATURE_FXSAVE_LEAK,
	268	[addr] "m" (tsk->thread.fpu.has_fpu));
	269
	270	return fpu_restore_checking(&tsk->thread.fpu);
	271	}
	272
	273	/*
	274	* Software FPU state helpers. Careful: these need to
	275	* be preemption protection and they need to be
	276	* properly paired with the CR0.TS changes!
	277	*/
	278	static inline int __thread_has_fpu(struct task_struct *tsk)
	279	{
	280	return tsk->thread.fpu.has_fpu;
	281	}
	282
	283	/* Must be paired with an 'stts' after! */
	284	static inline void __thread_clear_has_fpu(struct task_struct *tsk)
	285	{
	286	tsk->thread.fpu.has_fpu = 0;
c6ae41e7	287	this_cpu_write(fpu_owner_task, NULL);
1361b83a LT	288	}
	289
	290	/* Must be paired with a 'clts' before! */
	291	static inline void __thread_set_has_fpu(struct task_struct *tsk)
	292	{
	293	tsk->thread.fpu.has_fpu = 1;
c6ae41e7	294	this_cpu_write(fpu_owner_task, tsk);
1361b83a LT	295	}
	296
	297	/*
	298	* Encapsulate the CR0.TS handling together with the
	299	* software flag.
	300	*
	301	* These generally need preemption protection to work,
	302	* do try to avoid using these on their own.
	303	*/
	304	static inline void __thread_fpu_end(struct task_struct *tsk)
	305	{
	306	__thread_clear_has_fpu(tsk);
5d2bd700	307	if (!use_eager_fpu())
304bceda	308	stts();
1361b83a LT	309	}
	310
	311	static inline void __thread_fpu_begin(struct task_struct *tsk)
	312	{
5d2bd700	313	if (!use_eager_fpu())
304bceda	314	clts();
1361b83a LT	315	__thread_set_has_fpu(tsk);
	316	}
	317
304bceda SS	318	static inline void __drop_fpu(struct task_struct *tsk)
	319	{
	320	if (__thread_has_fpu(tsk)) {
	321	/* Ignore delayed exceptions from user space */
	322	asm volatile("1: fwait\n"
	323	"2:\n"
	324	_ASM_EXTABLE(1b, 2b));
	325	__thread_fpu_end(tsk);
	326	}
	327	}
	328
	329	static inline void drop_fpu(struct task_struct *tsk)
	330	{
	331	/*
	332	* Forget coprocessor state..
	333	*/
	334	preempt_disable();
	335	tsk->fpu_counter = 0;
	336	__drop_fpu(tsk);
	337	clear_used_math();
	338	preempt_enable();
	339	}
	340
	341	static inline void drop_init_fpu(struct task_struct *tsk)
	342	{
5d2bd700	343	if (!use_eager_fpu())
304bceda	344	drop_fpu(tsk);
5d2bd700 SS	345	else {
	346	if (use_xsave())
	347	xrstor_state(init_xstate_buf, -1);
	348	else
	349	fxrstor_checking(&init_xstate_buf->i387);
	350	}
304bceda SS	351	}
304bceda SS	352
1361b83a LT	353	/*
	354	* FPU state switching for scheduling.
	355	*
	356	* This is a two-stage process:
	357	*
	358	* - switch_fpu_prepare() saves the old state and
	359	* sets the new state of the CR0.TS bit. This is
	360	* done within the context of the old process.
	361	*
	362	* - switch_fpu_finish() restores the new state as
	363	* necessary.
	364	*/
	365	typedef struct { int preload; } fpu_switch_t;
	366
	367	/*
	368	* FIXME! We could do a totally lazy restore, but we need to
	369	* add a per-cpu "this was the task that last touched the FPU
	370	* on this CPU" variable, and the task needs to have a "I last
	371	* touched the FPU on this CPU" and check them.
	372	*
	373	* We don't do that yet, so "fpu_lazy_restore()" always returns
	374	* false, but some day..
	375	*/
	376	static inline int fpu_lazy_restore(struct task_struct *new, unsigned int cpu)
	377	{
c6ae41e7	378	return new == this_cpu_read_stable(fpu_owner_task) &&
1361b83a LT	379	cpu == new->thread.fpu.last_cpu;
	380	}
	381
	382	static inline fpu_switch_t switch_fpu_prepare(struct task_struct old, struct task_struct new, int cpu)
	383	{
	384	fpu_switch_t fpu;
	385
304bceda SS	386	/*
	387	* If the task has used the math, pre-load the FPU on xsave processors
	388	* or if the past 5 consecutive context-switches used math.
	389	*/
5d2bd700	390	fpu.preload = tsk_used_math(new) && (use_eager_fpu() \|\|
304bceda	391	new->fpu_counter > 5);
1361b83a LT	392	if (__thread_has_fpu(old)) {
	393	if (!__save_init_fpu(old))
	394	cpu = ~0;
	395	old->thread.fpu.last_cpu = cpu;
	396	old->thread.fpu.has_fpu = 0; /* But leave fpu_owner_task! */
	397
	398	/* Don't change CR0.TS if we just switch! */
	399	if (fpu.preload) {
	400	new->fpu_counter++;
	401	__thread_set_has_fpu(new);
	402	prefetch(new->thread.fpu.state);
5d2bd700	403	} else if (!use_eager_fpu())
1361b83a LT	404	stts();
	405	} else {
	406	old->fpu_counter = 0;
	407	old->thread.fpu.last_cpu = ~0;
	408	if (fpu.preload) {
	409	new->fpu_counter++;
5d2bd700	410	if (!use_eager_fpu() && fpu_lazy_restore(new, cpu))
1361b83a LT	411	fpu.preload = 0;
	412	else
	413	prefetch(new->thread.fpu.state);
	414	__thread_fpu_begin(new);
	415	}
	416	}
	417	return fpu;
	418	}
	419
	420	/*
	421	* By the time this gets called, we've already cleared CR0.TS and
	422	* given the process the FPU if we are going to preload the FPU
	423	* state - all we need to do is to conditionally restore the register
	424	* state itself.
	425	*/
	426	static inline void switch_fpu_finish(struct task_struct *new, fpu_switch_t fpu)
	427	{
	428	if (fpu.preload) {
	429	if (unlikely(restore_fpu_checking(new)))
304bceda	430	drop_init_fpu(new);
1361b83a LT	431	}
	432	}
	433
	434	/*
	435	* Signal frame handlers...
	436	*/
72a671ce SS	437	extern int save_xstate_sig(void __user buf, void __user fx, int size);
	438	extern int __restore_xstate_sig(void __user buf, void __user fx, int size);
	439
	440	static inline int xstate_sigframe_size(void)
	441	{
	442	return use_xsave() ? xstate_size + FP_XSTATE_MAGIC2_SIZE : xstate_size;
	443	}
	444
	445	static inline int restore_xstate_sig(void __user *buf, int ia32_frame)
	446	{
	447	void __user *buf_fx = buf;
	448	int size = xstate_sigframe_size();
	449
	450	if (ia32_frame && use_fxsr()) {
	451	buf_fx = buf + sizeof(struct i387_fsave_struct);
	452	size += sizeof(struct i387_fsave_struct);
	453	}
	454
	455	return __restore_xstate_sig(buf, buf_fx, size);
	456	}
1361b83a	457
1361b83a	458	/*
377ffbcc	459	* Need to be preemption-safe.
1361b83a	460	*
377ffbcc SS	461	* NOTE! user_fpu_begin() must be used only immediately before restoring
377ffbcc SS	462	* it. This function does not do any save/restore on their own.
1361b83a	463	*/
1361b83a LT	464	static inline void user_fpu_begin(void)
	465	{
	466	preempt_disable();
	467	if (!user_has_fpu())
	468	__thread_fpu_begin(current);
	469	preempt_enable();
	470	}
	471
5d2bd700 SS	472	static inline void __save_fpu(struct task_struct *tsk)
	473	{
	474	if (use_xsave())
	475	xsave_state(&tsk->thread.fpu.state->xsave, -1);
	476	else
	477	fpu_fxsave(&tsk->thread.fpu);
	478	}
	479
1361b83a LT	480	/*
	481	* These disable preemption on their own and are safe
	482	*/
	483	static inline void save_init_fpu(struct task_struct *tsk)
	484	{
	485	WARN_ON_ONCE(!__thread_has_fpu(tsk));
304bceda	486
5d2bd700 SS	487	if (use_eager_fpu()) {
5d2bd700 SS	488	__save_fpu(tsk);
304bceda SS	489	return;
	490	}
	491
1361b83a LT	492	preempt_disable();
	493	__save_init_fpu(tsk);
	494	__thread_fpu_end(tsk);
	495	preempt_enable();
	496	}
	497
1361b83a LT	498	/*
	499	* i387 state interaction
	500	*/
	501	static inline unsigned short get_fpu_cwd(struct task_struct *tsk)
	502	{
	503	if (cpu_has_fxsr) {
	504	return tsk->thread.fpu.state->fxsave.cwd;
	505	} else {
	506	return (unsigned short)tsk->thread.fpu.state->fsave.cwd;
	507	}
	508	}
	509
	510	static inline unsigned short get_fpu_swd(struct task_struct *tsk)
	511	{
	512	if (cpu_has_fxsr) {
	513	return tsk->thread.fpu.state->fxsave.swd;
	514	} else {
	515	return (unsigned short)tsk->thread.fpu.state->fsave.swd;
	516	}
	517	}
	518
	519	static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk)
	520	{
	521	if (cpu_has_xmm) {
	522	return tsk->thread.fpu.state->fxsave.mxcsr;
	523	} else {
	524	return MXCSR_DEFAULT;
	525	}
	526	}
	527
	528	static bool fpu_allocated(struct fpu *fpu)
	529	{
	530	return fpu->state != NULL;
	531	}
	532
	533	static inline int fpu_alloc(struct fpu *fpu)
	534	{
	535	if (fpu_allocated(fpu))
	536	return 0;
	537	fpu->state = kmem_cache_alloc(task_xstate_cachep, GFP_KERNEL);
	538	if (!fpu->state)
	539	return -ENOMEM;
	540	WARN_ON((unsigned long)fpu->state & 15);
	541	return 0;
	542	}
	543
	544	static inline void fpu_free(struct fpu *fpu)
	545	{
	546	if (fpu->state) {
	547	kmem_cache_free(task_xstate_cachep, fpu->state);
	548	fpu->state = NULL;
	549	}
	550	}
	551
304bceda	552	static inline void fpu_copy(struct task_struct dst, struct task_struct src)
1361b83a	553	{
5d2bd700 SS	554	if (use_eager_fpu()) {
	555	memset(&dst->thread.fpu.state->xsave, 0, xstate_size);
	556	__save_fpu(dst);
304bceda SS	557	} else {
	558	struct fpu *dfpu = &dst->thread.fpu;
	559	struct fpu *sfpu = &src->thread.fpu;
	560
	561	unlazy_fpu(src);
	562	memcpy(dfpu->state, sfpu->state, xstate_size);
	563	}
	564	}
1361b83a	565
72a671ce SS	566	static inline unsigned long
	567	alloc_mathframe(unsigned long sp, int ia32_frame, unsigned long *buf_fx,
	568	unsigned long *size)
	569	{
	570	unsigned long frame_size = xstate_sigframe_size();
	571
	572	*buf_fx = sp = round_down(sp - frame_size, 64);
	573	if (ia32_frame && use_fxsr()) {
	574	frame_size += sizeof(struct i387_fsave_struct);
	575	sp -= sizeof(struct i387_fsave_struct);
	576	}
	577
	578	*size = frame_size;
	579	return sp;
	580	}
	581
1361b83a	582	#endif