Commit | Line | Data |
---|---|---|
1361b83a LT |
1 | /* |
2 | * Copyright (C) 1994 Linus Torvalds | |
3 | * | |
4 | * Pentium III FXSR, SSE support | |
5 | * General FPU state handling cleanups | |
6 | * Gareth Hughes <gareth@valinux.com>, May 2000 | |
7 | * x86-64 work by Andi Kleen 2002 | |
8 | */ | |
9 | ||
10 | #ifndef _FPU_INTERNAL_H | |
11 | #define _FPU_INTERNAL_H | |
12 | ||
1361b83a | 13 | #include <linux/regset.h> |
050902c0 | 14 | #include <linux/compat.h> |
1361b83a | 15 | #include <linux/slab.h> |
f89e32e0 | 16 | |
1361b83a | 17 | #include <asm/user.h> |
f89e32e0 | 18 | #include <asm/i387.h> |
1361b83a LT |
19 | #include <asm/xsave.h> |
20 | ||
72a671ce SS |
21 | #ifdef CONFIG_X86_64 |
22 | # include <asm/sigcontext32.h> | |
23 | # include <asm/user32.h> | |
235b8022 AV |
24 | struct ksignal; |
25 | int ia32_setup_rt_frame(int sig, struct ksignal *ksig, | |
72a671ce | 26 | compat_sigset_t *set, struct pt_regs *regs); |
235b8022 | 27 | int ia32_setup_frame(int sig, struct ksignal *ksig, |
72a671ce SS |
28 | compat_sigset_t *set, struct pt_regs *regs); |
29 | #else | |
30 | # define user_i387_ia32_struct user_i387_struct | |
31 | # define user32_fxsr_struct user_fxsr_struct | |
32 | # define ia32_setup_frame __setup_frame | |
33 | # define ia32_setup_rt_frame __setup_rt_frame | |
34 | #endif | |
35 | ||
36 | extern unsigned int mxcsr_feature_mask; | |
3a9c4b0d | 37 | extern void fpu__cpu_init(void); |
5d2bd700 | 38 | extern void eager_fpu_init(void); |
1361b83a | 39 | |
36b544dc | 40 | DECLARE_PER_CPU(struct fpu *, fpu_fpregs_owner_ctx); |
1361b83a | 41 | |
72a671ce SS |
42 | extern void convert_from_fxsr(struct user_i387_ia32_struct *env, |
43 | struct task_struct *tsk); | |
44 | extern void convert_to_fxsr(struct task_struct *tsk, | |
45 | const struct user_i387_ia32_struct *env); | |
46 | ||
1361b83a LT |
47 | extern user_regset_active_fn fpregs_active, xfpregs_active; |
48 | extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get, | |
49 | xstateregs_get; | |
50 | extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set, | |
51 | xstateregs_set; | |
52 | ||
1361b83a LT |
53 | /* |
54 | * xstateregs_active == fpregs_active. Please refer to the comment | |
55 | * at the definition of fpregs_active. | |
56 | */ | |
57 | #define xstateregs_active fpregs_active | |
58 | ||
1361b83a LT |
59 | #ifdef CONFIG_MATH_EMULATION |
60 | extern void finit_soft_fpu(struct i387_soft_struct *soft); | |
61 | #else | |
62 | static inline void finit_soft_fpu(struct i387_soft_struct *soft) {} | |
63 | #endif | |
64 | ||
1c927eea | 65 | /* |
36b544dc | 66 | * Must be run with preemption disabled: this clears the fpu_fpregs_owner_ctx, |
1c927eea RR |
67 | * on this CPU. |
68 | * | |
69 | * This will disable any lazy FPU state restore of the current FPU state, | |
70 | * but if the current thread owns the FPU, it will still be saved by. | |
71 | */ | |
72 | static inline void __cpu_disable_lazy_restore(unsigned int cpu) | |
73 | { | |
36b544dc | 74 | per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; |
1c927eea RR |
75 | } |
76 | ||
77 | static inline int fpu_lazy_restore(struct task_struct *new, unsigned int cpu) | |
78 | { | |
36b544dc | 79 | return &new->thread.fpu == this_cpu_read_stable(fpu_fpregs_owner_ctx) && |
1c927eea RR |
80 | cpu == new->thread.fpu.last_cpu; |
81 | } | |
82 | ||
050902c0 SS |
83 | static inline int is_ia32_compat_frame(void) |
84 | { | |
85 | return config_enabled(CONFIG_IA32_EMULATION) && | |
86 | test_thread_flag(TIF_IA32); | |
87 | } | |
88 | ||
89 | static inline int is_ia32_frame(void) | |
90 | { | |
91 | return config_enabled(CONFIG_X86_32) || is_ia32_compat_frame(); | |
92 | } | |
93 | ||
94 | static inline int is_x32_frame(void) | |
95 | { | |
96 | return config_enabled(CONFIG_X86_X32_ABI) && test_thread_flag(TIF_X32); | |
97 | } | |
98 | ||
1361b83a LT |
99 | #define X87_FSW_ES (1 << 7) /* Exception Summary */ |
100 | ||
5d2bd700 SS |
101 | static __always_inline __pure bool use_eager_fpu(void) |
102 | { | |
c6b40691 | 103 | return static_cpu_has_safe(X86_FEATURE_EAGER_FPU); |
5d2bd700 SS |
104 | } |
105 | ||
1361b83a LT |
106 | static __always_inline __pure bool use_xsaveopt(void) |
107 | { | |
c6b40691 | 108 | return static_cpu_has_safe(X86_FEATURE_XSAVEOPT); |
1361b83a LT |
109 | } |
110 | ||
111 | static __always_inline __pure bool use_xsave(void) | |
112 | { | |
c6b40691 | 113 | return static_cpu_has_safe(X86_FEATURE_XSAVE); |
1361b83a LT |
114 | } |
115 | ||
116 | static __always_inline __pure bool use_fxsr(void) | |
117 | { | |
c6b40691 | 118 | return static_cpu_has_safe(X86_FEATURE_FXSR); |
1361b83a LT |
119 | } |
120 | ||
5d2bd700 SS |
121 | static inline void fx_finit(struct i387_fxsave_struct *fx) |
122 | { | |
5d2bd700 | 123 | fx->cwd = 0x37f; |
a8615af4 | 124 | fx->mxcsr = MXCSR_DEFAULT; |
5d2bd700 SS |
125 | } |
126 | ||
1361b83a LT |
127 | extern void __sanitize_i387_state(struct task_struct *); |
128 | ||
129 | static inline void sanitize_i387_state(struct task_struct *tsk) | |
130 | { | |
131 | if (!use_xsaveopt()) | |
132 | return; | |
133 | __sanitize_i387_state(tsk); | |
134 | } | |
135 | ||
49b8c695 PA |
136 | #define user_insn(insn, output, input...) \ |
137 | ({ \ | |
138 | int err; \ | |
139 | asm volatile(ASM_STAC "\n" \ | |
140 | "1:" #insn "\n\t" \ | |
141 | "2: " ASM_CLAC "\n" \ | |
142 | ".section .fixup,\"ax\"\n" \ | |
143 | "3: movl $-1,%[err]\n" \ | |
144 | " jmp 2b\n" \ | |
145 | ".previous\n" \ | |
146 | _ASM_EXTABLE(1b, 3b) \ | |
147 | : [err] "=r" (err), output \ | |
148 | : "0"(0), input); \ | |
149 | err; \ | |
150 | }) | |
151 | ||
0ca5bd0d SS |
152 | #define check_insn(insn, output, input...) \ |
153 | ({ \ | |
154 | int err; \ | |
155 | asm volatile("1:" #insn "\n\t" \ | |
156 | "2:\n" \ | |
157 | ".section .fixup,\"ax\"\n" \ | |
158 | "3: movl $-1,%[err]\n" \ | |
159 | " jmp 2b\n" \ | |
160 | ".previous\n" \ | |
161 | _ASM_EXTABLE(1b, 3b) \ | |
162 | : [err] "=r" (err), output \ | |
163 | : "0"(0), input); \ | |
164 | err; \ | |
165 | }) | |
166 | ||
167 | static inline int fsave_user(struct i387_fsave_struct __user *fx) | |
1361b83a | 168 | { |
49b8c695 | 169 | return user_insn(fnsave %[fx]; fwait, [fx] "=m" (*fx), "m" (*fx)); |
1361b83a LT |
170 | } |
171 | ||
172 | static inline int fxsave_user(struct i387_fxsave_struct __user *fx) | |
173 | { | |
0ca5bd0d | 174 | if (config_enabled(CONFIG_X86_32)) |
49b8c695 | 175 | return user_insn(fxsave %[fx], [fx] "=m" (*fx), "m" (*fx)); |
0ca5bd0d | 176 | else if (config_enabled(CONFIG_AS_FXSAVEQ)) |
49b8c695 | 177 | return user_insn(fxsaveq %[fx], [fx] "=m" (*fx), "m" (*fx)); |
1361b83a | 178 | |
0ca5bd0d | 179 | /* See comment in fpu_fxsave() below. */ |
49b8c695 | 180 | return user_insn(rex64/fxsave (%[fx]), "=m" (*fx), [fx] "R" (fx)); |
1361b83a LT |
181 | } |
182 | ||
0ca5bd0d | 183 | static inline int fxrstor_checking(struct i387_fxsave_struct *fx) |
1361b83a | 184 | { |
0ca5bd0d SS |
185 | if (config_enabled(CONFIG_X86_32)) |
186 | return check_insn(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx)); | |
187 | else if (config_enabled(CONFIG_AS_FXSAVEQ)) | |
188 | return check_insn(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx)); | |
1361b83a | 189 | |
0ca5bd0d SS |
190 | /* See comment in fpu_fxsave() below. */ |
191 | return check_insn(rex64/fxrstor (%[fx]), "=m" (*fx), [fx] "R" (fx), | |
192 | "m" (*fx)); | |
1361b83a LT |
193 | } |
194 | ||
e139e955 PA |
195 | static inline int fxrstor_user(struct i387_fxsave_struct __user *fx) |
196 | { | |
197 | if (config_enabled(CONFIG_X86_32)) | |
198 | return user_insn(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx)); | |
199 | else if (config_enabled(CONFIG_AS_FXSAVEQ)) | |
200 | return user_insn(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx)); | |
201 | ||
202 | /* See comment in fpu_fxsave() below. */ | |
203 | return user_insn(rex64/fxrstor (%[fx]), "=m" (*fx), [fx] "R" (fx), | |
204 | "m" (*fx)); | |
205 | } | |
206 | ||
0ca5bd0d | 207 | static inline int frstor_checking(struct i387_fsave_struct *fx) |
1361b83a | 208 | { |
0ca5bd0d | 209 | return check_insn(frstor %[fx], "=m" (*fx), [fx] "m" (*fx)); |
e139e955 PA |
210 | } |
211 | ||
212 | static inline int frstor_user(struct i387_fsave_struct __user *fx) | |
213 | { | |
214 | return user_insn(frstor %[fx], "=m" (*fx), [fx] "m" (*fx)); | |
1361b83a LT |
215 | } |
216 | ||
217 | static inline void fpu_fxsave(struct fpu *fpu) | |
218 | { | |
0ca5bd0d SS |
219 | if (config_enabled(CONFIG_X86_32)) |
220 | asm volatile( "fxsave %[fx]" : [fx] "=m" (fpu->state->fxsave)); | |
221 | else if (config_enabled(CONFIG_AS_FXSAVEQ)) | |
6ca7a8a1 | 222 | asm volatile("fxsaveq %[fx]" : [fx] "=m" (fpu->state->fxsave)); |
0ca5bd0d SS |
223 | else { |
224 | /* Using "rex64; fxsave %0" is broken because, if the memory | |
225 | * operand uses any extended registers for addressing, a second | |
226 | * REX prefix will be generated (to the assembler, rex64 | |
227 | * followed by semicolon is a separate instruction), and hence | |
228 | * the 64-bitness is lost. | |
229 | * | |
230 | * Using "fxsaveq %0" would be the ideal choice, but is only | |
231 | * supported starting with gas 2.16. | |
232 | * | |
233 | * Using, as a workaround, the properly prefixed form below | |
234 | * isn't accepted by any binutils version so far released, | |
235 | * complaining that the same type of prefix is used twice if | |
236 | * an extended register is needed for addressing (fix submitted | |
237 | * to mainline 2005-11-21). | |
238 | * | |
239 | * asm volatile("rex64/fxsave %0" : "=m" (fpu->state->fxsave)); | |
240 | * | |
241 | * This, however, we can work around by forcing the compiler to | |
242 | * select an addressing mode that doesn't require extended | |
243 | * registers. | |
244 | */ | |
245 | asm volatile( "rex64/fxsave (%[fx])" | |
246 | : "=m" (fpu->state->fxsave) | |
247 | : [fx] "R" (&fpu->state->fxsave)); | |
248 | } | |
1361b83a LT |
249 | } |
250 | ||
1361b83a LT |
251 | /* |
252 | * These must be called with preempt disabled. Returns | |
253 | * 'true' if the FPU state is still intact. | |
254 | */ | |
255 | static inline int fpu_save_init(struct fpu *fpu) | |
256 | { | |
257 | if (use_xsave()) { | |
0afc4a94 | 258 | xsave_state(&fpu->state->xsave); |
1361b83a LT |
259 | |
260 | /* | |
261 | * xsave header may indicate the init state of the FP. | |
262 | */ | |
263 | if (!(fpu->state->xsave.xsave_hdr.xstate_bv & XSTATE_FP)) | |
264 | return 1; | |
265 | } else if (use_fxsr()) { | |
266 | fpu_fxsave(fpu); | |
267 | } else { | |
268 | asm volatile("fnsave %[fx]; fwait" | |
269 | : [fx] "=m" (fpu->state->fsave)); | |
270 | return 0; | |
271 | } | |
272 | ||
273 | /* | |
274 | * If exceptions are pending, we need to clear them so | |
275 | * that we don't randomly get exceptions later. | |
276 | * | |
277 | * FIXME! Is this perhaps only true for the old-style | |
278 | * irq13 case? Maybe we could leave the x87 state | |
279 | * intact otherwise? | |
280 | */ | |
281 | if (unlikely(fpu->state->fxsave.swd & X87_FSW_ES)) { | |
282 | asm volatile("fnclex"); | |
283 | return 0; | |
284 | } | |
285 | return 1; | |
286 | } | |
287 | ||
1361b83a LT |
288 | static inline int fpu_restore_checking(struct fpu *fpu) |
289 | { | |
290 | if (use_xsave()) | |
0ca5bd0d SS |
291 | return fpu_xrstor_checking(&fpu->state->xsave); |
292 | else if (use_fxsr()) | |
293 | return fxrstor_checking(&fpu->state->fxsave); | |
1361b83a | 294 | else |
0ca5bd0d | 295 | return frstor_checking(&fpu->state->fsave); |
1361b83a LT |
296 | } |
297 | ||
298 | static inline int restore_fpu_checking(struct task_struct *tsk) | |
299 | { | |
6ca7a8a1 BP |
300 | /* |
301 | * AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception is | |
302 | * pending. Clear the x87 state here by setting it to fixed values. | |
303 | * "m" is a random variable that should be in L1. | |
304 | */ | |
9b13a93d | 305 | if (unlikely(static_cpu_has_bug_safe(X86_BUG_FXSAVE_LEAK))) { |
26bef131 LT |
306 | asm volatile( |
307 | "fnclex\n\t" | |
308 | "emms\n\t" | |
309 | "fildl %P[addr]" /* set F?P to defined value */ | |
310 | : : [addr] "m" (tsk->thread.fpu.has_fpu)); | |
311 | } | |
1361b83a LT |
312 | |
313 | return fpu_restore_checking(&tsk->thread.fpu); | |
314 | } | |
315 | ||
1361b83a | 316 | /* Must be paired with an 'stts' after! */ |
36fe6175 | 317 | static inline void __thread_clear_has_fpu(struct fpu *fpu) |
1361b83a | 318 | { |
36fe6175 | 319 | fpu->has_fpu = 0; |
36b544dc | 320 | this_cpu_write(fpu_fpregs_owner_ctx, NULL); |
1361b83a LT |
321 | } |
322 | ||
323 | /* Must be paired with a 'clts' before! */ | |
c0311f63 | 324 | static inline void __thread_set_has_fpu(struct fpu *fpu) |
1361b83a | 325 | { |
c0311f63 IM |
326 | fpu->has_fpu = 1; |
327 | this_cpu_write(fpu_fpregs_owner_ctx, fpu); | |
1361b83a LT |
328 | } |
329 | ||
330 | /* | |
331 | * Encapsulate the CR0.TS handling together with the | |
332 | * software flag. | |
333 | * | |
334 | * These generally need preemption protection to work, | |
335 | * do try to avoid using these on their own. | |
336 | */ | |
35191e3f | 337 | static inline void __thread_fpu_end(struct fpu *fpu) |
1361b83a | 338 | { |
35191e3f | 339 | __thread_clear_has_fpu(fpu); |
5d2bd700 | 340 | if (!use_eager_fpu()) |
304bceda | 341 | stts(); |
1361b83a LT |
342 | } |
343 | ||
4540d3fa | 344 | static inline void __thread_fpu_begin(struct fpu *fpu) |
1361b83a | 345 | { |
31d96338 | 346 | if (!use_eager_fpu()) |
304bceda | 347 | clts(); |
4540d3fa | 348 | __thread_set_has_fpu(fpu); |
1361b83a LT |
349 | } |
350 | ||
ca6787ba | 351 | static inline void drop_fpu(struct fpu *fpu) |
304bceda | 352 | { |
d2d0ac9a BP |
353 | /* |
354 | * Forget coprocessor state.. | |
355 | */ | |
356 | preempt_disable(); | |
ca6787ba | 357 | fpu->counter = 0; |
d2d0ac9a | 358 | |
276983f8 | 359 | if (fpu->has_fpu) { |
304bceda SS |
360 | /* Ignore delayed exceptions from user space */ |
361 | asm volatile("1: fwait\n" | |
362 | "2:\n" | |
363 | _ASM_EXTABLE(1b, 2b)); | |
35191e3f | 364 | __thread_fpu_end(fpu); |
304bceda | 365 | } |
304bceda | 366 | |
c5bedc68 | 367 | fpu->fpstate_active = 0; |
4c138410 | 368 | |
304bceda SS |
369 | preempt_enable(); |
370 | } | |
371 | ||
8f4d8186 ON |
372 | static inline void restore_init_xstate(void) |
373 | { | |
374 | if (use_xsave()) | |
375 | xrstor_state(init_xstate_buf, -1); | |
376 | else | |
377 | fxrstor_checking(&init_xstate_buf->i387); | |
378 | } | |
379 | ||
b85e67d1 BP |
380 | /* |
381 | * Reset the FPU state in the eager case and drop it in the lazy case (later use | |
382 | * will reinit it). | |
383 | */ | |
384 | static inline void fpu_reset_state(struct task_struct *tsk) | |
304bceda | 385 | { |
ca6787ba IM |
386 | struct fpu *fpu = &tsk->thread.fpu; |
387 | ||
5d2bd700 | 388 | if (!use_eager_fpu()) |
ca6787ba | 389 | drop_fpu(fpu); |
8f4d8186 ON |
390 | else |
391 | restore_init_xstate(); | |
304bceda SS |
392 | } |
393 | ||
1361b83a LT |
394 | /* |
395 | * FPU state switching for scheduling. | |
396 | * | |
397 | * This is a two-stage process: | |
398 | * | |
399 | * - switch_fpu_prepare() saves the old state and | |
400 | * sets the new state of the CR0.TS bit. This is | |
401 | * done within the context of the old process. | |
402 | * | |
403 | * - switch_fpu_finish() restores the new state as | |
404 | * necessary. | |
405 | */ | |
406 | typedef struct { int preload; } fpu_switch_t; | |
407 | ||
1361b83a LT |
408 | static inline fpu_switch_t switch_fpu_prepare(struct task_struct *old, struct task_struct *new, int cpu) |
409 | { | |
276983f8 | 410 | struct fpu *old_fpu = &old->thread.fpu; |
c0311f63 | 411 | struct fpu *new_fpu = &new->thread.fpu; |
1361b83a LT |
412 | fpu_switch_t fpu; |
413 | ||
304bceda SS |
414 | /* |
415 | * If the task has used the math, pre-load the FPU on xsave processors | |
416 | * or if the past 5 consecutive context-switches used math. | |
417 | */ | |
c5bedc68 | 418 | fpu.preload = new_fpu->fpstate_active && |
c0c2803d | 419 | (use_eager_fpu() || new->thread.fpu.counter > 5); |
1361ef29 | 420 | |
276983f8 | 421 | if (old_fpu->has_fpu) { |
6522d783 | 422 | if (!fpu_save_init(&old->thread.fpu)) |
eb6a3251 | 423 | old->thread.fpu.last_cpu = -1; |
1361ef29 RR |
424 | else |
425 | old->thread.fpu.last_cpu = cpu; | |
426 | ||
36b544dc | 427 | /* But leave fpu_fpregs_owner_ctx! */ |
1361ef29 | 428 | old->thread.fpu.has_fpu = 0; |
1361b83a LT |
429 | |
430 | /* Don't change CR0.TS if we just switch! */ | |
431 | if (fpu.preload) { | |
c0c2803d | 432 | new->thread.fpu.counter++; |
c0311f63 | 433 | __thread_set_has_fpu(new_fpu); |
1361b83a | 434 | prefetch(new->thread.fpu.state); |
5d2bd700 | 435 | } else if (!use_eager_fpu()) |
1361b83a LT |
436 | stts(); |
437 | } else { | |
c0c2803d | 438 | old->thread.fpu.counter = 0; |
eb6a3251 | 439 | old->thread.fpu.last_cpu = -1; |
1361b83a | 440 | if (fpu.preload) { |
c0c2803d | 441 | new->thread.fpu.counter++; |
728e53fe | 442 | if (fpu_lazy_restore(new, cpu)) |
1361b83a LT |
443 | fpu.preload = 0; |
444 | else | |
445 | prefetch(new->thread.fpu.state); | |
4540d3fa | 446 | __thread_fpu_begin(new_fpu); |
1361b83a LT |
447 | } |
448 | } | |
449 | return fpu; | |
450 | } | |
451 | ||
452 | /* | |
453 | * By the time this gets called, we've already cleared CR0.TS and | |
454 | * given the process the FPU if we are going to preload the FPU | |
455 | * state - all we need to do is to conditionally restore the register | |
456 | * state itself. | |
457 | */ | |
458 | static inline void switch_fpu_finish(struct task_struct *new, fpu_switch_t fpu) | |
459 | { | |
460 | if (fpu.preload) { | |
461 | if (unlikely(restore_fpu_checking(new))) | |
b85e67d1 | 462 | fpu_reset_state(new); |
1361b83a LT |
463 | } |
464 | } | |
465 | ||
466 | /* | |
467 | * Signal frame handlers... | |
468 | */ | |
72a671ce SS |
469 | extern int save_xstate_sig(void __user *buf, void __user *fx, int size); |
470 | extern int __restore_xstate_sig(void __user *buf, void __user *fx, int size); | |
1361b83a | 471 | |
72a671ce | 472 | static inline int xstate_sigframe_size(void) |
1361b83a | 473 | { |
72a671ce SS |
474 | return use_xsave() ? xstate_size + FP_XSTATE_MAGIC2_SIZE : xstate_size; |
475 | } | |
476 | ||
477 | static inline int restore_xstate_sig(void __user *buf, int ia32_frame) | |
478 | { | |
479 | void __user *buf_fx = buf; | |
480 | int size = xstate_sigframe_size(); | |
481 | ||
482 | if (ia32_frame && use_fxsr()) { | |
483 | buf_fx = buf + sizeof(struct i387_fsave_struct); | |
484 | size += sizeof(struct i387_fsave_struct); | |
1361b83a | 485 | } |
72a671ce SS |
486 | |
487 | return __restore_xstate_sig(buf, buf_fx, size); | |
1361b83a LT |
488 | } |
489 | ||
490 | /* | |
fb14b4ea | 491 | * Needs to be preemption-safe. |
1361b83a | 492 | * |
377ffbcc | 493 | * NOTE! user_fpu_begin() must be used only immediately before restoring |
fb14b4ea ON |
494 | * the save state. It does not do any saving/restoring on its own. In |
495 | * lazy FPU mode, it is just an optimization to avoid a #NM exception, | |
496 | * the task can lose the FPU right after preempt_enable(). | |
1361b83a | 497 | */ |
1361b83a LT |
498 | static inline void user_fpu_begin(void) |
499 | { | |
4540d3fa IM |
500 | struct fpu *fpu = ¤t->thread.fpu; |
501 | ||
1361b83a LT |
502 | preempt_disable(); |
503 | if (!user_has_fpu()) | |
4540d3fa | 504 | __thread_fpu_begin(fpu); |
1361b83a LT |
505 | preempt_enable(); |
506 | } | |
507 | ||
5d2bd700 SS |
508 | static inline void __save_fpu(struct task_struct *tsk) |
509 | { | |
f41d830f FY |
510 | if (use_xsave()) { |
511 | if (unlikely(system_state == SYSTEM_BOOTING)) | |
3e261c14 | 512 | xsave_state_booting(&tsk->thread.fpu.state->xsave); |
f41d830f | 513 | else |
3e261c14 | 514 | xsave_state(&tsk->thread.fpu.state->xsave); |
f41d830f | 515 | } else |
5d2bd700 SS |
516 | fpu_fxsave(&tsk->thread.fpu); |
517 | } | |
518 | ||
1361b83a LT |
519 | /* |
520 | * i387 state interaction | |
521 | */ | |
522 | static inline unsigned short get_fpu_cwd(struct task_struct *tsk) | |
523 | { | |
524 | if (cpu_has_fxsr) { | |
525 | return tsk->thread.fpu.state->fxsave.cwd; | |
526 | } else { | |
527 | return (unsigned short)tsk->thread.fpu.state->fsave.cwd; | |
528 | } | |
529 | } | |
530 | ||
531 | static inline unsigned short get_fpu_swd(struct task_struct *tsk) | |
532 | { | |
533 | if (cpu_has_fxsr) { | |
534 | return tsk->thread.fpu.state->fxsave.swd; | |
535 | } else { | |
536 | return (unsigned short)tsk->thread.fpu.state->fsave.swd; | |
537 | } | |
538 | } | |
539 | ||
540 | static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk) | |
541 | { | |
542 | if (cpu_has_xmm) { | |
543 | return tsk->thread.fpu.state->fxsave.mxcsr; | |
544 | } else { | |
545 | return MXCSR_DEFAULT; | |
546 | } | |
547 | } | |
548 | ||
8ffb53ab IM |
549 | extern void fpstate_cache_init(void); |
550 | ||
ed97b085 | 551 | extern int fpstate_alloc(struct fpu *fpu); |
5a12bf63 | 552 | extern void fpstate_free(struct fpu *fpu); |
a752b53d | 553 | extern int fpu__copy(struct task_struct *dst, struct task_struct *src); |
1361b83a | 554 | |
72a671ce SS |
555 | static inline unsigned long |
556 | alloc_mathframe(unsigned long sp, int ia32_frame, unsigned long *buf_fx, | |
557 | unsigned long *size) | |
558 | { | |
559 | unsigned long frame_size = xstate_sigframe_size(); | |
560 | ||
561 | *buf_fx = sp = round_down(sp - frame_size, 64); | |
562 | if (ia32_frame && use_fxsr()) { | |
563 | frame_size += sizeof(struct i387_fsave_struct); | |
564 | sp -= sizeof(struct i387_fsave_struct); | |
565 | } | |
566 | ||
567 | *size = frame_size; | |
568 | return sp; | |
569 | } | |
1361b83a LT |
570 | |
571 | #endif |