Commit | Line | Data |
---|---|---|
1361b83a LT |
1 | /* |
2 | * Copyright (C) 1994 Linus Torvalds | |
3 | * | |
4 | * Pentium III FXSR, SSE support | |
5 | * General FPU state handling cleanups | |
6 | * Gareth Hughes <gareth@valinux.com>, May 2000 | |
7 | * x86-64 work by Andi Kleen 2002 | |
8 | */ | |
9 | ||
10 | #ifndef _FPU_INTERNAL_H | |
11 | #define _FPU_INTERNAL_H | |
12 | ||
13 | #include <linux/kernel_stat.h> | |
14 | #include <linux/regset.h> | |
050902c0 | 15 | #include <linux/compat.h> |
1361b83a LT |
16 | #include <linux/slab.h> |
17 | #include <asm/asm.h> | |
18 | #include <asm/cpufeature.h> | |
19 | #include <asm/processor.h> | |
20 | #include <asm/sigcontext.h> | |
21 | #include <asm/user.h> | |
22 | #include <asm/uaccess.h> | |
23 | #include <asm/xsave.h> | |
49b8c695 | 24 | #include <asm/smap.h> |
1361b83a | 25 | |
72a671ce SS |
26 | #ifdef CONFIG_X86_64 |
27 | # include <asm/sigcontext32.h> | |
28 | # include <asm/user32.h> | |
235b8022 AV |
29 | struct ksignal; |
30 | int ia32_setup_rt_frame(int sig, struct ksignal *ksig, | |
72a671ce | 31 | compat_sigset_t *set, struct pt_regs *regs); |
235b8022 | 32 | int ia32_setup_frame(int sig, struct ksignal *ksig, |
72a671ce SS |
33 | compat_sigset_t *set, struct pt_regs *regs); |
34 | #else | |
35 | # define user_i387_ia32_struct user_i387_struct | |
36 | # define user32_fxsr_struct user_fxsr_struct | |
37 | # define ia32_setup_frame __setup_frame | |
38 | # define ia32_setup_rt_frame __setup_rt_frame | |
39 | #endif | |
40 | ||
41 | extern unsigned int mxcsr_feature_mask; | |
1361b83a | 42 | extern void fpu_init(void); |
5d2bd700 | 43 | extern void eager_fpu_init(void); |
1361b83a LT |
44 | |
45 | DECLARE_PER_CPU(struct task_struct *, fpu_owner_task); | |
46 | ||
72a671ce SS |
47 | extern void convert_from_fxsr(struct user_i387_ia32_struct *env, |
48 | struct task_struct *tsk); | |
49 | extern void convert_to_fxsr(struct task_struct *tsk, | |
50 | const struct user_i387_ia32_struct *env); | |
51 | ||
1361b83a LT |
52 | extern user_regset_active_fn fpregs_active, xfpregs_active; |
53 | extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get, | |
54 | xstateregs_get; | |
55 | extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set, | |
56 | xstateregs_set; | |
57 | ||
1361b83a LT |
58 | /* |
59 | * xstateregs_active == fpregs_active. Please refer to the comment | |
60 | * at the definition of fpregs_active. | |
61 | */ | |
62 | #define xstateregs_active fpregs_active | |
63 | ||
1361b83a LT |
64 | #ifdef CONFIG_MATH_EMULATION |
65 | extern void finit_soft_fpu(struct i387_soft_struct *soft); | |
66 | #else | |
67 | static inline void finit_soft_fpu(struct i387_soft_struct *soft) {} | |
68 | #endif | |
69 | ||
1c927eea RR |
70 | /* |
71 | * Must be run with preemption disabled: this clears the fpu_owner_task, | |
72 | * on this CPU. | |
73 | * | |
74 | * This will disable any lazy FPU state restore of the current FPU state, | |
75 | * but if the current thread owns the FPU, it will still be saved by. | |
76 | */ | |
77 | static inline void __cpu_disable_lazy_restore(unsigned int cpu) | |
78 | { | |
79 | per_cpu(fpu_owner_task, cpu) = NULL; | |
80 | } | |
81 | ||
33e03ded RR |
82 | /* |
83 | * Used to indicate that the FPU state in memory is newer than the FPU | |
84 | * state in registers, and the FPU state should be reloaded next time the | |
85 | * task is run. Only safe on the current task, or non-running tasks. | |
86 | */ | |
87 | static inline void task_disable_lazy_fpu_restore(struct task_struct *tsk) | |
88 | { | |
89 | tsk->thread.fpu.last_cpu = ~0; | |
90 | } | |
91 | ||
1c927eea RR |
92 | static inline int fpu_lazy_restore(struct task_struct *new, unsigned int cpu) |
93 | { | |
94 | return new == this_cpu_read_stable(fpu_owner_task) && | |
95 | cpu == new->thread.fpu.last_cpu; | |
96 | } | |
97 | ||
050902c0 SS |
98 | static inline int is_ia32_compat_frame(void) |
99 | { | |
100 | return config_enabled(CONFIG_IA32_EMULATION) && | |
101 | test_thread_flag(TIF_IA32); | |
102 | } | |
103 | ||
104 | static inline int is_ia32_frame(void) | |
105 | { | |
106 | return config_enabled(CONFIG_X86_32) || is_ia32_compat_frame(); | |
107 | } | |
108 | ||
109 | static inline int is_x32_frame(void) | |
110 | { | |
111 | return config_enabled(CONFIG_X86_X32_ABI) && test_thread_flag(TIF_X32); | |
112 | } | |
113 | ||
1361b83a LT |
114 | #define X87_FSW_ES (1 << 7) /* Exception Summary */ |
115 | ||
5d2bd700 SS |
116 | static __always_inline __pure bool use_eager_fpu(void) |
117 | { | |
c6b40691 | 118 | return static_cpu_has_safe(X86_FEATURE_EAGER_FPU); |
5d2bd700 SS |
119 | } |
120 | ||
1361b83a LT |
121 | static __always_inline __pure bool use_xsaveopt(void) |
122 | { | |
c6b40691 | 123 | return static_cpu_has_safe(X86_FEATURE_XSAVEOPT); |
1361b83a LT |
124 | } |
125 | ||
126 | static __always_inline __pure bool use_xsave(void) | |
127 | { | |
c6b40691 | 128 | return static_cpu_has_safe(X86_FEATURE_XSAVE); |
1361b83a LT |
129 | } |
130 | ||
131 | static __always_inline __pure bool use_fxsr(void) | |
132 | { | |
c6b40691 | 133 | return static_cpu_has_safe(X86_FEATURE_FXSR); |
1361b83a LT |
134 | } |
135 | ||
5d2bd700 SS |
136 | static inline void fx_finit(struct i387_fxsave_struct *fx) |
137 | { | |
5d2bd700 | 138 | fx->cwd = 0x37f; |
a8615af4 | 139 | fx->mxcsr = MXCSR_DEFAULT; |
5d2bd700 SS |
140 | } |
141 | ||
1361b83a LT |
142 | extern void __sanitize_i387_state(struct task_struct *); |
143 | ||
144 | static inline void sanitize_i387_state(struct task_struct *tsk) | |
145 | { | |
146 | if (!use_xsaveopt()) | |
147 | return; | |
148 | __sanitize_i387_state(tsk); | |
149 | } | |
150 | ||
49b8c695 PA |
151 | #define user_insn(insn, output, input...) \ |
152 | ({ \ | |
153 | int err; \ | |
154 | asm volatile(ASM_STAC "\n" \ | |
155 | "1:" #insn "\n\t" \ | |
156 | "2: " ASM_CLAC "\n" \ | |
157 | ".section .fixup,\"ax\"\n" \ | |
158 | "3: movl $-1,%[err]\n" \ | |
159 | " jmp 2b\n" \ | |
160 | ".previous\n" \ | |
161 | _ASM_EXTABLE(1b, 3b) \ | |
162 | : [err] "=r" (err), output \ | |
163 | : "0"(0), input); \ | |
164 | err; \ | |
165 | }) | |
166 | ||
0ca5bd0d SS |
167 | #define check_insn(insn, output, input...) \ |
168 | ({ \ | |
169 | int err; \ | |
170 | asm volatile("1:" #insn "\n\t" \ | |
171 | "2:\n" \ | |
172 | ".section .fixup,\"ax\"\n" \ | |
173 | "3: movl $-1,%[err]\n" \ | |
174 | " jmp 2b\n" \ | |
175 | ".previous\n" \ | |
176 | _ASM_EXTABLE(1b, 3b) \ | |
177 | : [err] "=r" (err), output \ | |
178 | : "0"(0), input); \ | |
179 | err; \ | |
180 | }) | |
181 | ||
182 | static inline int fsave_user(struct i387_fsave_struct __user *fx) | |
1361b83a | 183 | { |
49b8c695 | 184 | return user_insn(fnsave %[fx]; fwait, [fx] "=m" (*fx), "m" (*fx)); |
1361b83a LT |
185 | } |
186 | ||
187 | static inline int fxsave_user(struct i387_fxsave_struct __user *fx) | |
188 | { | |
0ca5bd0d | 189 | if (config_enabled(CONFIG_X86_32)) |
49b8c695 | 190 | return user_insn(fxsave %[fx], [fx] "=m" (*fx), "m" (*fx)); |
0ca5bd0d | 191 | else if (config_enabled(CONFIG_AS_FXSAVEQ)) |
49b8c695 | 192 | return user_insn(fxsaveq %[fx], [fx] "=m" (*fx), "m" (*fx)); |
1361b83a | 193 | |
0ca5bd0d | 194 | /* See comment in fpu_fxsave() below. */ |
49b8c695 | 195 | return user_insn(rex64/fxsave (%[fx]), "=m" (*fx), [fx] "R" (fx)); |
1361b83a LT |
196 | } |
197 | ||
0ca5bd0d | 198 | static inline int fxrstor_checking(struct i387_fxsave_struct *fx) |
1361b83a | 199 | { |
0ca5bd0d SS |
200 | if (config_enabled(CONFIG_X86_32)) |
201 | return check_insn(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx)); | |
202 | else if (config_enabled(CONFIG_AS_FXSAVEQ)) | |
203 | return check_insn(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx)); | |
1361b83a | 204 | |
0ca5bd0d SS |
205 | /* See comment in fpu_fxsave() below. */ |
206 | return check_insn(rex64/fxrstor (%[fx]), "=m" (*fx), [fx] "R" (fx), | |
207 | "m" (*fx)); | |
1361b83a LT |
208 | } |
209 | ||
e139e955 PA |
210 | static inline int fxrstor_user(struct i387_fxsave_struct __user *fx) |
211 | { | |
212 | if (config_enabled(CONFIG_X86_32)) | |
213 | return user_insn(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx)); | |
214 | else if (config_enabled(CONFIG_AS_FXSAVEQ)) | |
215 | return user_insn(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx)); | |
216 | ||
217 | /* See comment in fpu_fxsave() below. */ | |
218 | return user_insn(rex64/fxrstor (%[fx]), "=m" (*fx), [fx] "R" (fx), | |
219 | "m" (*fx)); | |
220 | } | |
221 | ||
0ca5bd0d | 222 | static inline int frstor_checking(struct i387_fsave_struct *fx) |
1361b83a | 223 | { |
0ca5bd0d | 224 | return check_insn(frstor %[fx], "=m" (*fx), [fx] "m" (*fx)); |
e139e955 PA |
225 | } |
226 | ||
227 | static inline int frstor_user(struct i387_fsave_struct __user *fx) | |
228 | { | |
229 | return user_insn(frstor %[fx], "=m" (*fx), [fx] "m" (*fx)); | |
1361b83a LT |
230 | } |
231 | ||
232 | static inline void fpu_fxsave(struct fpu *fpu) | |
233 | { | |
0ca5bd0d SS |
234 | if (config_enabled(CONFIG_X86_32)) |
235 | asm volatile( "fxsave %[fx]" : [fx] "=m" (fpu->state->fxsave)); | |
236 | else if (config_enabled(CONFIG_AS_FXSAVEQ)) | |
6ca7a8a1 | 237 | asm volatile("fxsaveq %[fx]" : [fx] "=m" (fpu->state->fxsave)); |
0ca5bd0d SS |
238 | else { |
239 | /* Using "rex64; fxsave %0" is broken because, if the memory | |
240 | * operand uses any extended registers for addressing, a second | |
241 | * REX prefix will be generated (to the assembler, rex64 | |
242 | * followed by semicolon is a separate instruction), and hence | |
243 | * the 64-bitness is lost. | |
244 | * | |
245 | * Using "fxsaveq %0" would be the ideal choice, but is only | |
246 | * supported starting with gas 2.16. | |
247 | * | |
248 | * Using, as a workaround, the properly prefixed form below | |
249 | * isn't accepted by any binutils version so far released, | |
250 | * complaining that the same type of prefix is used twice if | |
251 | * an extended register is needed for addressing (fix submitted | |
252 | * to mainline 2005-11-21). | |
253 | * | |
254 | * asm volatile("rex64/fxsave %0" : "=m" (fpu->state->fxsave)); | |
255 | * | |
256 | * This, however, we can work around by forcing the compiler to | |
257 | * select an addressing mode that doesn't require extended | |
258 | * registers. | |
259 | */ | |
260 | asm volatile( "rex64/fxsave (%[fx])" | |
261 | : "=m" (fpu->state->fxsave) | |
262 | : [fx] "R" (&fpu->state->fxsave)); | |
263 | } | |
1361b83a LT |
264 | } |
265 | ||
1361b83a LT |
266 | /* |
267 | * These must be called with preempt disabled. Returns | |
268 | * 'true' if the FPU state is still intact. | |
269 | */ | |
270 | static inline int fpu_save_init(struct fpu *fpu) | |
271 | { | |
272 | if (use_xsave()) { | |
273 | fpu_xsave(fpu); | |
274 | ||
275 | /* | |
276 | * xsave header may indicate the init state of the FP. | |
277 | */ | |
278 | if (!(fpu->state->xsave.xsave_hdr.xstate_bv & XSTATE_FP)) | |
279 | return 1; | |
280 | } else if (use_fxsr()) { | |
281 | fpu_fxsave(fpu); | |
282 | } else { | |
283 | asm volatile("fnsave %[fx]; fwait" | |
284 | : [fx] "=m" (fpu->state->fsave)); | |
285 | return 0; | |
286 | } | |
287 | ||
288 | /* | |
289 | * If exceptions are pending, we need to clear them so | |
290 | * that we don't randomly get exceptions later. | |
291 | * | |
292 | * FIXME! Is this perhaps only true for the old-style | |
293 | * irq13 case? Maybe we could leave the x87 state | |
294 | * intact otherwise? | |
295 | */ | |
296 | if (unlikely(fpu->state->fxsave.swd & X87_FSW_ES)) { | |
297 | asm volatile("fnclex"); | |
298 | return 0; | |
299 | } | |
300 | return 1; | |
301 | } | |
302 | ||
303 | static inline int __save_init_fpu(struct task_struct *tsk) | |
304 | { | |
305 | return fpu_save_init(&tsk->thread.fpu); | |
306 | } | |
307 | ||
1361b83a LT |
308 | static inline int fpu_restore_checking(struct fpu *fpu) |
309 | { | |
310 | if (use_xsave()) | |
0ca5bd0d SS |
311 | return fpu_xrstor_checking(&fpu->state->xsave); |
312 | else if (use_fxsr()) | |
313 | return fxrstor_checking(&fpu->state->fxsave); | |
1361b83a | 314 | else |
0ca5bd0d | 315 | return frstor_checking(&fpu->state->fsave); |
1361b83a LT |
316 | } |
317 | ||
318 | static inline int restore_fpu_checking(struct task_struct *tsk) | |
319 | { | |
6ca7a8a1 BP |
320 | /* |
321 | * AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception is | |
322 | * pending. Clear the x87 state here by setting it to fixed values. | |
323 | * "m" is a random variable that should be in L1. | |
324 | */ | |
9b13a93d | 325 | if (unlikely(static_cpu_has_bug_safe(X86_BUG_FXSAVE_LEAK))) { |
26bef131 LT |
326 | asm volatile( |
327 | "fnclex\n\t" | |
328 | "emms\n\t" | |
329 | "fildl %P[addr]" /* set F?P to defined value */ | |
330 | : : [addr] "m" (tsk->thread.fpu.has_fpu)); | |
331 | } | |
1361b83a LT |
332 | |
333 | return fpu_restore_checking(&tsk->thread.fpu); | |
334 | } | |
335 | ||
336 | /* | |
337 | * Software FPU state helpers. Careful: these need to | |
338 | * be preemption protection *and* they need to be | |
339 | * properly paired with the CR0.TS changes! | |
340 | */ | |
341 | static inline int __thread_has_fpu(struct task_struct *tsk) | |
342 | { | |
343 | return tsk->thread.fpu.has_fpu; | |
344 | } | |
345 | ||
346 | /* Must be paired with an 'stts' after! */ | |
347 | static inline void __thread_clear_has_fpu(struct task_struct *tsk) | |
348 | { | |
349 | tsk->thread.fpu.has_fpu = 0; | |
c6ae41e7 | 350 | this_cpu_write(fpu_owner_task, NULL); |
1361b83a LT |
351 | } |
352 | ||
353 | /* Must be paired with a 'clts' before! */ | |
354 | static inline void __thread_set_has_fpu(struct task_struct *tsk) | |
355 | { | |
356 | tsk->thread.fpu.has_fpu = 1; | |
c6ae41e7 | 357 | this_cpu_write(fpu_owner_task, tsk); |
1361b83a LT |
358 | } |
359 | ||
360 | /* | |
361 | * Encapsulate the CR0.TS handling together with the | |
362 | * software flag. | |
363 | * | |
364 | * These generally need preemption protection to work, | |
365 | * do try to avoid using these on their own. | |
366 | */ | |
367 | static inline void __thread_fpu_end(struct task_struct *tsk) | |
368 | { | |
369 | __thread_clear_has_fpu(tsk); | |
5d2bd700 | 370 | if (!use_eager_fpu()) |
304bceda | 371 | stts(); |
1361b83a LT |
372 | } |
373 | ||
374 | static inline void __thread_fpu_begin(struct task_struct *tsk) | |
375 | { | |
31d96338 | 376 | if (!use_eager_fpu()) |
304bceda | 377 | clts(); |
1361b83a LT |
378 | __thread_set_has_fpu(tsk); |
379 | } | |
380 | ||
304bceda SS |
381 | static inline void __drop_fpu(struct task_struct *tsk) |
382 | { | |
383 | if (__thread_has_fpu(tsk)) { | |
384 | /* Ignore delayed exceptions from user space */ | |
385 | asm volatile("1: fwait\n" | |
386 | "2:\n" | |
387 | _ASM_EXTABLE(1b, 2b)); | |
388 | __thread_fpu_end(tsk); | |
389 | } | |
390 | } | |
391 | ||
392 | static inline void drop_fpu(struct task_struct *tsk) | |
393 | { | |
394 | /* | |
395 | * Forget coprocessor state.. | |
396 | */ | |
397 | preempt_disable(); | |
c375f15a | 398 | tsk->thread.fpu_counter = 0; |
304bceda | 399 | __drop_fpu(tsk); |
f4c36863 | 400 | clear_stopped_child_used_math(tsk); |
304bceda SS |
401 | preempt_enable(); |
402 | } | |
403 | ||
404 | static inline void drop_init_fpu(struct task_struct *tsk) | |
405 | { | |
5d2bd700 | 406 | if (!use_eager_fpu()) |
304bceda | 407 | drop_fpu(tsk); |
5d2bd700 SS |
408 | else { |
409 | if (use_xsave()) | |
410 | xrstor_state(init_xstate_buf, -1); | |
411 | else | |
412 | fxrstor_checking(&init_xstate_buf->i387); | |
413 | } | |
304bceda SS |
414 | } |
415 | ||
1361b83a LT |
416 | /* |
417 | * FPU state switching for scheduling. | |
418 | * | |
419 | * This is a two-stage process: | |
420 | * | |
421 | * - switch_fpu_prepare() saves the old state and | |
422 | * sets the new state of the CR0.TS bit. This is | |
423 | * done within the context of the old process. | |
424 | * | |
425 | * - switch_fpu_finish() restores the new state as | |
426 | * necessary. | |
427 | */ | |
428 | typedef struct { int preload; } fpu_switch_t; | |
429 | ||
1361b83a LT |
430 | static inline fpu_switch_t switch_fpu_prepare(struct task_struct *old, struct task_struct *new, int cpu) |
431 | { | |
432 | fpu_switch_t fpu; | |
433 | ||
304bceda SS |
434 | /* |
435 | * If the task has used the math, pre-load the FPU on xsave processors | |
436 | * or if the past 5 consecutive context-switches used math. | |
437 | */ | |
1361ef29 RR |
438 | fpu.preload = tsk_used_math(new) && |
439 | (use_eager_fpu() || new->thread.fpu_counter > 5); | |
440 | ||
1361b83a LT |
441 | if (__thread_has_fpu(old)) { |
442 | if (!__save_init_fpu(old)) | |
6a5fe895 | 443 | task_disable_lazy_fpu_restore(old); |
1361ef29 RR |
444 | else |
445 | old->thread.fpu.last_cpu = cpu; | |
446 | ||
447 | /* But leave fpu_owner_task! */ | |
448 | old->thread.fpu.has_fpu = 0; | |
1361b83a LT |
449 | |
450 | /* Don't change CR0.TS if we just switch! */ | |
451 | if (fpu.preload) { | |
c375f15a | 452 | new->thread.fpu_counter++; |
1361b83a LT |
453 | __thread_set_has_fpu(new); |
454 | prefetch(new->thread.fpu.state); | |
5d2bd700 | 455 | } else if (!use_eager_fpu()) |
1361b83a LT |
456 | stts(); |
457 | } else { | |
c375f15a | 458 | old->thread.fpu_counter = 0; |
6a5fe895 | 459 | task_disable_lazy_fpu_restore(old); |
1361b83a | 460 | if (fpu.preload) { |
c375f15a | 461 | new->thread.fpu_counter++; |
728e53fe | 462 | if (fpu_lazy_restore(new, cpu)) |
1361b83a LT |
463 | fpu.preload = 0; |
464 | else | |
465 | prefetch(new->thread.fpu.state); | |
466 | __thread_fpu_begin(new); | |
467 | } | |
468 | } | |
469 | return fpu; | |
470 | } | |
471 | ||
472 | /* | |
473 | * By the time this gets called, we've already cleared CR0.TS and | |
474 | * given the process the FPU if we are going to preload the FPU | |
475 | * state - all we need to do is to conditionally restore the register | |
476 | * state itself. | |
477 | */ | |
478 | static inline void switch_fpu_finish(struct task_struct *new, fpu_switch_t fpu) | |
479 | { | |
480 | if (fpu.preload) { | |
481 | if (unlikely(restore_fpu_checking(new))) | |
304bceda | 482 | drop_init_fpu(new); |
1361b83a LT |
483 | } |
484 | } | |
485 | ||
486 | /* | |
487 | * Signal frame handlers... | |
488 | */ | |
72a671ce SS |
489 | extern int save_xstate_sig(void __user *buf, void __user *fx, int size); |
490 | extern int __restore_xstate_sig(void __user *buf, void __user *fx, int size); | |
1361b83a | 491 | |
72a671ce | 492 | static inline int xstate_sigframe_size(void) |
1361b83a | 493 | { |
72a671ce SS |
494 | return use_xsave() ? xstate_size + FP_XSTATE_MAGIC2_SIZE : xstate_size; |
495 | } | |
496 | ||
497 | static inline int restore_xstate_sig(void __user *buf, int ia32_frame) | |
498 | { | |
499 | void __user *buf_fx = buf; | |
500 | int size = xstate_sigframe_size(); | |
501 | ||
502 | if (ia32_frame && use_fxsr()) { | |
503 | buf_fx = buf + sizeof(struct i387_fsave_struct); | |
504 | size += sizeof(struct i387_fsave_struct); | |
1361b83a | 505 | } |
72a671ce SS |
506 | |
507 | return __restore_xstate_sig(buf, buf_fx, size); | |
1361b83a LT |
508 | } |
509 | ||
510 | /* | |
377ffbcc | 511 | * Need to be preemption-safe. |
1361b83a | 512 | * |
377ffbcc SS |
513 | * NOTE! user_fpu_begin() must be used only immediately before restoring |
514 | * it. This function does not do any save/restore on their own. | |
1361b83a | 515 | */ |
1361b83a LT |
516 | static inline void user_fpu_begin(void) |
517 | { | |
518 | preempt_disable(); | |
519 | if (!user_has_fpu()) | |
520 | __thread_fpu_begin(current); | |
521 | preempt_enable(); | |
522 | } | |
523 | ||
5d2bd700 SS |
524 | static inline void __save_fpu(struct task_struct *tsk) |
525 | { | |
f41d830f FY |
526 | if (use_xsave()) { |
527 | if (unlikely(system_state == SYSTEM_BOOTING)) | |
528 | xsave_state_booting(&tsk->thread.fpu.state->xsave, -1); | |
529 | else | |
530 | xsave_state(&tsk->thread.fpu.state->xsave, -1); | |
531 | } else | |
5d2bd700 SS |
532 | fpu_fxsave(&tsk->thread.fpu); |
533 | } | |
534 | ||
1361b83a LT |
535 | /* |
536 | * i387 state interaction | |
537 | */ | |
538 | static inline unsigned short get_fpu_cwd(struct task_struct *tsk) | |
539 | { | |
540 | if (cpu_has_fxsr) { | |
541 | return tsk->thread.fpu.state->fxsave.cwd; | |
542 | } else { | |
543 | return (unsigned short)tsk->thread.fpu.state->fsave.cwd; | |
544 | } | |
545 | } | |
546 | ||
547 | static inline unsigned short get_fpu_swd(struct task_struct *tsk) | |
548 | { | |
549 | if (cpu_has_fxsr) { | |
550 | return tsk->thread.fpu.state->fxsave.swd; | |
551 | } else { | |
552 | return (unsigned short)tsk->thread.fpu.state->fsave.swd; | |
553 | } | |
554 | } | |
555 | ||
556 | static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk) | |
557 | { | |
558 | if (cpu_has_xmm) { | |
559 | return tsk->thread.fpu.state->fxsave.mxcsr; | |
560 | } else { | |
561 | return MXCSR_DEFAULT; | |
562 | } | |
563 | } | |
564 | ||
565 | static bool fpu_allocated(struct fpu *fpu) | |
566 | { | |
567 | return fpu->state != NULL; | |
568 | } | |
569 | ||
570 | static inline int fpu_alloc(struct fpu *fpu) | |
571 | { | |
572 | if (fpu_allocated(fpu)) | |
573 | return 0; | |
574 | fpu->state = kmem_cache_alloc(task_xstate_cachep, GFP_KERNEL); | |
575 | if (!fpu->state) | |
576 | return -ENOMEM; | |
577 | WARN_ON((unsigned long)fpu->state & 15); | |
578 | return 0; | |
579 | } | |
580 | ||
581 | static inline void fpu_free(struct fpu *fpu) | |
582 | { | |
583 | if (fpu->state) { | |
584 | kmem_cache_free(task_xstate_cachep, fpu->state); | |
585 | fpu->state = NULL; | |
586 | } | |
587 | } | |
588 | ||
304bceda | 589 | static inline void fpu_copy(struct task_struct *dst, struct task_struct *src) |
1361b83a | 590 | { |
5d2bd700 SS |
591 | if (use_eager_fpu()) { |
592 | memset(&dst->thread.fpu.state->xsave, 0, xstate_size); | |
593 | __save_fpu(dst); | |
304bceda SS |
594 | } else { |
595 | struct fpu *dfpu = &dst->thread.fpu; | |
596 | struct fpu *sfpu = &src->thread.fpu; | |
597 | ||
598 | unlazy_fpu(src); | |
599 | memcpy(dfpu->state, sfpu->state, xstate_size); | |
600 | } | |
1361b83a LT |
601 | } |
602 | ||
72a671ce SS |
603 | static inline unsigned long |
604 | alloc_mathframe(unsigned long sp, int ia32_frame, unsigned long *buf_fx, | |
605 | unsigned long *size) | |
606 | { | |
607 | unsigned long frame_size = xstate_sigframe_size(); | |
608 | ||
609 | *buf_fx = sp = round_down(sp - frame_size, 64); | |
610 | if (ia32_frame && use_fxsr()) { | |
611 | frame_size += sizeof(struct i387_fsave_struct); | |
612 | sp -= sizeof(struct i387_fsave_struct); | |
613 | } | |
614 | ||
615 | *size = frame_size; | |
616 | return sp; | |
617 | } | |
1361b83a LT |
618 | |
619 | #endif |