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46184415 DB |
1 | /* |
2 | * iosf_mbi.h: Intel OnChip System Fabric MailBox access support | |
3 | */ | |
4 | ||
5 | #ifndef IOSF_MBI_SYMS_H | |
6 | #define IOSF_MBI_SYMS_H | |
7 | ||
8 | #define MBI_MCR_OFFSET 0xD0 | |
9 | #define MBI_MDR_OFFSET 0xD4 | |
10 | #define MBI_MCRX_OFFSET 0xD8 | |
11 | ||
12 | #define MBI_RD_MASK 0xFEFFFFFF | |
13 | #define MBI_WR_MASK 0X01000000 | |
14 | ||
15 | #define MBI_MASK_HI 0xFFFFFF00 | |
16 | #define MBI_MASK_LO 0x000000FF | |
17 | #define MBI_ENABLE 0xF0 | |
18 | ||
19 | /* Baytrail available units */ | |
20 | #define BT_MBI_UNIT_AUNIT 0x00 | |
21 | #define BT_MBI_UNIT_SMC 0x01 | |
22 | #define BT_MBI_UNIT_CPU 0x02 | |
23 | #define BT_MBI_UNIT_BUNIT 0x03 | |
24 | #define BT_MBI_UNIT_PMC 0x04 | |
25 | #define BT_MBI_UNIT_GFX 0x06 | |
26 | #define BT_MBI_UNIT_SMI 0x0C | |
27 | #define BT_MBI_UNIT_USB 0x43 | |
28 | #define BT_MBI_UNIT_SATA 0xA3 | |
29 | #define BT_MBI_UNIT_PCIE 0xA6 | |
30 | ||
31 | /* Baytrail read/write opcodes */ | |
32 | #define BT_MBI_AUNIT_READ 0x10 | |
33 | #define BT_MBI_AUNIT_WRITE 0x11 | |
34 | #define BT_MBI_SMC_READ 0x10 | |
35 | #define BT_MBI_SMC_WRITE 0x11 | |
36 | #define BT_MBI_CPU_READ 0x10 | |
37 | #define BT_MBI_CPU_WRITE 0x11 | |
38 | #define BT_MBI_BUNIT_READ 0x10 | |
39 | #define BT_MBI_BUNIT_WRITE 0x11 | |
40 | #define BT_MBI_PMC_READ 0x06 | |
41 | #define BT_MBI_PMC_WRITE 0x07 | |
42 | #define BT_MBI_GFX_READ 0x00 | |
43 | #define BT_MBI_GFX_WRITE 0x01 | |
44 | #define BT_MBI_SMIO_READ 0x06 | |
45 | #define BT_MBI_SMIO_WRITE 0x07 | |
46 | #define BT_MBI_USB_READ 0x06 | |
47 | #define BT_MBI_USB_WRITE 0x07 | |
48 | #define BT_MBI_SATA_READ 0x00 | |
49 | #define BT_MBI_SATA_WRITE 0x01 | |
50 | #define BT_MBI_PCIE_READ 0x00 | |
51 | #define BT_MBI_PCIE_WRITE 0x01 | |
52 | ||
7ef1def8 OBL |
53 | /* Quark available units */ |
54 | #define QRK_MBI_UNIT_HBA 0x00 | |
55 | #define QRK_MBI_UNIT_HB 0x03 | |
56 | #define QRK_MBI_UNIT_RMU 0x04 | |
57 | #define QRK_MBI_UNIT_MM 0x05 | |
58 | #define QRK_MBI_UNIT_MMESRAM 0x05 | |
59 | #define QRK_MBI_UNIT_SOC 0x31 | |
60 | ||
61 | /* Quark read/write opcodes */ | |
62 | #define QRK_MBI_HBA_READ 0x10 | |
63 | #define QRK_MBI_HBA_WRITE 0x11 | |
64 | #define QRK_MBI_HB_READ 0x10 | |
65 | #define QRK_MBI_HB_WRITE 0x11 | |
66 | #define QRK_MBI_RMU_READ 0x10 | |
67 | #define QRK_MBI_RMU_WRITE 0x11 | |
68 | #define QRK_MBI_MM_READ 0x10 | |
69 | #define QRK_MBI_MM_WRITE 0x11 | |
70 | #define QRK_MBI_MMESRAM_READ 0x12 | |
71 | #define QRK_MBI_MMESRAM_WRITE 0x13 | |
72 | #define QRK_MBI_SOC_READ 0x06 | |
73 | #define QRK_MBI_SOC_WRITE 0x07 | |
74 | ||
6b8f0c87 DB |
75 | #if IS_ENABLED(CONFIG_IOSF_MBI) |
76 | ||
77 | bool iosf_mbi_available(void); | |
78 | ||
46184415 DB |
79 | /** |
80 | * iosf_mbi_read() - MailBox Interface read command | |
81 | * @port: port indicating subunit being accessed | |
82 | * @opcode: port specific read or write opcode | |
83 | * @offset: register address offset | |
84 | * @mdr: register data to be read | |
85 | * | |
86 | * Locking is handled by spinlock - cannot sleep. | |
87 | * Return: Nonzero on error | |
88 | */ | |
89 | int iosf_mbi_read(u8 port, u8 opcode, u32 offset, u32 *mdr); | |
90 | ||
91 | /** | |
92 | * iosf_mbi_write() - MailBox unmasked write command | |
93 | * @port: port indicating subunit being accessed | |
94 | * @opcode: port specific read or write opcode | |
95 | * @offset: register address offset | |
96 | * @mdr: register data to be written | |
97 | * | |
98 | * Locking is handled by spinlock - cannot sleep. | |
99 | * Return: Nonzero on error | |
100 | */ | |
101 | int iosf_mbi_write(u8 port, u8 opcode, u32 offset, u32 mdr); | |
102 | ||
103 | /** | |
104 | * iosf_mbi_modify() - MailBox masked write command | |
105 | * @port: port indicating subunit being accessed | |
106 | * @opcode: port specific read or write opcode | |
107 | * @offset: register address offset | |
108 | * @mdr: register data being modified | |
109 | * @mask: mask indicating bits in mdr to be modified | |
110 | * | |
111 | * Locking is handled by spinlock - cannot sleep. | |
112 | * Return: Nonzero on error | |
113 | */ | |
114 | int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask); | |
115 | ||
6b8f0c87 DB |
116 | #else /* CONFIG_IOSF_MBI is not enabled */ |
117 | static inline | |
118 | bool iosf_mbi_available(void) | |
119 | { | |
120 | return false; | |
121 | } | |
122 | ||
123 | static inline | |
124 | int iosf_mbi_read(u8 port, u8 opcode, u32 offset, u32 *mdr) | |
125 | { | |
126 | WARN(1, "IOSF_MBI driver not available"); | |
127 | return -EPERM; | |
128 | } | |
129 | ||
130 | static inline | |
131 | int iosf_mbi_write(u8 port, u8 opcode, u32 offset, u32 mdr) | |
132 | { | |
133 | WARN(1, "IOSF_MBI driver not available"); | |
134 | return -EPERM; | |
135 | } | |
136 | ||
137 | static inline | |
138 | int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask) | |
139 | { | |
140 | WARN(1, "IOSF_MBI driver not available"); | |
141 | return -EPERM; | |
142 | } | |
143 | #endif /* CONFIG_IOSF_MBI */ | |
144 | ||
46184415 | 145 | #endif /* IOSF_MBI_SYMS_H */ |