projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 1965aae3 PA |
1 | #ifndef _ASM_X86_IPI_H |
| 2 | #define _ASM_X86_IPI_H | |
| 1da177e4 LT |
3 | |
| 4 | /* | |
| 5 | * Copyright 2004 James Cleverdon, IBM. | |
| 6 | * Subject to the GNU Public License, v.2 | |
| 7 | * | |
| 8 | * Generic APIC InterProcessor Interrupt code. | |
| 9 | * | |
| 10 | * Moved to include file by James Cleverdon from | |
| 11 | * arch/x86-64/kernel/smp.c | |
| 12 | * | |
| 13 | * Copyrights from kernel/smp.c: | |
| 14 | * | |
| 15 | * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> | |
| 16 | * (c) 1998-99, 2000 Ingo Molnar <mingo@redhat.com> | |
| 17 | * (c) 2002,2003 Andi Kleen, SuSE Labs. | |
| 18 | * Subject to the GNU Public License, v.2 | |
| 19 | */ | |
| 20 | ||
| 1da177e4 | 21 | #include <asm/hw_irq.h> |
| 00f1ea69 | 22 | #include <asm/apic.h> |
| e3f8ba81 | 23 | #include <asm/smp.h> |
| 1da177e4 LT |
24 | |
| 25 | /* | |
| 26 | * the following functions deal with sending IPIs between CPUs. | |
| 27 | * | |
| 28 | * We use 'broadcast', CPU->CPU IPIs and self-IPIs too. | |
| 29 | */ | |
| 30 | ||
| 061b3d90 JP |
31 | static inline unsigned int __prepare_ICR(unsigned int shortcut, int vector, |
| 32 | unsigned int dest) | |
| 1da177e4 | 33 | { |
| 1a426cb7 JB |
34 | unsigned int icr = shortcut | dest; |
| 35 | ||
| 36 | switch (vector) { | |
| 37 | default: | |
| 38 | icr |= APIC_DM_FIXED | vector; | |
| 39 | break; | |
| 40 | case NMI_VECTOR: | |
| 1a426cb7 JB |
41 | icr |= APIC_DM_NMI; |
| 42 | break; | |
| 43 | } | |
| 1da177e4 LT |
44 | return icr; |
| 45 | } | |
| 46 | ||
| 061b3d90 | 47 | static inline int __prepare_ICR2(unsigned int mask) |
| 1da177e4 LT |
48 | { |
| 49 | return SET_APIC_DEST_FIELD(mask); | |
| 50 | } | |
| 51 | ||
| 1b374e4d SS |
52 | static inline void __xapic_wait_icr_idle(void) |
| 53 | { | |
| 54 | while (native_apic_mem_read(APIC_ICR) & APIC_ICR_BUSY) | |
| 55 | cpu_relax(); | |
| 56 | } | |
| 57 | ||
| 061b3d90 JP |
58 | static inline void __send_IPI_shortcut(unsigned int shortcut, int vector, |
| 59 | unsigned int dest) | |
| 1da177e4 LT |
60 | { |
| 61 | /* | |
| 62 | * Subtle. In the case of the 'never do double writes' workaround | |
| 63 | * we have to lock out interrupts to be safe. As we don't care | |
| 64 | * of the value read we use an atomic rmw access to avoid costly | |
| 65 | * cli/sti. Otherwise we use an even cheaper single atomic write | |
| 66 | * to the APIC. | |
| 67 | */ | |
| 68 | unsigned int cfg; | |
| 69 | ||
| 70 | /* | |
| 71 | * Wait for idle. | |
| 72 | */ | |
| 1b374e4d | 73 | __xapic_wait_icr_idle(); |
| 1da177e4 LT |
74 | |
| 75 | /* | |
| 76 | * No need to touch the target chip field | |
| 77 | */ | |
| 78 | cfg = __prepare_ICR(shortcut, vector, dest); | |
| 79 | ||
| 80 | /* | |
| 81 | * Send the IPI. The write to APIC_ICR fires this off. | |
| 82 | */ | |
| 1b374e4d | 83 | native_apic_mem_write(APIC_ICR, cfg); |
| 1da177e4 LT |
84 | } |
| 85 |