Commit | Line | Data |
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5e1b0075 PA |
1 | #ifndef _ASM_X86_IRQ_REMAPPING_H |
2 | #define _ASM_X86_IRQ_REMAPPING_H | |
89027d35 | 3 | |
fc1edaf9 | 4 | #define IRTE_DEST(dest) ((x2apic_mode) ? dest : dest << 8) |
89027d35 | 5 | |
62a92f4c SS |
6 | #ifdef CONFIG_INTR_REMAP |
7 | static inline void prepare_irte(struct irte *irte, int vector, | |
8 | unsigned int dest) | |
9 | { | |
10 | memset(irte, 0, sizeof(*irte)); | |
11 | ||
12 | irte->present = 1; | |
13 | irte->dst_mode = apic->irq_dest_mode; | |
14 | /* | |
15 | * Trigger mode in the IRTE will always be edge, and for IO-APIC, the | |
16 | * actual level or edge trigger will be setup in the IO-APIC | |
17 | * RTE. This will help simplify level triggered irq migration. | |
18 | * For more details, see the comments (in io_apic.c) explainig IO-APIC | |
19 | * irq migration in the presence of interrupt-remapping. | |
20 | */ | |
21 | irte->trigger_mode = 0; | |
22 | irte->dlvry_mode = apic->irq_delivery_mode; | |
23 | irte->vector = vector; | |
24 | irte->dest_id = IRTE_DEST(dest); | |
25 | irte->redir_hint = 1; | |
26 | } | |
1a0730d6 TG |
27 | static inline bool irq_remapped(struct irq_cfg *cfg) |
28 | { | |
29 | return cfg->irq_2_iommu.iommu != NULL; | |
30 | } | |
62a92f4c SS |
31 | #else |
32 | static void prepare_irte(struct irte *irte, int vector, unsigned int dest) | |
33 | { | |
34 | } | |
1a0730d6 TG |
35 | static inline bool irq_remapped(struct irq_cfg *cfg) |
36 | { | |
37 | return false; | |
38 | } | |
62a92f4c SS |
39 | #endif |
40 | ||
5e1b0075 | 41 | #endif /* _ASM_X86_IRQ_REMAPPING_H */ |