[deliverable/linux.git] / arch / x86 / include / asm / irq_vectors.h

#ifndef _ASM_X86_IRQ_VECTORS_H
#define _ASM_X86_IRQ_VECTORS_H

#include <linux/threads.h>
/*
 * Linux IRQ vector layout.
 *
 * There are 256 IDT entries (per CPU - each entry is 8 bytes) which can
 * be defined by Linux. They are used as a jump table by the CPU when a
 * given vector is triggered - by a CPU-external, CPU-internal or
 * software-triggered event.
 *
 * Linux sets the kernel code address each entry jumps to early during
 * bootup, and never changes them. This is the general layout of the
 * IDT entries:
 *
 *  Vectors   0 ...  31 : system traps and exceptions - hardcoded events
 *  Vectors  32 ... 127 : device interrupts
 *  Vector  128         : legacy int80 syscall interface
 *  Vectors 129 ... INVALIDATE_TLB_VECTOR_START-1 except 204 : device interrupts
 *  Vectors INVALIDATE_TLB_VECTOR_START ... 255 : special interrupts
 *
 * 64-bit x86 has per CPU IDT tables, 32-bit has one shared IDT table.
 *
 * This file enumerates the exact layout of them:
 */

#define NMI_VECTOR			0x02
#define MCE_VECTOR			0x12

/*
 * IDT vectors usable for external interrupt sources start at 0x20.
 * (0x80 is the syscall vector, 0x30-0x3f are for ISA)
 */
#define FIRST_EXTERNAL_VECTOR		0x20
/*
 * We start allocating at 0x21 to spread out vectors evenly between
 * priority levels. (0x80 is the syscall vector)
 */
#define VECTOR_OFFSET_START		1

/*
 * Reserve the lowest usable vector (and hence lowest priority)  0x20 for
 * triggering cleanup after irq migration. 0x21-0x2f will still be used
 * for device interrupts.
 */
#define IRQ_MOVE_CLEANUP_VECTOR		FIRST_EXTERNAL_VECTOR

#define IA32_SYSCALL_VECTOR		0x80

/*
 * Vectors 0x30-0x3f are used for ISA interrupts.
 *   round up to the next 16-vector boundary
 */
#define ISA_IRQ_VECTOR(irq)		(((FIRST_EXTERNAL_VECTOR + 16) & ~15) + irq)

/*
 * Special IRQ vectors used by the SMP architecture, 0xf0-0xff
 *
 *  some of the following vectors are 'rare', they are merged
 *  into a single vector (CALL_FUNCTION_VECTOR) to save vector space.
 *  TLB, reschedule and local APIC vectors are performance-critical.
 */

#define SPURIOUS_APIC_VECTOR		0xff
/*
 * Sanity check
 */
#if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
# error SPURIOUS_APIC_VECTOR definition error
#endif

#define ERROR_APIC_VECTOR		0xfe
#define RESCHEDULE_VECTOR		0xfd
#define CALL_FUNCTION_VECTOR		0xfc
#define CALL_FUNCTION_SINGLE_VECTOR	0xfb
#define THERMAL_APIC_VECTOR		0xfa
#define THRESHOLD_APIC_VECTOR		0xf9
#define REBOOT_VECTOR			0xf8

/*
 * Generic system vector for platform specific use
 */
#define X86_PLATFORM_IPI_VECTOR		0xf7

#define POSTED_INTR_WAKEUP_VECTOR	0xf1
/*
 * IRQ work vector:
 */
#define IRQ_WORK_VECTOR			0xf6

#define UV_BAU_MESSAGE			0xf5
#define DEFERRED_ERROR_VECTOR		0xf4

/* Vector on which hypervisor callbacks will be delivered */
#define HYPERVISOR_CALLBACK_VECTOR	0xf3

/* Vector for KVM to deliver posted interrupt IPI */
#ifdef CONFIG_HAVE_KVM
#define POSTED_INTR_VECTOR		0xf2
#endif

/*
 * Local APIC timer IRQ vector is on a different priority level,
 * to work around the 'lost local interrupt if more than 2 IRQ
 * sources per level' errata.
 */
#define LOCAL_TIMER_VECTOR		0xef

#define NR_VECTORS			 256

#ifdef CONFIG_X86_LOCAL_APIC
#define FIRST_SYSTEM_VECTOR		LOCAL_TIMER_VECTOR
#else
#define FIRST_SYSTEM_VECTOR		NR_VECTORS
#endif

#define FPU_IRQ				  13

/*
 * Size the maximum number of interrupts.
 *
 * If the irq_desc[] array has a sparse layout, we can size things
 * generously - it scales up linearly with the maximum number of CPUs,
 * and the maximum number of IO-APICs, whichever is higher.
 *
 * In other cases we size more conservatively, to not create too large
 * static arrays.
 */

#define NR_IRQS_LEGACY			16

#define CPU_VECTOR_LIMIT		(64 * NR_CPUS)
#define IO_APIC_VECTOR_LIMIT		(32 * MAX_IO_APICS)

#if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_PCI_MSI)
#define NR_IRQS						\
	(CPU_VECTOR_LIMIT > IO_APIC_VECTOR_LIMIT ?	\
		(NR_VECTORS + CPU_VECTOR_LIMIT)  :	\
		(NR_VECTORS + IO_APIC_VECTOR_LIMIT))
#elif defined(CONFIG_X86_IO_APIC)
#define	NR_IRQS				(NR_VECTORS + IO_APIC_VECTOR_LIMIT)
#elif defined(CONFIG_PCI_MSI)
#define NR_IRQS				(NR_VECTORS + CPU_VECTOR_LIMIT)
#else
#define NR_IRQS				NR_IRQS_LEGACY
#endif

#endif /* _ASM_X86_IRQ_VECTORS_H */
Commit	Line	Data
1965aae3 PA	1	#ifndef _ASM_X86_IRQ_VECTORS_H
1965aae3 PA	2	#define _ASM_X86_IRQ_VECTORS_H
9b7dc567	3
60f6e65d	4	#include <linux/threads.h>
9fc2e79d IM	5	/*
	6	* Linux IRQ vector layout.
	7	*
	8	* There are 256 IDT entries (per CPU - each entry is 8 bytes) which can
	9	* be defined by Linux. They are used as a jump table by the CPU when a
	10	* given vector is triggered - by a CPU-external, CPU-internal or
	11	* software-triggered event.
	12	*
	13	* Linux sets the kernel code address each entry jumps to early during
	14	* bootup, and never changes them. This is the general layout of the
	15	* IDT entries:
	16	*
	17	* Vectors 0 ... 31 : system traps and exceptions - hardcoded events
	18	* Vectors 32 ... 127 : device interrupts
	19	* Vector 128 : legacy int80 syscall interface
5cec93c2	20	* Vectors 129 ... INVALIDATE_TLB_VECTOR_START-1 except 204 : device interrupts
70e4a369	21	* Vectors INVALIDATE_TLB_VECTOR_START ... 255 : special interrupts
9fc2e79d IM	22	*
	23	* 64-bit x86 has per CPU IDT tables, 32-bit has one shared IDT table.
	24	*
	25	* This file enumerates the exact layout of them:
	26	*/
	27
	28	#define NMI_VECTOR 0x02
8fa8dd9e	29	#define MCE_VECTOR 0x12
9b7dc567 TG	30
9b7dc567 TG	31	/*
6579b474 SS	32	* IDT vectors usable for external interrupt sources start at 0x20.
6579b474 SS	33	* (0x80 is the syscall vector, 0x30-0x3f are for ISA)
9b7dc567	34	*/
6579b474 SS	35	#define FIRST_EXTERNAL_VECTOR 0x20
	36	/*
	37	* We start allocating at 0x21 to spread out vectors evenly between
	38	* priority levels. (0x80 is the syscall vector)
	39	*/
	40	#define VECTOR_OFFSET_START 1
	41
	42	/*
	43	* Reserve the lowest usable vector (and hence lowest priority) 0x20 for
	44	* triggering cleanup after irq migration. 0x21-0x2f will still be used
	45	* for device interrupts.
	46	*/
	47	#define IRQ_MOVE_CLEANUP_VECTOR FIRST_EXTERNAL_VECTOR
9b7dc567	48
99d113b1	49	#define IA32_SYSCALL_VECTOR 0x80
9b7dc567 TG	50
9b7dc567 TG	51	/*
6579b474	52	* Vectors 0x30-0x3f are used for ISA interrupts.
99d113b1	53	* round up to the next 16-vector boundary
9b7dc567	54	*/
8b455e65	55	#define ISA_IRQ_VECTOR(irq) (((FIRST_EXTERNAL_VECTOR + 16) & ~15) + irq)
9b7dc567 TG	56
	57	/*
	58	* Special IRQ vectors used by the SMP architecture, 0xf0-0xff
	59	*
	60	* some of the following vectors are 'rare', they are merged
	61	* into a single vector (CALL_FUNCTION_VECTOR) to save vector space.
	62	* TLB, reschedule and local APIC vectors are performance-critical.
9b7dc567	63	*/
02cf94c3	64
5da690d2	65	#define SPURIOUS_APIC_VECTOR 0xff
647ad94f IM	66	/*
	67	* Sanity check
	68	*/
	69	#if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
	70	# error SPURIOUS_APIC_VECTOR definition error
	71	#endif
	72
5da690d2 IM	73	#define ERROR_APIC_VECTOR 0xfe
	74	#define RESCHEDULE_VECTOR 0xfd
	75	#define CALL_FUNCTION_VECTOR 0xfc
	76	#define CALL_FUNCTION_SINGLE_VECTOR 0xfb
	77	#define THERMAL_APIC_VECTOR 0xfa
7856f6cc	78	#define THRESHOLD_APIC_VECTOR 0xf9
4ef702c1	79	#define REBOOT_VECTOR 0xf8
9b7dc567	80
193c81b9	81	/*
acaabe79	82	* Generic system vector for platform specific use
193c81b9	83	*/
60f6e65d	84	#define X86_PLATFORM_IPI_VECTOR 0xf7
193c81b9	85
f6b3c72c	86	#define POSTED_INTR_WAKEUP_VECTOR 0xf1
acaabe79	87	/*
e360adbe	88	* IRQ work vector:
acaabe79	89	*/
60f6e65d	90	#define IRQ_WORK_VECTOR 0xf6
acaabe79	91
60f6e65d	92	#define UV_BAU_MESSAGE 0xf5
24fd78a8	93	#define DEFERRED_ERROR_VECTOR 0xf4
4ef702c1	94
bc2b0331 S	95	/* Vector on which hypervisor callbacks will be delivered */
bc2b0331 S	96	#define HYPERVISOR_CALLBACK_VECTOR 0xf3
60f6e65d	97
5c0d728e AG	98	/* Vector for KVM to deliver posted interrupt IPI */
	99	#ifdef CONFIG_HAVE_KVM
	100	#define POSTED_INTR_VECTOR 0xf2
	101	#endif
	102
60f6e65d SL	103	/*
	104	* Local APIC timer IRQ vector is on a different priority level,
	105	* to work around the 'lost local interrupt if more than 2 IRQ
	106	* sources per level' errata.
	107	*/
	108	#define LOCAL_TIMER_VECTOR 0xef
	109
9fc2e79d	110	#define NR_VECTORS 256
9b7dc567	111
2414e021 JB	112	#ifdef CONFIG_X86_LOCAL_APIC
	113	#define FIRST_SYSTEM_VECTOR LOCAL_TIMER_VECTOR
	114	#else
	115	#define FIRST_SYSTEM_VECTOR NR_VECTORS
	116	#endif
	117
9fc2e79d	118	#define FPU_IRQ 13
9b7dc567	119
009eb3fe IM	120	/*
	121	* Size the maximum number of interrupts.
	122	*
	123	* If the irq_desc[] array has a sparse layout, we can size things
	124	* generously - it scales up linearly with the maximum number of CPUs,
	125	* and the maximum number of IO-APICs, whichever is higher.
	126	*
	127	* In other cases we size more conservatively, to not create too large
	128	* static arrays.
	129	*/
	130
4399b14f	131	#define NR_IRQS_LEGACY 16
99d093d1	132
4399b14f JL	133	#define CPU_VECTOR_LIMIT (64 * NR_CPUS)
4399b14f JL	134	#define IO_APIC_VECTOR_LIMIT (32 * MAX_IO_APICS)
009eb3fe	135
4399b14f JL	136	#if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_PCI_MSI)
4399b14f JL	137	#define NR_IRQS \
009eb3fe IM	138	(CPU_VECTOR_LIMIT > IO_APIC_VECTOR_LIMIT ? \
	139	(NR_VECTORS + CPU_VECTOR_LIMIT) : \
	140	(NR_VECTORS + IO_APIC_VECTOR_LIMIT))
4399b14f JL	141	#elif defined(CONFIG_X86_IO_APIC)
	142	#define NR_IRQS (NR_VECTORS + IO_APIC_VECTOR_LIMIT)
	143	#elif defined(CONFIG_PCI_MSI)
	144	#define NR_IRQS (NR_VECTORS + CPU_VECTOR_LIMIT)
	145	#else
	146	#define NR_IRQS NR_IRQS_LEGACY
1b489768	147	#endif
9b7dc567	148
1965aae3	149	#endif /* _ASM_X86_IRQ_VECTORS_H */