[deliverable/linux.git] / arch / x86 / include / asm / irq_vectors.h

#ifndef _ASM_X86_IRQ_VECTORS_H
#define _ASM_X86_IRQ_VECTORS_H

#include <linux/threads.h>

#define NMI_VECTOR		0x02

/*
 * IDT vectors usable for external interrupt sources start
 * at 0x20:
 */
#define FIRST_EXTERNAL_VECTOR	0x20

#ifdef CONFIG_X86_32
# define SYSCALL_VECTOR		0x80
#else
# define IA32_SYSCALL_VECTOR	0x80
#endif

/*
 * Reserve the lowest usable priority level 0x20 - 0x2f for triggering
 * cleanup after irq migration.
 */
#define IRQ_MOVE_CLEANUP_VECTOR	FIRST_EXTERNAL_VECTOR

/*
 * Vectors 0x30-0x3f are used for ISA interrupts.
 */
#define IRQ0_VECTOR		(FIRST_EXTERNAL_VECTOR + 0x10)
#define IRQ1_VECTOR		(IRQ0_VECTOR + 1)
#define IRQ2_VECTOR		(IRQ0_VECTOR + 2)
#define IRQ3_VECTOR		(IRQ0_VECTOR + 3)
#define IRQ4_VECTOR		(IRQ0_VECTOR + 4)
#define IRQ5_VECTOR		(IRQ0_VECTOR + 5)
#define IRQ6_VECTOR		(IRQ0_VECTOR + 6)
#define IRQ7_VECTOR		(IRQ0_VECTOR + 7)
#define IRQ8_VECTOR		(IRQ0_VECTOR + 8)
#define IRQ9_VECTOR		(IRQ0_VECTOR + 9)
#define IRQ10_VECTOR		(IRQ0_VECTOR + 10)
#define IRQ11_VECTOR		(IRQ0_VECTOR + 11)
#define IRQ12_VECTOR		(IRQ0_VECTOR + 12)
#define IRQ13_VECTOR		(IRQ0_VECTOR + 13)
#define IRQ14_VECTOR		(IRQ0_VECTOR + 14)
#define IRQ15_VECTOR		(IRQ0_VECTOR + 15)

/*
 * Special IRQ vectors used by the SMP architecture, 0xf0-0xff
 *
 *  some of the following vectors are 'rare', they are merged
 *  into a single vector (CALL_FUNCTION_VECTOR) to save vector space.
 *  TLB, reschedule and local APIC vectors are performance-critical.
 */

#define SPURIOUS_APIC_VECTOR		0xff
#define ERROR_APIC_VECTOR		0xfe
#define RESCHEDULE_VECTOR		0xfd
#define CALL_FUNCTION_VECTOR		0xfc
#define CALL_FUNCTION_SINGLE_VECTOR	0xfb
#define THERMAL_APIC_VECTOR		0xfa

#ifdef CONFIG_X86_32
/* 0xf8 - 0xf9 : free */
#else
# define THRESHOLD_APIC_VECTOR		0xf9
# define UV_BAU_MESSAGE			0xf8
#endif

/* f0-f7 used for spreading out TLB flushes: */
#define INVALIDATE_TLB_VECTOR_END	0xf7
#define INVALIDATE_TLB_VECTOR_START	0xf0
#define NUM_INVALIDATE_TLB_VECTORS	8

/*
 * Local APIC timer IRQ vector is on a different priority level,
 * to work around the 'lost local interrupt if more than 2 IRQ
 * sources per level' errata.
 */
#define LOCAL_TIMER_VECTOR	0xef

/*
 * Performance monitoring interrupt vector:
 */
#define LOCAL_PERF_VECTOR	0xee

/*
 * First APIC vector available to drivers: (vectors 0x30-0xee) we
 * start at 0x31(0x41) to spread out vectors evenly between priority
 * levels. (0x80 is the syscall vector)
 */
#define FIRST_DEVICE_VECTOR	(IRQ15_VECTOR + 2)

#define NR_VECTORS		256

#define FPU_IRQ			13

#define	FIRST_VM86_IRQ		3
#define LAST_VM86_IRQ		15
#define invalid_vm86_irq(irq)	((irq) < 3 || (irq) > 15)

#define NR_IRQS_LEGACY		16

#if defined(CONFIG_X86_IO_APIC) && !defined(CONFIG_X86_VOYAGER)

#include <asm/apicnum.h>	/* need MAX_IO_APICS */

#ifndef CONFIG_SPARSE_IRQ
# if NR_CPUS < MAX_IO_APICS
#  define NR_IRQS (NR_VECTORS + (32 * NR_CPUS))
# else
#  define NR_IRQS (NR_VECTORS + (32 * MAX_IO_APICS))
# endif
#else

# define NR_IRQS					\
	((8 * NR_CPUS) > (32 * MAX_IO_APICS) ?		\
		(NR_VECTORS + (8 * NR_CPUS)) :		\
		(NR_VECTORS + (32 * MAX_IO_APICS)))	\

#endif

#elif defined(CONFIG_X86_VOYAGER)

# define NR_IRQS		224

#else /* IO_APIC || VOYAGER */

# define NR_IRQS		16

#endif

/* Voyager specific defines */
/* These define the CPIs we use in linux */
#define VIC_CPI_LEVEL0			0
#define VIC_CPI_LEVEL1			1
/* now the fake CPIs */
#define VIC_TIMER_CPI			2
#define VIC_INVALIDATE_CPI		3
#define VIC_RESCHEDULE_CPI		4
#define VIC_ENABLE_IRQ_CPI		5
#define VIC_CALL_FUNCTION_CPI		6
#define VIC_CALL_FUNCTION_SINGLE_CPI	7

/* Now the QIC CPIs:  Since we don't need the two initial levels,
 * these are 2 less than the VIC CPIs */
#define QIC_CPI_OFFSET			1
#define QIC_TIMER_CPI			(VIC_TIMER_CPI - QIC_CPI_OFFSET)
#define QIC_INVALIDATE_CPI		(VIC_INVALIDATE_CPI - QIC_CPI_OFFSET)
#define QIC_RESCHEDULE_CPI		(VIC_RESCHEDULE_CPI - QIC_CPI_OFFSET)
#define QIC_ENABLE_IRQ_CPI		(VIC_ENABLE_IRQ_CPI - QIC_CPI_OFFSET)
#define QIC_CALL_FUNCTION_CPI		(VIC_CALL_FUNCTION_CPI - QIC_CPI_OFFSET)
#define QIC_CALL_FUNCTION_SINGLE_CPI	(VIC_CALL_FUNCTION_SINGLE_CPI - QIC_CPI_OFFSET)

#define VIC_START_FAKE_CPI		VIC_TIMER_CPI
#define VIC_END_FAKE_CPI		VIC_CALL_FUNCTION_SINGLE_CPI

/* this is the SYS_INT CPI. */
#define VIC_SYS_INT			8
#define VIC_CMN_INT			15

/* This is the boot CPI for alternate processors.  It gets overwritten
 * by the above once the system has activated all available processors */
#define VIC_CPU_BOOT_CPI		VIC_CPI_LEVEL0
#define VIC_CPU_BOOT_ERRATA_CPI		(VIC_CPI_LEVEL0 + 8)


#endif /* _ASM_X86_IRQ_VECTORS_H */
Commit	Line	Data
1965aae3 PA	1	#ifndef _ASM_X86_IRQ_VECTORS_H
1965aae3 PA	2	#define _ASM_X86_IRQ_VECTORS_H
9b7dc567 TG	3
	4	#include <linux/threads.h>
	5
	6	#define NMI_VECTOR 0x02
	7
	8	/*
	9	* IDT vectors usable for external interrupt sources start
	10	* at 0x20:
	11	*/
	12	#define FIRST_EXTERNAL_VECTOR 0x20
	13
	14	#ifdef CONFIG_X86_32
	15	# define SYSCALL_VECTOR 0x80
	16	#else
	17	# define IA32_SYSCALL_VECTOR 0x80
	18	#endif
	19
	20	/*
9b7dc567	21	* Reserve the lowest usable priority level 0x20 - 0x2f for triggering
497c9a19	22	* cleanup after irq migration.
9b7dc567 TG	23	*/
	24	#define IRQ_MOVE_CLEANUP_VECTOR FIRST_EXTERNAL_VECTOR
	25
	26	/*
497c9a19	27	* Vectors 0x30-0x3f are used for ISA interrupts.
9b7dc567 TG	28	*/
	29	#define IRQ0_VECTOR (FIRST_EXTERNAL_VECTOR + 0x10)
	30	#define IRQ1_VECTOR (IRQ0_VECTOR + 1)
	31	#define IRQ2_VECTOR (IRQ0_VECTOR + 2)
	32	#define IRQ3_VECTOR (IRQ0_VECTOR + 3)
	33	#define IRQ4_VECTOR (IRQ0_VECTOR + 4)
	34	#define IRQ5_VECTOR (IRQ0_VECTOR + 5)
	35	#define IRQ6_VECTOR (IRQ0_VECTOR + 6)
	36	#define IRQ7_VECTOR (IRQ0_VECTOR + 7)
	37	#define IRQ8_VECTOR (IRQ0_VECTOR + 8)
	38	#define IRQ9_VECTOR (IRQ0_VECTOR + 9)
	39	#define IRQ10_VECTOR (IRQ0_VECTOR + 10)
	40	#define IRQ11_VECTOR (IRQ0_VECTOR + 11)
	41	#define IRQ12_VECTOR (IRQ0_VECTOR + 12)
	42	#define IRQ13_VECTOR (IRQ0_VECTOR + 13)
	43	#define IRQ14_VECTOR (IRQ0_VECTOR + 14)
	44	#define IRQ15_VECTOR (IRQ0_VECTOR + 15)
	45
	46	/*
	47	* Special IRQ vectors used by the SMP architecture, 0xf0-0xff
	48	*
	49	* some of the following vectors are 'rare', they are merged
	50	* into a single vector (CALL_FUNCTION_VECTOR) to save vector space.
	51	* TLB, reschedule and local APIC vectors are performance-critical.
9b7dc567	52	*/
02cf94c3	53
5da690d2 IM	54	#define SPURIOUS_APIC_VECTOR 0xff
	55	#define ERROR_APIC_VECTOR 0xfe
	56	#define RESCHEDULE_VECTOR 0xfd
	57	#define CALL_FUNCTION_VECTOR 0xfc
	58	#define CALL_FUNCTION_SINGLE_VECTOR 0xfb
	59	#define THERMAL_APIC_VECTOR 0xfa
9b7dc567	60
5da690d2 IM	61	#ifdef CONFIG_X86_32
5da690d2 IM	62	/* 0xf8 - 0xf9 : free */
9b7dc567	63	#else
6dd01bed TH	64	# define THRESHOLD_APIC_VECTOR 0xf9
6dd01bed TH	65	# define UV_BAU_MESSAGE 0xf8
5da690d2	66	#endif
9b7dc567	67
5da690d2 IM	68	/* f0-f7 used for spreading out TLB flushes: */
	69	#define INVALIDATE_TLB_VECTOR_END 0xf7
	70	#define INVALIDATE_TLB_VECTOR_START 0xf0
9b7dc567 TG	71	#define NUM_INVALIDATE_TLB_VECTORS 8
9b7dc567 TG	72
9b7dc567 TG	73	/*
	74	* Local APIC timer IRQ vector is on a different priority level,
	75	* to work around the 'lost local interrupt if more than 2 IRQ
	76	* sources per level' errata.
	77	*/
	78	#define LOCAL_TIMER_VECTOR 0xef
	79
193c81b9 IM	80	/*
	81	* Performance monitoring interrupt vector:
	82	*/
	83	#define LOCAL_PERF_VECTOR 0xee
	84
9b7dc567 TG	85	/*
	86	* First APIC vector available to drivers: (vectors 0x30-0xee) we
	87	* start at 0x31(0x41) to spread out vectors evenly between priority
	88	* levels. (0x80 is the syscall vector)
	89	*/
497c9a19	90	#define FIRST_DEVICE_VECTOR (IRQ15_VECTOR + 2)
9b7dc567	91
9b7dc567 TG	92	#define NR_VECTORS 256
	93
	94	#define FPU_IRQ 13
	95
	96	#define FIRST_VM86_IRQ 3
	97	#define LAST_VM86_IRQ 15
	98	#define invalid_vm86_irq(irq) ((irq) < 3 \|\| (irq) > 15)
	99
99d093d1 YL	100	#define NR_IRQS_LEGACY 16
99d093d1 YL	101
7db282fa	102	#if defined(CONFIG_X86_IO_APIC) && !defined(CONFIG_X86_VOYAGER)
0b8f1efa	103
9332fccd MT	104	#include <asm/apicnum.h> /* need MAX_IO_APICS */
9332fccd MT	105
0b8f1efa	106	#ifndef CONFIG_SPARSE_IRQ
3c7569b2 EB	107	# if NR_CPUS < MAX_IO_APICS
	108	# define NR_IRQS (NR_VECTORS + (32 * NR_CPUS))
	109	# else
	110	# define NR_IRQS (NR_VECTORS + (32 * MAX_IO_APICS))
	111	# endif
0b8f1efa	112	#else
9332fccd	113
4a046d17 YL	114	# define NR_IRQS \
4a046d17 YL	115	((8 * NR_CPUS) > (32 * MAX_IO_APICS) ? \
9332fccd MT	116	(NR_VECTORS + (8 * NR_CPUS)) : \
	117	(NR_VECTORS + (32 * MAX_IO_APICS))) \
	118
0b8f1efa	119	#endif
3c7569b2	120
7db282fa	121	#elif defined(CONFIG_X86_VOYAGER)
9b7dc567	122
1b489768	123	# define NR_IRQS 224
9b7dc567	124
7db282fa	125	#else /* IO_APIC \|\| VOYAGER */
9b7dc567	126
1b489768	127	# define NR_IRQS 16
9b7dc567	128
1b489768	129	#endif
9b7dc567 TG	130
	131	/* Voyager specific defines */
	132	/* These define the CPIs we use in linux */
	133	#define VIC_CPI_LEVEL0 0
	134	#define VIC_CPI_LEVEL1 1
	135	/* now the fake CPIs */
	136	#define VIC_TIMER_CPI 2
	137	#define VIC_INVALIDATE_CPI 3
	138	#define VIC_RESCHEDULE_CPI 4
	139	#define VIC_ENABLE_IRQ_CPI 5
	140	#define VIC_CALL_FUNCTION_CPI 6
1a781a77	141	#define VIC_CALL_FUNCTION_SINGLE_CPI 7
9b7dc567 TG	142
	143	/* Now the QIC CPIs: Since we don't need the two initial levels,
	144	* these are 2 less than the VIC CPIs */
	145	#define QIC_CPI_OFFSET 1
	146	#define QIC_TIMER_CPI (VIC_TIMER_CPI - QIC_CPI_OFFSET)
	147	#define QIC_INVALIDATE_CPI (VIC_INVALIDATE_CPI - QIC_CPI_OFFSET)
	148	#define QIC_RESCHEDULE_CPI (VIC_RESCHEDULE_CPI - QIC_CPI_OFFSET)
	149	#define QIC_ENABLE_IRQ_CPI (VIC_ENABLE_IRQ_CPI - QIC_CPI_OFFSET)
	150	#define QIC_CALL_FUNCTION_CPI (VIC_CALL_FUNCTION_CPI - QIC_CPI_OFFSET)
1a781a77	151	#define QIC_CALL_FUNCTION_SINGLE_CPI (VIC_CALL_FUNCTION_SINGLE_CPI - QIC_CPI_OFFSET)
9b7dc567 TG	152
9b7dc567 TG	153	#define VIC_START_FAKE_CPI VIC_TIMER_CPI
1a781a77	154	#define VIC_END_FAKE_CPI VIC_CALL_FUNCTION_SINGLE_CPI
9b7dc567 TG	155
	156	/* this is the SYS_INT CPI. */
	157	#define VIC_SYS_INT 8
	158	#define VIC_CMN_INT 15
	159
	160	/* This is the boot CPI for alternate processors. It gets overwritten
	161	* by the above once the system has activated all available processors */
	162	#define VIC_CPU_BOOT_CPI VIC_CPI_LEVEL0
	163	#define VIC_CPU_BOOT_ERRATA_CPI (VIC_CPI_LEVEL0 + 8)
	164
	165
1965aae3	166	#endif /* _ASM_X86_IRQ_VECTORS_H */