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1965aae3 PA |
1 | #ifndef _ASM_X86_IRQ_VECTORS_H |
2 | #define _ASM_X86_IRQ_VECTORS_H | |
9b7dc567 | 3 | |
9fc2e79d IM |
4 | /* |
5 | * Linux IRQ vector layout. | |
6 | * | |
7 | * There are 256 IDT entries (per CPU - each entry is 8 bytes) which can | |
8 | * be defined by Linux. They are used as a jump table by the CPU when a | |
9 | * given vector is triggered - by a CPU-external, CPU-internal or | |
10 | * software-triggered event. | |
11 | * | |
12 | * Linux sets the kernel code address each entry jumps to early during | |
13 | * bootup, and never changes them. This is the general layout of the | |
14 | * IDT entries: | |
15 | * | |
16 | * Vectors 0 ... 31 : system traps and exceptions - hardcoded events | |
17 | * Vectors 32 ... 127 : device interrupts | |
18 | * Vector 128 : legacy int80 syscall interface | |
19 | * Vectors 129 ... 237 : device interrupts | |
20 | * Vectors 238 ... 255 : special interrupts | |
21 | * | |
22 | * 64-bit x86 has per CPU IDT tables, 32-bit has one shared IDT table. | |
23 | * | |
24 | * This file enumerates the exact layout of them: | |
25 | */ | |
26 | ||
27 | #define NMI_VECTOR 0x02 | |
8fa8dd9e | 28 | #define MCE_VECTOR 0x12 |
9b7dc567 TG |
29 | |
30 | /* | |
31 | * IDT vectors usable for external interrupt sources start | |
32 | * at 0x20: | |
99d113b1 PA |
33 | * hpa said we can start from 0x1f. |
34 | * 0x1f is documented as reserved. However, the ability for the APIC | |
35 | * to generate vectors starting at 0x10 is documented, as is the | |
36 | * ability for the CPU to receive any vector number as an interrupt. | |
37 | * 0x1f is used for IRQ_MOVE_CLEANUP_VECTOR since that vector needs | |
38 | * an entire privilege level (16 vectors) all by itself at a higher | |
39 | * priority than any actual device vector. Thus, by placing it in the | |
40 | * otherwise-unusable 0x10 privilege level, we avoid wasting a full | |
41 | * 16-vector block. | |
9b7dc567 | 42 | */ |
99d113b1 | 43 | #define FIRST_EXTERNAL_VECTOR 0x1f |
9b7dc567 | 44 | |
99d113b1 | 45 | #define IA32_SYSCALL_VECTOR 0x80 |
9b7dc567 | 46 | #ifdef CONFIG_X86_32 |
9fc2e79d | 47 | # define SYSCALL_VECTOR 0x80 |
9b7dc567 TG |
48 | #endif |
49 | ||
50 | /* | |
99d113b1 | 51 | * Reserve the lowest usable priority level 0x10 - 0x1f for triggering |
497c9a19 | 52 | * cleanup after irq migration. |
99d113b1 PA |
53 | * this overlaps with the reserved range for cpu exceptions so this |
54 | * will need to be changed to 0x20 - 0x2f if the last cpu exception is | |
55 | * ever allocated. | |
9b7dc567 | 56 | */ |
99d113b1 | 57 | |
9fc2e79d | 58 | #define IRQ_MOVE_CLEANUP_VECTOR FIRST_EXTERNAL_VECTOR |
9b7dc567 TG |
59 | |
60 | /* | |
99d113b1 PA |
61 | * Vectors 0x20-0x2f are used for ISA interrupts. |
62 | * round up to the next 16-vector boundary | |
9b7dc567 | 63 | */ |
99d113b1 | 64 | #define IRQ0_VECTOR ((FIRST_EXTERNAL_VECTOR + 16) & ~15) |
9fc2e79d IM |
65 | |
66 | #define IRQ1_VECTOR (IRQ0_VECTOR + 1) | |
67 | #define IRQ2_VECTOR (IRQ0_VECTOR + 2) | |
68 | #define IRQ3_VECTOR (IRQ0_VECTOR + 3) | |
69 | #define IRQ4_VECTOR (IRQ0_VECTOR + 4) | |
70 | #define IRQ5_VECTOR (IRQ0_VECTOR + 5) | |
71 | #define IRQ6_VECTOR (IRQ0_VECTOR + 6) | |
72 | #define IRQ7_VECTOR (IRQ0_VECTOR + 7) | |
73 | #define IRQ8_VECTOR (IRQ0_VECTOR + 8) | |
74 | #define IRQ9_VECTOR (IRQ0_VECTOR + 9) | |
75 | #define IRQ10_VECTOR (IRQ0_VECTOR + 10) | |
76 | #define IRQ11_VECTOR (IRQ0_VECTOR + 11) | |
77 | #define IRQ12_VECTOR (IRQ0_VECTOR + 12) | |
78 | #define IRQ13_VECTOR (IRQ0_VECTOR + 13) | |
79 | #define IRQ14_VECTOR (IRQ0_VECTOR + 14) | |
80 | #define IRQ15_VECTOR (IRQ0_VECTOR + 15) | |
9b7dc567 TG |
81 | |
82 | /* | |
83 | * Special IRQ vectors used by the SMP architecture, 0xf0-0xff | |
84 | * | |
85 | * some of the following vectors are 'rare', they are merged | |
86 | * into a single vector (CALL_FUNCTION_VECTOR) to save vector space. | |
87 | * TLB, reschedule and local APIC vectors are performance-critical. | |
9b7dc567 | 88 | */ |
02cf94c3 | 89 | |
5da690d2 | 90 | #define SPURIOUS_APIC_VECTOR 0xff |
647ad94f IM |
91 | /* |
92 | * Sanity check | |
93 | */ | |
94 | #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F) | |
95 | # error SPURIOUS_APIC_VECTOR definition error | |
96 | #endif | |
97 | ||
5da690d2 IM |
98 | #define ERROR_APIC_VECTOR 0xfe |
99 | #define RESCHEDULE_VECTOR 0xfd | |
100 | #define CALL_FUNCTION_VECTOR 0xfc | |
101 | #define CALL_FUNCTION_SINGLE_VECTOR 0xfb | |
102 | #define THERMAL_APIC_VECTOR 0xfa | |
7856f6cc | 103 | #define THRESHOLD_APIC_VECTOR 0xf9 |
4ef702c1 | 104 | #define REBOOT_VECTOR 0xf8 |
9b7dc567 | 105 | |
5da690d2 IM |
106 | /* f0-f7 used for spreading out TLB flushes: */ |
107 | #define INVALIDATE_TLB_VECTOR_END 0xf7 | |
108 | #define INVALIDATE_TLB_VECTOR_START 0xf0 | |
9fc2e79d | 109 | #define NUM_INVALIDATE_TLB_VECTORS 8 |
9b7dc567 | 110 | |
9b7dc567 TG |
111 | /* |
112 | * Local APIC timer IRQ vector is on a different priority level, | |
113 | * to work around the 'lost local interrupt if more than 2 IRQ | |
114 | * sources per level' errata. | |
115 | */ | |
9fc2e79d | 116 | #define LOCAL_TIMER_VECTOR 0xef |
9b7dc567 | 117 | |
193c81b9 | 118 | /* |
acaabe79 | 119 | * Generic system vector for platform specific use |
193c81b9 | 120 | */ |
4a4de9c7 | 121 | #define X86_PLATFORM_IPI_VECTOR 0xed |
193c81b9 | 122 | |
acaabe79 | 123 | /* |
b6276f35 | 124 | * Performance monitoring pending work vector: |
acaabe79 | 125 | */ |
b6276f35 | 126 | #define LOCAL_PENDING_VECTOR 0xec |
acaabe79 | 127 | |
1d865fb7 | 128 | #define UV_BAU_MESSAGE 0xea |
4ef702c1 | 129 | |
ccc3c319 AK |
130 | /* |
131 | * Self IPI vector for machine checks | |
132 | */ | |
133 | #define MCE_SELF_VECTOR 0xeb | |
134 | ||
9b7dc567 | 135 | /* |
ea943966 PA |
136 | * First APIC vector available to drivers: (vectors 0x30-0xee). We |
137 | * start allocating at 0x31 to spread out vectors evenly between | |
138 | * priority levels. (0x80 is the syscall vector) | |
9b7dc567 | 139 | */ |
ea943966 PA |
140 | #define FIRST_DEVICE_VECTOR (IRQ15_VECTOR + 1) |
141 | #define VECTOR_OFFSET_START 1 | |
9b7dc567 | 142 | |
9fc2e79d | 143 | #define NR_VECTORS 256 |
9b7dc567 | 144 | |
9fc2e79d | 145 | #define FPU_IRQ 13 |
9b7dc567 | 146 | |
9fc2e79d IM |
147 | #define FIRST_VM86_IRQ 3 |
148 | #define LAST_VM86_IRQ 15 | |
d8106d2e IM |
149 | |
150 | #ifndef __ASSEMBLY__ | |
151 | static inline int invalid_vm86_irq(int irq) | |
152 | { | |
57e37293 | 153 | return irq < FIRST_VM86_IRQ || irq > LAST_VM86_IRQ; |
d8106d2e IM |
154 | } |
155 | #endif | |
9b7dc567 | 156 | |
009eb3fe IM |
157 | /* |
158 | * Size the maximum number of interrupts. | |
159 | * | |
160 | * If the irq_desc[] array has a sparse layout, we can size things | |
161 | * generously - it scales up linearly with the maximum number of CPUs, | |
162 | * and the maximum number of IO-APICs, whichever is higher. | |
163 | * | |
164 | * In other cases we size more conservatively, to not create too large | |
165 | * static arrays. | |
166 | */ | |
167 | ||
9fc2e79d | 168 | #define NR_IRQS_LEGACY 16 |
99d093d1 | 169 | |
009eb3fe IM |
170 | #define IO_APIC_VECTOR_LIMIT ( 32 * MAX_IO_APICS ) |
171 | ||
3e92ab3d | 172 | #ifdef CONFIG_X86_IO_APIC |
009eb3fe | 173 | # ifdef CONFIG_SPARSE_IRQ |
9959c888 | 174 | # define CPU_VECTOR_LIMIT (64 * NR_CPUS) |
009eb3fe IM |
175 | # define NR_IRQS \ |
176 | (CPU_VECTOR_LIMIT > IO_APIC_VECTOR_LIMIT ? \ | |
177 | (NR_VECTORS + CPU_VECTOR_LIMIT) : \ | |
178 | (NR_VECTORS + IO_APIC_VECTOR_LIMIT)) | |
179 | # else | |
9959c888 YL |
180 | # define CPU_VECTOR_LIMIT (32 * NR_CPUS) |
181 | # define NR_IRQS \ | |
182 | (CPU_VECTOR_LIMIT < IO_APIC_VECTOR_LIMIT ? \ | |
183 | (NR_VECTORS + CPU_VECTOR_LIMIT) : \ | |
184 | (NR_VECTORS + IO_APIC_VECTOR_LIMIT)) | |
c379698f | 185 | # endif |
3e92ab3d | 186 | #else /* !CONFIG_X86_IO_APIC: */ |
009eb3fe | 187 | # define NR_IRQS NR_IRQS_LEGACY |
1b489768 | 188 | #endif |
9b7dc567 | 189 | |
1965aae3 | 190 | #endif /* _ASM_X86_IRQ_VECTORS_H */ |