KVM: x86: use vcpu-specific functions to read/write/translate GFNs
[deliverable/linux.git] / arch / x86 / include / asm / kvm_host.h
CommitLineData
a656c8ef 1/*
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2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This header defines architecture specific interfaces, x86 version
5 *
6 * This work is licensed under the terms of the GNU GPL, version 2. See
7 * the COPYING file in the top-level directory.
8 *
9 */
10
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11#ifndef _ASM_X86_KVM_HOST_H
12#define _ASM_X86_KVM_HOST_H
043405e1 13
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14#include <linux/types.h>
15#include <linux/mm.h>
e930bffe 16#include <linux/mmu_notifier.h>
229456fc 17#include <linux/tracepoint.h>
f5f48ee1 18#include <linux/cpumask.h>
f5132b01 19#include <linux/irq_work.h>
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20
21#include <linux/kvm.h>
22#include <linux/kvm_para.h>
edf88417 23#include <linux/kvm_types.h>
f5132b01 24#include <linux/perf_event.h>
d828199e
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25#include <linux/pvclock_gtod.h>
26#include <linux/clocksource.h>
34c16eec 27
50d0a0f9 28#include <asm/pvclock-abi.h>
e01a1b57 29#include <asm/desc.h>
0bed3b56 30#include <asm/mtrr.h>
9962d032 31#include <asm/msr-index.h>
3ee89722 32#include <asm/asm.h>
e01a1b57 33
cbf64358 34#define KVM_MAX_VCPUS 255
a59cb29e 35#define KVM_SOFT_MAX_VCPUS 160
1d4e7e3c 36#define KVM_USER_MEM_SLOTS 509
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37/* memory slots that are not exposed to userspace */
38#define KVM_PRIVATE_MEM_SLOTS 3
bbacc0c1 39#define KVM_MEM_SLOTS_NUM (KVM_USER_MEM_SLOTS + KVM_PRIVATE_MEM_SLOTS)
93a5cef0 40
69a9f69b 41#define KVM_PIO_PAGE_OFFSET 1
542472b5 42#define KVM_COALESCED_MMIO_PAGE_OFFSET 2
69a9f69b 43
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44#define KVM_IRQCHIP_NUM_PINS KVM_IOAPIC_NUM_PINS
45
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46#define CR0_RESERVED_BITS \
47 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
48 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
49 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
50
346874c9 51#define CR3_L_MODE_RESERVED_BITS 0xFFFFFF0000000000ULL
cfaa790a 52#define CR3_PCID_INVD BIT_64(63)
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53#define CR4_RESERVED_BITS \
54 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
55 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
ad756a16 56 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \
afcbf13f 57 | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \
56d6efc2 58 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE | X86_CR4_SMAP))
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59
60#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
61
62
cd6e8f87 63
cd6e8f87 64#define INVALID_PAGE (~(hpa_t)0)
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65#define VALID_PAGE(x) ((x) != INVALID_PAGE)
66
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67#define UNMAPPED_GVA (~(gpa_t)0)
68
ec04b260 69/* KVM Hugepage definitions for x86 */
04326caa 70#define KVM_NR_PAGE_SIZES 3
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71#define KVM_HPAGE_GFN_SHIFT(x) (((x) - 1) * 9)
72#define KVM_HPAGE_SHIFT(x) (PAGE_SHIFT + KVM_HPAGE_GFN_SHIFT(x))
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73#define KVM_HPAGE_SIZE(x) (1UL << KVM_HPAGE_SHIFT(x))
74#define KVM_HPAGE_MASK(x) (~(KVM_HPAGE_SIZE(x) - 1))
75#define KVM_PAGES_PER_HPAGE(x) (KVM_HPAGE_SIZE(x) / PAGE_SIZE)
05da4558 76
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CD
77static inline gfn_t gfn_to_index(gfn_t gfn, gfn_t base_gfn, int level)
78{
79 /* KVM_HPAGE_GFN_SHIFT(PT_PAGE_TABLE_LEVEL) must be 0. */
80 return (gfn >> KVM_HPAGE_GFN_SHIFT(level)) -
81 (base_gfn >> KVM_HPAGE_GFN_SHIFT(level));
82}
83
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84#define KVM_PERMILLE_MMU_PAGES 20
85#define KVM_MIN_ALLOC_MMU_PAGES 64
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86#define KVM_MMU_HASH_SHIFT 10
87#define KVM_NUM_MMU_PAGES (1 << KVM_MMU_HASH_SHIFT)
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88#define KVM_MIN_FREE_MMU_PAGES 5
89#define KVM_REFILL_PAGES 25
73c1160c 90#define KVM_MAX_CPUID_ENTRIES 80
0bed3b56 91#define KVM_NR_FIXED_MTRR_REGION 88
0d234daf 92#define KVM_NR_VAR_MTRR 8
d657a98e 93
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94#define ASYNC_PF_PER_VCPU 64
95
5fdbf976 96enum kvm_reg {
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97 VCPU_REGS_RAX = 0,
98 VCPU_REGS_RCX = 1,
99 VCPU_REGS_RDX = 2,
100 VCPU_REGS_RBX = 3,
101 VCPU_REGS_RSP = 4,
102 VCPU_REGS_RBP = 5,
103 VCPU_REGS_RSI = 6,
104 VCPU_REGS_RDI = 7,
105#ifdef CONFIG_X86_64
106 VCPU_REGS_R8 = 8,
107 VCPU_REGS_R9 = 9,
108 VCPU_REGS_R10 = 10,
109 VCPU_REGS_R11 = 11,
110 VCPU_REGS_R12 = 12,
111 VCPU_REGS_R13 = 13,
112 VCPU_REGS_R14 = 14,
113 VCPU_REGS_R15 = 15,
114#endif
5fdbf976 115 VCPU_REGS_RIP,
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116 NR_VCPU_REGS
117};
118
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119enum kvm_reg_ex {
120 VCPU_EXREG_PDPTR = NR_VCPU_REGS,
aff48baa 121 VCPU_EXREG_CR3,
6de12732 122 VCPU_EXREG_RFLAGS,
2fb92db1 123 VCPU_EXREG_SEGMENTS,
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AK
124};
125
2b3ccfa0 126enum {
81609e3e 127 VCPU_SREG_ES,
2b3ccfa0 128 VCPU_SREG_CS,
81609e3e 129 VCPU_SREG_SS,
2b3ccfa0 130 VCPU_SREG_DS,
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131 VCPU_SREG_FS,
132 VCPU_SREG_GS,
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133 VCPU_SREG_TR,
134 VCPU_SREG_LDTR,
135};
136
56e82318 137#include <asm/kvm_emulate.h>
2b3ccfa0 138
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139#define KVM_NR_MEM_OBJS 40
140
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141#define KVM_NR_DB_REGS 4
142
143#define DR6_BD (1 << 13)
144#define DR6_BS (1 << 14)
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NA
145#define DR6_RTM (1 << 16)
146#define DR6_FIXED_1 0xfffe0ff0
147#define DR6_INIT 0xffff0ff0
148#define DR6_VOLATILE 0x0001e00f
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149
150#define DR7_BP_EN_MASK 0x000000ff
151#define DR7_GE (1 << 9)
152#define DR7_GD (1 << 13)
153#define DR7_FIXED_1 0x00000400
6f43ed01 154#define DR7_VOLATILE 0xffff2bff
42dbaa5a 155
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NA
156#define PFERR_PRESENT_BIT 0
157#define PFERR_WRITE_BIT 1
158#define PFERR_USER_BIT 2
159#define PFERR_RSVD_BIT 3
160#define PFERR_FETCH_BIT 4
161
162#define PFERR_PRESENT_MASK (1U << PFERR_PRESENT_BIT)
163#define PFERR_WRITE_MASK (1U << PFERR_WRITE_BIT)
164#define PFERR_USER_MASK (1U << PFERR_USER_BIT)
165#define PFERR_RSVD_MASK (1U << PFERR_RSVD_BIT)
166#define PFERR_FETCH_MASK (1U << PFERR_FETCH_BIT)
167
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168/* apic attention bits */
169#define KVM_APIC_CHECK_VAPIC 0
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MT
170/*
171 * The following bit is set with PV-EOI, unset on EOI.
172 * We detect PV-EOI changes by guest by comparing
173 * this bit with PV-EOI in guest memory.
174 * See the implementation in apic_update_pv_eoi.
175 */
176#define KVM_APIC_PV_EOI_PENDING 1
41383771 177
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178/*
179 * We don't want allocation failures within the mmu code, so we preallocate
180 * enough memory for a single page fault in a cache.
181 */
182struct kvm_mmu_memory_cache {
183 int nobjs;
184 void *objects[KVM_NR_MEM_OBJS];
185};
186
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187/*
188 * kvm_mmu_page_role, below, is defined as:
189 *
190 * bits 0:3 - total guest paging levels (2-4, or zero for real mode)
191 * bits 4:7 - page table level for this shadow (1-4)
192 * bits 8:9 - page table quadrant for 2-level guests
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193 * bit 16 - direct mapping of virtual to physical mapping at gfn
194 * used for real mode and two-dimensional paging
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195 * bits 17:19 - common access permissions for all ptes in this shadow page
196 */
197union kvm_mmu_page_role {
198 unsigned word;
199 struct {
7d76b4d3 200 unsigned level:4;
5b7e0102 201 unsigned cr4_pae:1;
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JP
202 unsigned quadrant:2;
203 unsigned pad_for_nice_hex_output:6;
f6e2c02b 204 unsigned direct:1;
7d76b4d3 205 unsigned access:3;
2e53d63a 206 unsigned invalid:1;
9645bb56 207 unsigned nxe:1;
3dbe1415 208 unsigned cr0_wp:1;
411c588d 209 unsigned smep_andnot_wp:1;
edc90b7d 210 unsigned smap_andnot_wp:1;
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211 };
212};
213
214struct kvm_mmu_page {
215 struct list_head link;
216 struct hlist_node hash_link;
217
218 /*
219 * The following two entries are used to key the shadow page in the
220 * hash table.
221 */
222 gfn_t gfn;
223 union kvm_mmu_page_role role;
224
225 u64 *spt;
226 /* hold the gfn of each spte inside spt */
227 gfn_t *gfns;
4731d4c7 228 bool unsync;
0571d366 229 int root_count; /* Currently serving as active root */
60c8aec6 230 unsigned int unsync_children;
67052b35 231 unsigned long parent_ptes; /* Reverse mapping for parent_pte */
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232
233 /* The page is obsolete if mmu_valid_gen != kvm->arch.mmu_valid_gen. */
5304b8d3 234 unsigned long mmu_valid_gen;
f6f8adee 235
0074ff63 236 DECLARE_BITMAP(unsync_child_bitmap, 512);
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XG
237
238#ifdef CONFIG_X86_32
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239 /*
240 * Used out of the mmu-lock to avoid reading spte values while an
241 * update is in progress; see the comments in __get_spte_lockless().
242 */
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243 int clear_spte_count;
244#endif
245
0cbf8e43 246 /* Number of writes since the last time traversal visited this page. */
a30f47cb 247 int write_flooding_count;
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248};
249
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250struct kvm_pio_request {
251 unsigned long count;
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252 int in;
253 int port;
254 int size;
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AK
255};
256
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257/*
258 * x86 supports 3 paging modes (4-level 64-bit, 3-level 64-bit, and 2-level
259 * 32-bit). The kvm_mmu structure abstracts the details of the current mmu
260 * mode.
261 */
262struct kvm_mmu {
f43addd4 263 void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long root);
5777ed34 264 unsigned long (*get_cr3)(struct kvm_vcpu *vcpu);
e4e517b4 265 u64 (*get_pdptr)(struct kvm_vcpu *vcpu, int index);
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266 int (*page_fault)(struct kvm_vcpu *vcpu, gva_t gva, u32 err,
267 bool prefault);
6389ee94
AK
268 void (*inject_page_fault)(struct kvm_vcpu *vcpu,
269 struct x86_exception *fault);
1871c602 270 gpa_t (*gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t gva, u32 access,
ab9ae313 271 struct x86_exception *exception);
54987b7a
PB
272 gpa_t (*translate_gpa)(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
273 struct x86_exception *exception);
e8bc217a 274 int (*sync_page)(struct kvm_vcpu *vcpu,
a4a8e6f7 275 struct kvm_mmu_page *sp);
a7052897 276 void (*invlpg)(struct kvm_vcpu *vcpu, gva_t gva);
0f53b5b1 277 void (*update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
7c562522 278 u64 *spte, const void *pte);
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279 hpa_t root_hpa;
280 int root_level;
281 int shadow_root_level;
a770f6f2 282 union kvm_mmu_page_role base_role;
c5a78f2b 283 bool direct_map;
d657a98e 284
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285 /*
286 * Bitmap; bit set = permission fault
287 * Byte index: page fault error code [4:1]
288 * Bit index: pte permissions in ACC_* format
289 */
290 u8 permissions[16];
291
d657a98e 292 u64 *pae_root;
81407ca5 293 u64 *lm_root;
82725b20 294 u64 rsvd_bits_mask[2][4];
25d92081 295 u64 bad_mt_xwr;
ff03a073 296
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297 /*
298 * Bitmap: bit set = last pte in walk
299 * index[0:1]: level (zero-based)
300 * index[2]: pte.ps
301 */
302 u8 last_pte_bitmap;
303
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JR
304 bool nx;
305
ff03a073 306 u64 pdptrs[4]; /* pae */
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ZX
307};
308
f5132b01
GN
309enum pmc_type {
310 KVM_PMC_GP = 0,
311 KVM_PMC_FIXED,
312};
313
314struct kvm_pmc {
315 enum pmc_type type;
316 u8 idx;
317 u64 counter;
318 u64 eventsel;
319 struct perf_event *perf_event;
320 struct kvm_vcpu *vcpu;
321};
322
323struct kvm_pmu {
324 unsigned nr_arch_gp_counters;
325 unsigned nr_arch_fixed_counters;
326 unsigned available_event_types;
327 u64 fixed_ctr_ctrl;
328 u64 global_ctrl;
329 u64 global_status;
330 u64 global_ovf_ctrl;
331 u64 counter_bitmask[2];
332 u64 global_ctrl_mask;
103af0a9 333 u64 reserved_bits;
f5132b01 334 u8 version;
15c7ad51
RR
335 struct kvm_pmc gp_counters[INTEL_PMC_MAX_GENERIC];
336 struct kvm_pmc fixed_counters[INTEL_PMC_MAX_FIXED];
f5132b01
GN
337 struct irq_work irq_work;
338 u64 reprogram_pmi;
339};
340
360b948d
PB
341enum {
342 KVM_DEBUGREG_BP_ENABLED = 1,
c77fb5fe 343 KVM_DEBUGREG_WONT_EXIT = 2,
ae561ede 344 KVM_DEBUGREG_RELOAD = 4,
360b948d
PB
345};
346
ad312c7c 347struct kvm_vcpu_arch {
5fdbf976
MT
348 /*
349 * rip and regs accesses must go through
350 * kvm_{register,rip}_{read,write} functions.
351 */
352 unsigned long regs[NR_VCPU_REGS];
353 u32 regs_avail;
354 u32 regs_dirty;
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ZX
355
356 unsigned long cr0;
e8467fda 357 unsigned long cr0_guest_owned_bits;
34c16eec
ZX
358 unsigned long cr2;
359 unsigned long cr3;
360 unsigned long cr4;
fc78f519 361 unsigned long cr4_guest_owned_bits;
34c16eec 362 unsigned long cr8;
1371d904 363 u32 hflags;
f6801dff 364 u64 efer;
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ZX
365 u64 apic_base;
366 struct kvm_lapic *apic; /* kernel irqchip context */
41383771 367 unsigned long apic_attention;
e1035715 368 int32_t apic_arb_prio;
34c16eec 369 int mp_state;
34c16eec 370 u64 ia32_misc_enable_msr;
64d60670 371 u64 smbase;
b209749f 372 bool tpr_access_reporting;
20300099 373 u64 ia32_xss;
34c16eec 374
14dfe855
JR
375 /*
376 * Paging state of the vcpu
377 *
378 * If the vcpu runs in guest mode with two level paging this still saves
379 * the paging mode of the l1 guest. This context is always used to
380 * handle faults.
381 */
34c16eec 382 struct kvm_mmu mmu;
8df25a32 383
6539e738
JR
384 /*
385 * Paging state of an L2 guest (used for nested npt)
386 *
387 * This context will save all necessary information to walk page tables
388 * of the an L2 guest. This context is only initialized for page table
389 * walking and not for faulting since we never handle l2 page faults on
390 * the host.
391 */
392 struct kvm_mmu nested_mmu;
393
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JR
394 /*
395 * Pointer to the mmu context currently used for
396 * gva_to_gpa translations.
397 */
398 struct kvm_mmu *walk_mmu;
399
53c07b18 400 struct kvm_mmu_memory_cache mmu_pte_list_desc_cache;
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ZX
401 struct kvm_mmu_memory_cache mmu_page_cache;
402 struct kvm_mmu_memory_cache mmu_page_header_cache;
403
98918833 404 struct fpu guest_fpu;
c447e76b 405 bool eager_fpu;
2acf923e 406 u64 xcr0;
d7876f1b 407 u64 guest_supported_xcr0;
4344ee98 408 u32 guest_xstate_size;
34c16eec 409
34c16eec
ZX
410 struct kvm_pio_request pio;
411 void *pio_data;
412
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GN
413 u8 event_exit_inst_len;
414
298101da
AK
415 struct kvm_queued_exception {
416 bool pending;
417 bool has_error_code;
ce7ddec4 418 bool reinject;
298101da
AK
419 u8 nr;
420 u32 error_code;
421 } exception;
422
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AK
423 struct kvm_queued_interrupt {
424 bool pending;
66fd3f7f 425 bool soft;
937a7eae
AK
426 u8 nr;
427 } interrupt;
428
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ZX
429 int halt_request; /* real mode on Intel only */
430
431 int cpuid_nent;
07716717 432 struct kvm_cpuid_entry2 cpuid_entries[KVM_MAX_CPUID_ENTRIES];
5a4f55cd
EK
433
434 int maxphyaddr;
435
34c16eec
ZX
436 /* emulate context */
437
438 struct x86_emulate_ctxt emulate_ctxt;
7ae441ea
GN
439 bool emulate_regs_need_sync_to_vcpu;
440 bool emulate_regs_need_sync_from_vcpu;
716d51ab 441 int (*complete_userspace_io)(struct kvm_vcpu *vcpu);
18068523
GOC
442
443 gpa_t time;
50d0a0f9 444 struct pvclock_vcpu_time_info hv_clock;
e48672fa 445 unsigned int hw_tsc_khz;
0b79459b
AH
446 struct gfn_to_hva_cache pv_time;
447 bool pv_time_enabled;
51d59c6b
MT
448 /* set guest stopped flag in pvclock flags field */
449 bool pvclock_set_guest_stopped_request;
c9aaa895
GC
450
451 struct {
452 u64 msr_val;
453 u64 last_steal;
454 u64 accum_steal;
455 struct gfn_to_hva_cache stime;
456 struct kvm_steal_time steal;
457 } st;
458
1d5f066e 459 u64 last_guest_tsc;
6f526ec5 460 u64 last_host_tsc;
0dd6a6ed 461 u64 tsc_offset_adjustment;
e26101b1
ZA
462 u64 this_tsc_nsec;
463 u64 this_tsc_write;
0d3da0d2 464 u64 this_tsc_generation;
c285545f 465 bool tsc_catchup;
cc578287
ZA
466 bool tsc_always_catchup;
467 s8 virtual_tsc_shift;
468 u32 virtual_tsc_mult;
469 u32 virtual_tsc_khz;
ba904635 470 s64 ia32_tsc_adjust_msr;
3419ffc8 471
7460fb4a
AK
472 atomic_t nmi_queued; /* unprocessed asynchronous NMIs */
473 unsigned nmi_pending; /* NMI queued after currently running handler */
474 bool nmi_injected; /* Trying to inject an NMI this entry */
f077825a 475 bool smi_pending; /* SMI queued after currently running handler */
9ba075a6 476
0bed3b56 477 struct mtrr_state_type mtrr_state;
7cb060a9 478 u64 pat;
42dbaa5a 479
360b948d 480 unsigned switch_db_regs;
42dbaa5a
JK
481 unsigned long db[KVM_NR_DB_REGS];
482 unsigned long dr6;
483 unsigned long dr7;
484 unsigned long eff_db[KVM_NR_DB_REGS];
c8639010 485 unsigned long guest_debug_dr7;
890ca9ae
HY
486
487 u64 mcg_cap;
488 u64 mcg_status;
489 u64 mcg_ctl;
490 u64 *mce_banks;
94fe45da 491
bebb106a
XG
492 /* Cache MMIO info */
493 u64 mmio_gva;
494 unsigned access;
495 gfn_t mmio_gfn;
56f17dd3 496 u64 mmio_gen;
bebb106a 497
f5132b01
GN
498 struct kvm_pmu pmu;
499
94fe45da 500 /* used for guest single stepping over the given code position */
94fe45da 501 unsigned long singlestep_rip;
f92653ee 502
10388a07
GN
503 /* fields used by HYPER-V emulation */
504 u64 hv_vapic;
f5f48ee1
SY
505
506 cpumask_var_t wbinvd_dirty_mask;
af585b92 507
1cb3f3ae
XG
508 unsigned long last_retry_eip;
509 unsigned long last_retry_addr;
510
af585b92
GN
511 struct {
512 bool halted;
513 gfn_t gfns[roundup_pow_of_two(ASYNC_PF_PER_VCPU)];
344d9588
GN
514 struct gfn_to_hva_cache data;
515 u64 msr_val;
7c90705b 516 u32 id;
6adba527 517 bool send_user_only;
af585b92 518 } apf;
2b036c6b
BO
519
520 /* OSVW MSRs (AMD only) */
521 struct {
522 u64 length;
523 u64 status;
524 } osvw;
ae7a2a3f
MT
525
526 struct {
527 u64 msr_val;
528 struct gfn_to_hva_cache data;
529 } pv_eoi;
93c05d3e
XG
530
531 /*
532 * Indicate whether the access faults on its page table in guest
533 * which is set when fix page fault and used to detect unhandeable
534 * instruction.
535 */
536 bool write_fault_to_shadow_pgtable;
25d92081
YZ
537
538 /* set at EPT violation at this point */
539 unsigned long exit_qualification;
6aef266c
SV
540
541 /* pv related host specific info */
542 struct {
543 bool pv_unhalted;
544 } pv;
34c16eec
ZX
545};
546
db3fe4eb 547struct kvm_lpage_info {
db3fe4eb
TY
548 int write_count;
549};
550
551struct kvm_arch_memory_slot {
d89cc617 552 unsigned long *rmap[KVM_NR_PAGE_SIZES];
db3fe4eb
TY
553 struct kvm_lpage_info *lpage_info[KVM_NR_PAGE_SIZES - 1];
554};
555
3548a259
RK
556/*
557 * We use as the mode the number of bits allocated in the LDR for the
558 * logical processor ID. It happens that these are all powers of two.
559 * This makes it is very easy to detect cases where the APICs are
560 * configured for multiple modes; in that case, we cannot use the map and
561 * hence cannot use kvm_irq_delivery_to_apic_fast either.
562 */
563#define KVM_APIC_MODE_XAPIC_CLUSTER 4
564#define KVM_APIC_MODE_XAPIC_FLAT 8
565#define KVM_APIC_MODE_X2APIC 16
566
1e08ec4a
GN
567struct kvm_apic_map {
568 struct rcu_head rcu;
3548a259 569 u8 mode;
1e08ec4a
GN
570 struct kvm_lapic *phys_map[256];
571 /* first index is cluster id second is cpu id in a cluster */
572 struct kvm_lapic *logical_map[16][16];
573};
574
fef9cce0 575struct kvm_arch {
49d5ca26 576 unsigned int n_used_mmu_pages;
f05e70ac 577 unsigned int n_requested_mmu_pages;
39de71ec 578 unsigned int n_max_mmu_pages;
332b207d 579 unsigned int indirect_shadow_pages;
5304b8d3 580 unsigned long mmu_valid_gen;
f05e70ac
ZX
581 struct hlist_head mmu_page_hash[KVM_NUM_MMU_PAGES];
582 /*
583 * Hash table of struct kvm_mmu_page.
584 */
585 struct list_head active_mmu_pages;
365c8868
XG
586 struct list_head zapped_obsolete_pages;
587
4d5c5d0f 588 struct list_head assigned_dev_head;
19de40a8 589 struct iommu_domain *iommu_domain;
d96eb2c6 590 bool iommu_noncoherent;
e0f0bbc5
AW
591#define __KVM_HAVE_ARCH_NONCOHERENT_DMA
592 atomic_t noncoherent_dma_count;
d7deeeb0
ZX
593 struct kvm_pic *vpic;
594 struct kvm_ioapic *vioapic;
7837699f 595 struct kvm_pit *vpit;
cc6e462c 596 int vapics_in_nmi_mode;
1e08ec4a
GN
597 struct mutex apic_map_lock;
598 struct kvm_apic_map *apic_map;
bfc6d222 599
bfc6d222 600 unsigned int tss_addr;
c24ae0dc 601 bool apic_access_page_done;
18068523
GOC
602
603 gpa_t wall_clock;
b7ebfb05 604
b7ebfb05 605 bool ept_identity_pagetable_done;
b927a3ce 606 gpa_t ept_identity_map_addr;
5550af4d
SY
607
608 unsigned long irq_sources_bitmap;
afbcf7ab 609 s64 kvmclock_offset;
038f8c11 610 raw_spinlock_t tsc_write_lock;
f38e098f 611 u64 last_tsc_nsec;
f38e098f 612 u64 last_tsc_write;
5d3cb0f6 613 u32 last_tsc_khz;
e26101b1
ZA
614 u64 cur_tsc_nsec;
615 u64 cur_tsc_write;
616 u64 cur_tsc_offset;
0d3da0d2 617 u64 cur_tsc_generation;
b48aa97e 618 int nr_vcpus_matched_tsc;
ffde22ac 619
d828199e
MT
620 spinlock_t pvclock_gtod_sync_lock;
621 bool use_master_clock;
622 u64 master_kernel_ns;
623 cycle_t master_cycle_now;
7e44e449 624 struct delayed_work kvmclock_update_work;
332967a3 625 struct delayed_work kvmclock_sync_work;
d828199e 626
ffde22ac 627 struct kvm_xen_hvm_config xen_hvm_config;
55cd8e5a 628
6ef768fa
PB
629 /* reads protected by irq_srcu, writes by irq_lock */
630 struct hlist_head mask_notifier_list;
631
55cd8e5a
GN
632 /* fields used by HYPER-V emulation */
633 u64 hv_guest_os_id;
634 u64 hv_hypercall;
e984097b 635 u64 hv_tsc_page;
b034cf01
XG
636
637 #ifdef CONFIG_KVM_MMU_AUDIT
638 int audit_point;
639 #endif
54750f2c
MT
640
641 bool boot_vcpu_runs_old_kvmclock;
90de4a18
NA
642
643 u64 disabled_quirks;
d69fb81f
ZX
644};
645
0711456c
ZX
646struct kvm_vm_stat {
647 u32 mmu_shadow_zapped;
648 u32 mmu_pte_write;
649 u32 mmu_pte_updated;
650 u32 mmu_pde_zapped;
651 u32 mmu_flooded;
652 u32 mmu_recycled;
dfc5aa00 653 u32 mmu_cache_miss;
4731d4c7 654 u32 mmu_unsync;
0711456c 655 u32 remote_tlb_flush;
05da4558 656 u32 lpages;
0711456c
ZX
657};
658
77b4c255
ZX
659struct kvm_vcpu_stat {
660 u32 pf_fixed;
661 u32 pf_guest;
662 u32 tlb_flush;
663 u32 invlpg;
664
665 u32 exits;
666 u32 io_exits;
667 u32 mmio_exits;
668 u32 signal_exits;
669 u32 irq_window_exits;
f08864b4 670 u32 nmi_window_exits;
77b4c255 671 u32 halt_exits;
f7819512 672 u32 halt_successful_poll;
77b4c255
ZX
673 u32 halt_wakeup;
674 u32 request_irq_exits;
675 u32 irq_exits;
676 u32 host_state_reload;
677 u32 efer_reload;
678 u32 fpu_reload;
679 u32 insn_emulation;
680 u32 insn_emulation_fail;
f11c3a8d 681 u32 hypercalls;
fa89a817 682 u32 irq_injections;
c4abb7c9 683 u32 nmi_injections;
77b4c255 684};
ad312c7c 685
8a76d7f2
JR
686struct x86_instruction_info;
687
8fe8ab46
WA
688struct msr_data {
689 bool host_initiated;
690 u32 index;
691 u64 data;
692};
693
cb5281a5
PB
694struct kvm_lapic_irq {
695 u32 vector;
b7cb2231
PB
696 u16 delivery_mode;
697 u16 dest_mode;
698 bool level;
699 u16 trig_mode;
cb5281a5
PB
700 u32 shorthand;
701 u32 dest_id;
93bbf0b8 702 bool msi_redir_hint;
cb5281a5
PB
703};
704
ea4a5ff8
ZX
705struct kvm_x86_ops {
706 int (*cpu_has_kvm_support)(void); /* __init */
707 int (*disabled_by_bios)(void); /* __init */
13a34e06
RK
708 int (*hardware_enable)(void);
709 void (*hardware_disable)(void);
ea4a5ff8
ZX
710 void (*check_processor_compatibility)(void *rtn);
711 int (*hardware_setup)(void); /* __init */
712 void (*hardware_unsetup)(void); /* __exit */
774ead3a 713 bool (*cpu_has_accelerated_tpr)(void);
0e851880 714 void (*cpuid_update)(struct kvm_vcpu *vcpu);
ea4a5ff8
ZX
715
716 /* Create, but do not attach this VCPU */
717 struct kvm_vcpu *(*vcpu_create)(struct kvm *kvm, unsigned id);
718 void (*vcpu_free)(struct kvm_vcpu *vcpu);
d28bc9dd 719 void (*vcpu_reset)(struct kvm_vcpu *vcpu, bool init_event);
ea4a5ff8
ZX
720
721 void (*prepare_guest_switch)(struct kvm_vcpu *vcpu);
722 void (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu);
723 void (*vcpu_put)(struct kvm_vcpu *vcpu);
ea4a5ff8 724
c8639010 725 void (*update_db_bp_intercept)(struct kvm_vcpu *vcpu);
609e36d3 726 int (*get_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr);
8fe8ab46 727 int (*set_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr);
ea4a5ff8
ZX
728 u64 (*get_segment_base)(struct kvm_vcpu *vcpu, int seg);
729 void (*get_segment)(struct kvm_vcpu *vcpu,
730 struct kvm_segment *var, int seg);
2e4d2653 731 int (*get_cpl)(struct kvm_vcpu *vcpu);
ea4a5ff8
ZX
732 void (*set_segment)(struct kvm_vcpu *vcpu,
733 struct kvm_segment *var, int seg);
734 void (*get_cs_db_l_bits)(struct kvm_vcpu *vcpu, int *db, int *l);
e8467fda 735 void (*decache_cr0_guest_bits)(struct kvm_vcpu *vcpu);
aff48baa 736 void (*decache_cr3)(struct kvm_vcpu *vcpu);
ea4a5ff8
ZX
737 void (*decache_cr4_guest_bits)(struct kvm_vcpu *vcpu);
738 void (*set_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0);
739 void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3);
5e1746d6 740 int (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4);
ea4a5ff8 741 void (*set_efer)(struct kvm_vcpu *vcpu, u64 efer);
89a27f4d
GN
742 void (*get_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt);
743 void (*set_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt);
744 void (*get_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt);
745 void (*set_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt);
73aaf249
JK
746 u64 (*get_dr6)(struct kvm_vcpu *vcpu);
747 void (*set_dr6)(struct kvm_vcpu *vcpu, unsigned long value);
c77fb5fe 748 void (*sync_dirty_debug_regs)(struct kvm_vcpu *vcpu);
020df079 749 void (*set_dr7)(struct kvm_vcpu *vcpu, unsigned long value);
5fdbf976 750 void (*cache_reg)(struct kvm_vcpu *vcpu, enum kvm_reg reg);
ea4a5ff8
ZX
751 unsigned long (*get_rflags)(struct kvm_vcpu *vcpu);
752 void (*set_rflags)(struct kvm_vcpu *vcpu, unsigned long rflags);
0fdd74f7 753 void (*fpu_activate)(struct kvm_vcpu *vcpu);
02daab21 754 void (*fpu_deactivate)(struct kvm_vcpu *vcpu);
ea4a5ff8
ZX
755
756 void (*tlb_flush)(struct kvm_vcpu *vcpu);
ea4a5ff8 757
851ba692
AK
758 void (*run)(struct kvm_vcpu *vcpu);
759 int (*handle_exit)(struct kvm_vcpu *vcpu);
ea4a5ff8 760 void (*skip_emulated_instruction)(struct kvm_vcpu *vcpu);
2809f5d2 761 void (*set_interrupt_shadow)(struct kvm_vcpu *vcpu, int mask);
37ccdcbe 762 u32 (*get_interrupt_shadow)(struct kvm_vcpu *vcpu);
ea4a5ff8
ZX
763 void (*patch_hypercall)(struct kvm_vcpu *vcpu,
764 unsigned char *hypercall_addr);
66fd3f7f 765 void (*set_irq)(struct kvm_vcpu *vcpu);
95ba8273 766 void (*set_nmi)(struct kvm_vcpu *vcpu);
298101da 767 void (*queue_exception)(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR
768 bool has_error_code, u32 error_code,
769 bool reinject);
b463a6f7 770 void (*cancel_injection)(struct kvm_vcpu *vcpu);
78646121 771 int (*interrupt_allowed)(struct kvm_vcpu *vcpu);
95ba8273 772 int (*nmi_allowed)(struct kvm_vcpu *vcpu);
3cfc3092
JK
773 bool (*get_nmi_mask)(struct kvm_vcpu *vcpu);
774 void (*set_nmi_mask)(struct kvm_vcpu *vcpu, bool masked);
c9a7953f
JK
775 void (*enable_nmi_window)(struct kvm_vcpu *vcpu);
776 void (*enable_irq_window)(struct kvm_vcpu *vcpu);
95ba8273 777 void (*update_cr8_intercept)(struct kvm_vcpu *vcpu, int tpr, int irr);
c7c9c56c
YZ
778 int (*vm_has_apicv)(struct kvm *kvm);
779 void (*hwapic_irr_update)(struct kvm_vcpu *vcpu, int max_irr);
780 void (*hwapic_isr_update)(struct kvm *kvm, int isr);
781 void (*load_eoi_exitmap)(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap);
8d14695f 782 void (*set_virtual_x2apic_mode)(struct kvm_vcpu *vcpu, bool set);
4256f43f 783 void (*set_apic_access_page_addr)(struct kvm_vcpu *vcpu, hpa_t hpa);
a20ed54d
YZ
784 void (*deliver_posted_interrupt)(struct kvm_vcpu *vcpu, int vector);
785 void (*sync_pir_to_irr)(struct kvm_vcpu *vcpu);
ea4a5ff8 786 int (*set_tss_addr)(struct kvm *kvm, unsigned int addr);
67253af5 787 int (*get_tdp_level)(void);
4b12f0de 788 u64 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio);
17cc3935 789 int (*get_lpage_level)(void);
4e47c7a6 790 bool (*rdtscp_supported)(void);
ad756a16 791 bool (*invpcid_supported)(void);
f1e2b260 792 void (*adjust_tsc_offset)(struct kvm_vcpu *vcpu, s64 adjustment, bool host);
344f414f 793
1c97f0a0
JR
794 void (*set_tdp_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3);
795
d4330ef2
JR
796 void (*set_supported_cpuid)(u32 func, struct kvm_cpuid_entry2 *entry);
797
f5f48ee1
SY
798 bool (*has_wbinvd_exit)(void);
799
cc578287 800 void (*set_tsc_khz)(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale);
ba904635 801 u64 (*read_tsc_offset)(struct kvm_vcpu *vcpu);
99e3e30a
ZA
802 void (*write_tsc_offset)(struct kvm_vcpu *vcpu, u64 offset);
803
857e4099 804 u64 (*compute_tsc_offset)(struct kvm_vcpu *vcpu, u64 target_tsc);
886b470c 805 u64 (*read_l1_tsc)(struct kvm_vcpu *vcpu, u64 host_tsc);
857e4099 806
586f9607 807 void (*get_exit_info)(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2);
8a76d7f2
JR
808
809 int (*check_intercept)(struct kvm_vcpu *vcpu,
810 struct x86_instruction_info *info,
811 enum x86_intercept_stage stage);
a547c6db 812 void (*handle_external_intr)(struct kvm_vcpu *vcpu);
da8999d3 813 bool (*mpx_supported)(void);
55412b2e 814 bool (*xsaves_supported)(void);
b6b8a145
JK
815
816 int (*check_nested_events)(struct kvm_vcpu *vcpu, bool external_intr);
ae97a3b8
RK
817
818 void (*sched_in)(struct kvm_vcpu *kvm, int cpu);
88178fd4
KH
819
820 /*
821 * Arch-specific dirty logging hooks. These hooks are only supposed to
822 * be valid if the specific arch has hardware-accelerated dirty logging
823 * mechanism. Currently only for PML on VMX.
824 *
825 * - slot_enable_log_dirty:
826 * called when enabling log dirty mode for the slot.
827 * - slot_disable_log_dirty:
828 * called when disabling log dirty mode for the slot.
829 * also called when slot is created with log dirty disabled.
830 * - flush_log_dirty:
831 * called before reporting dirty_bitmap to userspace.
832 * - enable_log_dirty_pt_masked:
833 * called when reenabling log dirty for the GFNs in the mask after
834 * corresponding bits are cleared in slot->dirty_bitmap.
835 */
836 void (*slot_enable_log_dirty)(struct kvm *kvm,
837 struct kvm_memory_slot *slot);
838 void (*slot_disable_log_dirty)(struct kvm *kvm,
839 struct kvm_memory_slot *slot);
840 void (*flush_log_dirty)(struct kvm *kvm);
841 void (*enable_log_dirty_pt_masked)(struct kvm *kvm,
842 struct kvm_memory_slot *slot,
843 gfn_t offset, unsigned long mask);
ea4a5ff8
ZX
844};
845
af585b92 846struct kvm_arch_async_pf {
7c90705b 847 u32 token;
af585b92 848 gfn_t gfn;
fb67e14f 849 unsigned long cr3;
c4806acd 850 bool direct_map;
af585b92
GN
851};
852
97896d04
ZX
853extern struct kvm_x86_ops *kvm_x86_ops;
854
f1e2b260
MT
855static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
856 s64 adjustment)
857{
858 kvm_x86_ops->adjust_tsc_offset(vcpu, adjustment, false);
859}
860
861static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
862{
863 kvm_x86_ops->adjust_tsc_offset(vcpu, adjustment, true);
864}
865
54f1585a
ZX
866int kvm_mmu_module_init(void);
867void kvm_mmu_module_exit(void);
868
869void kvm_mmu_destroy(struct kvm_vcpu *vcpu);
870int kvm_mmu_create(struct kvm_vcpu *vcpu);
8a3c1a33 871void kvm_mmu_setup(struct kvm_vcpu *vcpu);
7b52345e 872void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
4b12f0de 873 u64 dirty_mask, u64 nx_mask, u64 x_mask);
54f1585a 874
8a3c1a33 875void kvm_mmu_reset_context(struct kvm_vcpu *vcpu);
1c91cad4
KH
876void kvm_mmu_slot_remove_write_access(struct kvm *kvm,
877 struct kvm_memory_slot *memslot);
3ea3b7fa 878void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm,
f36f3f28 879 const struct kvm_memory_slot *memslot);
f4b4b180
KH
880void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm,
881 struct kvm_memory_slot *memslot);
882void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm,
883 struct kvm_memory_slot *memslot);
884void kvm_mmu_slot_set_dirty(struct kvm *kvm,
885 struct kvm_memory_slot *memslot);
886void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm,
887 struct kvm_memory_slot *slot,
888 gfn_t gfn_offset, unsigned long mask);
54f1585a 889void kvm_mmu_zap_all(struct kvm *kvm);
54bf36aa 890void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, struct kvm_memslots *slots);
3ad82a7e 891unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm);
54f1585a
ZX
892void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages);
893
ff03a073 894int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3);
cc4b6871 895
3200f405 896int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 897 const void *val, int bytes);
4b12f0de 898u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn);
2f333bcb 899
6ef768fa
PB
900struct kvm_irq_mask_notifier {
901 void (*func)(struct kvm_irq_mask_notifier *kimn, bool masked);
902 int irq;
903 struct hlist_node link;
904};
905
906void kvm_register_irq_mask_notifier(struct kvm *kvm, int irq,
907 struct kvm_irq_mask_notifier *kimn);
908void kvm_unregister_irq_mask_notifier(struct kvm *kvm, int irq,
909 struct kvm_irq_mask_notifier *kimn);
910void kvm_fire_mask_notifiers(struct kvm *kvm, unsigned irqchip, unsigned pin,
911 bool mask);
912
2f333bcb 913extern bool tdp_enabled;
9f811285 914
a3e06bbe
LJ
915u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu);
916
92a1f12d
JR
917/* control of guest tsc rate supported? */
918extern bool kvm_has_tsc_control;
919/* minimum supported tsc_khz for guests */
920extern u32 kvm_min_guest_tsc_khz;
921/* maximum supported tsc_khz for guests */
922extern u32 kvm_max_guest_tsc_khz;
923
54f1585a 924enum emulation_result {
ac0a48c3
PB
925 EMULATE_DONE, /* no further processing */
926 EMULATE_USER_EXIT, /* kvm_run ready for userspace exit */
54f1585a
ZX
927 EMULATE_FAIL, /* can't emulate this instruction */
928};
929
571008da
SY
930#define EMULTYPE_NO_DECODE (1 << 0)
931#define EMULTYPE_TRAP_UD (1 << 1)
ba8afb6b 932#define EMULTYPE_SKIP (1 << 2)
1cb3f3ae 933#define EMULTYPE_RETRY (1 << 3)
991eebf9 934#define EMULTYPE_NO_REEXECUTE (1 << 4)
dc25e89e
AP
935int x86_emulate_instruction(struct kvm_vcpu *vcpu, unsigned long cr2,
936 int emulation_type, void *insn, int insn_len);
51d8b661
AP
937
938static inline int emulate_instruction(struct kvm_vcpu *vcpu,
939 int emulation_type)
940{
dc25e89e 941 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
51d8b661
AP
942}
943
f2b4b7dd 944void kvm_enable_efer_bits(u64);
384bb783 945bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer);
609e36d3 946int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr);
8fe8ab46 947int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr);
54f1585a
ZX
948
949struct x86_emulate_ctxt;
950
cf8f70bf 951int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port);
54f1585a
ZX
952void kvm_emulate_cpuid(struct kvm_vcpu *vcpu);
953int kvm_emulate_halt(struct kvm_vcpu *vcpu);
5cb56059 954int kvm_vcpu_halt(struct kvm_vcpu *vcpu);
f5f48ee1 955int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu);
54f1585a 956
3e6e0aab 957void kvm_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
c697518a 958int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg);
2b4a273b 959void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector);
3e6e0aab 960
7f3d35fd
KW
961int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
962 int reason, bool has_error_code, u32 error_code);
37817f29 963
49a9b07e 964int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
2390218b 965int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
a83b29c6 966int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
eea1cff9 967int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8);
020df079
GN
968int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val);
969int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val);
2d3ad1f4
AK
970unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu);
971void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw);
54f1585a 972void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l);
2acf923e 973int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr);
54f1585a 974
609e36d3 975int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr);
8fe8ab46 976int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr);
54f1585a 977
91586a3b
JK
978unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu);
979void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
022cd0e8 980bool kvm_rdpmc(struct kvm_vcpu *vcpu);
91586a3b 981
298101da
AK
982void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr);
983void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code);
ce7ddec4
JR
984void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr);
985void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code);
6389ee94 986void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault);
ec92fe44
JR
987int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
988 gfn_t gfn, void *data, int offset, int len,
989 u32 access);
0a79b009 990bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl);
16f8a6f9 991bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr);
298101da 992
1a577b72
MT
993static inline int __kvm_irq_line_state(unsigned long *irq_state,
994 int irq_source_id, int level)
995{
996 /* Logical OR for level trig interrupt */
997 if (level)
998 __set_bit(irq_source_id, irq_state);
999 else
1000 __clear_bit(irq_source_id, irq_state);
1001
1002 return !!(*irq_state);
1003}
1004
1005int kvm_pic_set_irq(struct kvm_pic *pic, int irq, int irq_source_id, int level);
1006void kvm_pic_clear_all(struct kvm_pic *pic, int irq_source_id);
3de42dc0 1007
3419ffc8
SY
1008void kvm_inject_nmi(struct kvm_vcpu *vcpu);
1009
d28bc9dd 1010int fx_init(struct kvm_vcpu *vcpu, bool init_event);
54f1585a 1011
54f1585a 1012void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
f57f2ef5 1013 const u8 *new, int bytes);
1cb3f3ae 1014int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn);
54f1585a
ZX
1015int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva);
1016void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu);
1017int kvm_mmu_load(struct kvm_vcpu *vcpu);
1018void kvm_mmu_unload(struct kvm_vcpu *vcpu);
0ba73cda 1019void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu);
54987b7a
PB
1020gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
1021 struct x86_exception *exception);
ab9ae313
AK
1022gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
1023 struct x86_exception *exception);
1024gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
1025 struct x86_exception *exception);
1026gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
1027 struct x86_exception *exception);
1028gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
1029 struct x86_exception *exception);
54f1585a
ZX
1030
1031int kvm_emulate_hypercall(struct kvm_vcpu *vcpu);
1032
dc25e89e
AP
1033int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t gva, u32 error_code,
1034 void *insn, int insn_len);
a7052897 1035void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva);
d8d173da 1036void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu);
34c16eec 1037
18552672 1038void kvm_enable_tdp(void);
5f4cb662 1039void kvm_disable_tdp(void);
18552672 1040
54987b7a
PB
1041static inline gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
1042 struct x86_exception *exception)
e459e322
XG
1043{
1044 return gpa;
1045}
1046
ec6d273d
ZX
1047static inline struct kvm_mmu_page *page_header(hpa_t shadow_page)
1048{
1049 struct page *page = pfn_to_page(shadow_page >> PAGE_SHIFT);
1050
1051 return (struct kvm_mmu_page *)page_private(page);
1052}
1053
d6e88aec 1054static inline u16 kvm_read_ldt(void)
ec6d273d
ZX
1055{
1056 u16 ldt;
1057 asm("sldt %0" : "=g"(ldt));
1058 return ldt;
1059}
1060
d6e88aec 1061static inline void kvm_load_ldt(u16 sel)
ec6d273d
ZX
1062{
1063 asm("lldt %0" : : "rm"(sel));
1064}
ec6d273d 1065
ec6d273d
ZX
1066#ifdef CONFIG_X86_64
1067static inline unsigned long read_msr(unsigned long msr)
1068{
1069 u64 value;
1070
1071 rdmsrl(msr, value);
1072 return value;
1073}
1074#endif
1075
ec6d273d
ZX
1076static inline u32 get_rdx_init_val(void)
1077{
1078 return 0x600; /* P6 family */
1079}
1080
c1a5d4f9
AK
1081static inline void kvm_inject_gp(struct kvm_vcpu *vcpu, u32 error_code)
1082{
1083 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
1084}
1085
854e8bb1
NA
1086static inline u64 get_canonical(u64 la)
1087{
1088 return ((int64_t)la << 16) >> 16;
1089}
1090
1091static inline bool is_noncanonical_address(u64 la)
1092{
1093#ifdef CONFIG_X86_64
1094 return get_canonical(la) != la;
1095#else
1096 return false;
1097#endif
1098}
1099
ec6d273d
ZX
1100#define TSS_IOPB_BASE_OFFSET 0x66
1101#define TSS_BASE_SIZE 0x68
1102#define TSS_IOPB_SIZE (65536 / 8)
1103#define TSS_REDIRECTION_SIZE (256 / 8)
7d76b4d3
JP
1104#define RMODE_TSS_SIZE \
1105 (TSS_BASE_SIZE + TSS_REDIRECTION_SIZE + TSS_IOPB_SIZE + 1)
53e0aa7b 1106
37817f29
IE
1107enum {
1108 TASK_SWITCH_CALL = 0,
1109 TASK_SWITCH_IRET = 1,
1110 TASK_SWITCH_JMP = 2,
1111 TASK_SWITCH_GATE = 3,
1112};
1113
1371d904 1114#define HF_GIF_MASK (1 << 0)
3d6368ef
AG
1115#define HF_HIF_MASK (1 << 1)
1116#define HF_VINTR_MASK (1 << 2)
95ba8273 1117#define HF_NMI_MASK (1 << 3)
44c11430 1118#define HF_IRET_MASK (1 << 4)
ec9e60b2 1119#define HF_GUEST_MASK (1 << 5) /* VCPU is in guest-mode */
f077825a
PB
1120#define HF_SMM_MASK (1 << 6)
1121#define HF_SMM_INSIDE_NMI_MASK (1 << 7)
1371d904 1122
4ecac3fd
AK
1123/*
1124 * Hardware virtualization extension instructions may fault if a
1125 * reboot turns off virtualization while processes are running.
1126 * Trap the fault and ignore the instruction if that happens.
1127 */
b7c4145b 1128asmlinkage void kvm_spurious_fault(void);
4ecac3fd 1129
5e520e62 1130#define ____kvm_handle_fault_on_reboot(insn, cleanup_insn) \
4ecac3fd 1131 "666: " insn "\n\t" \
b7c4145b 1132 "668: \n\t" \
18b13e54 1133 ".pushsection .fixup, \"ax\" \n" \
4ecac3fd 1134 "667: \n\t" \
5e520e62 1135 cleanup_insn "\n\t" \
b7c4145b
AK
1136 "cmpb $0, kvm_rebooting \n\t" \
1137 "jne 668b \n\t" \
8ceed347 1138 __ASM_SIZE(push) " $666b \n\t" \
b7c4145b 1139 "call kvm_spurious_fault \n\t" \
4ecac3fd 1140 ".popsection \n\t" \
3ee89722 1141 _ASM_EXTABLE(666b, 667b)
4ecac3fd 1142
5e520e62
AK
1143#define __kvm_handle_fault_on_reboot(insn) \
1144 ____kvm_handle_fault_on_reboot(insn, "")
1145
e930bffe
AA
1146#define KVM_ARCH_WANT_MMU_NOTIFIER
1147int kvm_unmap_hva(struct kvm *kvm, unsigned long hva);
b3ae2096 1148int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end);
57128468 1149int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end);
8ee53820 1150int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);
3da0dd43 1151void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
c7c9c56c 1152int kvm_cpu_has_injectable_intr(struct kvm_vcpu *v);
a1b37100
GN
1153int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu);
1154int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu);
0b71785d 1155int kvm_cpu_get_interrupt(struct kvm_vcpu *v);
d28bc9dd 1156void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event);
4256f43f 1157void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu);
fe71557a
TC
1158void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
1159 unsigned long address);
e930bffe 1160
18863bdd 1161void kvm_define_shared_msr(unsigned index, u32 msr);
8b3c3104 1162int kvm_set_shared_msr(unsigned index, u64 val, u64 mask);
18863bdd 1163
82b32774 1164unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu);
f92653ee
JK
1165bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip);
1166
af585b92
GN
1167void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
1168 struct kvm_async_pf *work);
1169void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
1170 struct kvm_async_pf *work);
56028d08
GN
1171void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu,
1172 struct kvm_async_pf *work);
7c90705b 1173bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu);
af585b92
GN
1174extern bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn);
1175
db8fcefa
AP
1176void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err);
1177
f5132b01
GN
1178int kvm_is_in_guest(void);
1179
1180void kvm_pmu_init(struct kvm_vcpu *vcpu);
1181void kvm_pmu_destroy(struct kvm_vcpu *vcpu);
1182void kvm_pmu_reset(struct kvm_vcpu *vcpu);
1183void kvm_pmu_cpuid_update(struct kvm_vcpu *vcpu);
1184bool kvm_pmu_msr(struct kvm_vcpu *vcpu, u32 msr);
1185int kvm_pmu_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
afd80d85 1186int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
67f4d428 1187int kvm_pmu_check_pmc(struct kvm_vcpu *vcpu, unsigned pmc);
f5132b01
GN
1188int kvm_pmu_read_pmc(struct kvm_vcpu *vcpu, unsigned pmc, u64 *data);
1189void kvm_handle_pmu_event(struct kvm_vcpu *vcpu);
1190void kvm_deliver_pmi(struct kvm_vcpu *vcpu);
1191
1965aae3 1192#endif /* _ASM_X86_KVM_HOST_H */
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