Commit | Line | Data |
---|---|---|
a656c8ef | 1 | /* |
043405e1 CO |
2 | * Kernel-based Virtual Machine driver for Linux |
3 | * | |
4 | * This header defines architecture specific interfaces, x86 version | |
5 | * | |
6 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
7 | * the COPYING file in the top-level directory. | |
8 | * | |
9 | */ | |
10 | ||
1965aae3 PA |
11 | #ifndef _ASM_X86_KVM_HOST_H |
12 | #define _ASM_X86_KVM_HOST_H | |
043405e1 | 13 | |
34c16eec ZX |
14 | #include <linux/types.h> |
15 | #include <linux/mm.h> | |
e930bffe | 16 | #include <linux/mmu_notifier.h> |
229456fc | 17 | #include <linux/tracepoint.h> |
f5f48ee1 | 18 | #include <linux/cpumask.h> |
f5132b01 | 19 | #include <linux/irq_work.h> |
34c16eec ZX |
20 | |
21 | #include <linux/kvm.h> | |
22 | #include <linux/kvm_para.h> | |
edf88417 | 23 | #include <linux/kvm_types.h> |
f5132b01 | 24 | #include <linux/perf_event.h> |
34c16eec | 25 | |
50d0a0f9 | 26 | #include <asm/pvclock-abi.h> |
e01a1b57 | 27 | #include <asm/desc.h> |
0bed3b56 | 28 | #include <asm/mtrr.h> |
9962d032 | 29 | #include <asm/msr-index.h> |
3ee89722 | 30 | #include <asm/asm.h> |
e01a1b57 | 31 | |
8c3ba334 | 32 | #define KVM_MAX_VCPUS 254 |
a59cb29e | 33 | #define KVM_SOFT_MAX_VCPUS 160 |
69a9f69b AK |
34 | #define KVM_MEMORY_SLOTS 32 |
35 | /* memory slots that does not exposed to userspace */ | |
36 | #define KVM_PRIVATE_MEM_SLOTS 4 | |
93a5cef0 XG |
37 | #define KVM_MEM_SLOTS_NUM (KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS) |
38 | ||
cef4dea0 | 39 | #define KVM_MMIO_SIZE 16 |
69a9f69b AK |
40 | |
41 | #define KVM_PIO_PAGE_OFFSET 1 | |
542472b5 | 42 | #define KVM_COALESCED_MMIO_PAGE_OFFSET 2 |
69a9f69b | 43 | |
cfec82cb JR |
44 | #define CR0_RESERVED_BITS \ |
45 | (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \ | |
46 | | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \ | |
47 | | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG)) | |
48 | ||
cd6e8f87 ZX |
49 | #define CR3_PAE_RESERVED_BITS ((X86_CR3_PWT | X86_CR3_PCD) - 1) |
50 | #define CR3_NONPAE_RESERVED_BITS ((PAGE_SIZE-1) & ~(X86_CR3_PWT | X86_CR3_PCD)) | |
7d76b4d3 JP |
51 | #define CR3_L_MODE_RESERVED_BITS (CR3_NONPAE_RESERVED_BITS | \ |
52 | 0xFFFFFF0000000000ULL) | |
cfec82cb JR |
53 | #define CR4_RESERVED_BITS \ |
54 | (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\ | |
55 | | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \ | |
56 | | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \ | |
d9c3476d | 57 | | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_RDWRGSFS \ |
cfec82cb JR |
58 | | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE)) |
59 | ||
60 | #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) | |
61 | ||
62 | ||
cd6e8f87 | 63 | |
cd6e8f87 | 64 | #define INVALID_PAGE (~(hpa_t)0) |
dd180b3e XG |
65 | #define VALID_PAGE(x) ((x) != INVALID_PAGE) |
66 | ||
cd6e8f87 ZX |
67 | #define UNMAPPED_GVA (~(gpa_t)0) |
68 | ||
ec04b260 | 69 | /* KVM Hugepage definitions for x86 */ |
04326caa | 70 | #define KVM_NR_PAGE_SIZES 3 |
82855413 JR |
71 | #define KVM_HPAGE_GFN_SHIFT(x) (((x) - 1) * 9) |
72 | #define KVM_HPAGE_SHIFT(x) (PAGE_SHIFT + KVM_HPAGE_GFN_SHIFT(x)) | |
ec04b260 JR |
73 | #define KVM_HPAGE_SIZE(x) (1UL << KVM_HPAGE_SHIFT(x)) |
74 | #define KVM_HPAGE_MASK(x) (~(KVM_HPAGE_SIZE(x) - 1)) | |
75 | #define KVM_PAGES_PER_HPAGE(x) (KVM_HPAGE_SIZE(x) / PAGE_SIZE) | |
05da4558 | 76 | |
cd6e8f87 | 77 | #define DE_VECTOR 0 |
19bd8afd | 78 | #define DB_VECTOR 1 |
77ab6db0 JK |
79 | #define BP_VECTOR 3 |
80 | #define OF_VECTOR 4 | |
81 | #define BR_VECTOR 5 | |
cd6e8f87 ZX |
82 | #define UD_VECTOR 6 |
83 | #define NM_VECTOR 7 | |
84 | #define DF_VECTOR 8 | |
85 | #define TS_VECTOR 10 | |
86 | #define NP_VECTOR 11 | |
87 | #define SS_VECTOR 12 | |
88 | #define GP_VECTOR 13 | |
89 | #define PF_VECTOR 14 | |
77ab6db0 | 90 | #define MF_VECTOR 16 |
53371b50 | 91 | #define MC_VECTOR 18 |
cd6e8f87 ZX |
92 | |
93 | #define SELECTOR_TI_MASK (1 << 2) | |
94 | #define SELECTOR_RPL_MASK 0x03 | |
95 | ||
96 | #define IOPL_SHIFT 12 | |
97 | ||
d657a98e ZX |
98 | #define KVM_PERMILLE_MMU_PAGES 20 |
99 | #define KVM_MIN_ALLOC_MMU_PAGES 64 | |
1ae0a13d DE |
100 | #define KVM_MMU_HASH_SHIFT 10 |
101 | #define KVM_NUM_MMU_PAGES (1 << KVM_MMU_HASH_SHIFT) | |
d657a98e ZX |
102 | #define KVM_MIN_FREE_MMU_PAGES 5 |
103 | #define KVM_REFILL_PAGES 25 | |
73c1160c | 104 | #define KVM_MAX_CPUID_ENTRIES 80 |
0bed3b56 | 105 | #define KVM_NR_FIXED_MTRR_REGION 88 |
9ba075a6 | 106 | #define KVM_NR_VAR_MTRR 8 |
d657a98e | 107 | |
af585b92 GN |
108 | #define ASYNC_PF_PER_VCPU 64 |
109 | ||
e935b837 | 110 | extern raw_spinlock_t kvm_lock; |
e9b11c17 ZX |
111 | extern struct list_head vm_list; |
112 | ||
d657a98e ZX |
113 | struct kvm_vcpu; |
114 | struct kvm; | |
af585b92 | 115 | struct kvm_async_pf; |
d657a98e | 116 | |
5fdbf976 | 117 | enum kvm_reg { |
2b3ccfa0 ZX |
118 | VCPU_REGS_RAX = 0, |
119 | VCPU_REGS_RCX = 1, | |
120 | VCPU_REGS_RDX = 2, | |
121 | VCPU_REGS_RBX = 3, | |
122 | VCPU_REGS_RSP = 4, | |
123 | VCPU_REGS_RBP = 5, | |
124 | VCPU_REGS_RSI = 6, | |
125 | VCPU_REGS_RDI = 7, | |
126 | #ifdef CONFIG_X86_64 | |
127 | VCPU_REGS_R8 = 8, | |
128 | VCPU_REGS_R9 = 9, | |
129 | VCPU_REGS_R10 = 10, | |
130 | VCPU_REGS_R11 = 11, | |
131 | VCPU_REGS_R12 = 12, | |
132 | VCPU_REGS_R13 = 13, | |
133 | VCPU_REGS_R14 = 14, | |
134 | VCPU_REGS_R15 = 15, | |
135 | #endif | |
5fdbf976 | 136 | VCPU_REGS_RIP, |
2b3ccfa0 ZX |
137 | NR_VCPU_REGS |
138 | }; | |
139 | ||
6de4f3ad AK |
140 | enum kvm_reg_ex { |
141 | VCPU_EXREG_PDPTR = NR_VCPU_REGS, | |
aff48baa | 142 | VCPU_EXREG_CR3, |
6de12732 | 143 | VCPU_EXREG_RFLAGS, |
69c73028 | 144 | VCPU_EXREG_CPL, |
2fb92db1 | 145 | VCPU_EXREG_SEGMENTS, |
6de4f3ad AK |
146 | }; |
147 | ||
2b3ccfa0 | 148 | enum { |
81609e3e | 149 | VCPU_SREG_ES, |
2b3ccfa0 | 150 | VCPU_SREG_CS, |
81609e3e | 151 | VCPU_SREG_SS, |
2b3ccfa0 | 152 | VCPU_SREG_DS, |
2b3ccfa0 ZX |
153 | VCPU_SREG_FS, |
154 | VCPU_SREG_GS, | |
2b3ccfa0 ZX |
155 | VCPU_SREG_TR, |
156 | VCPU_SREG_LDTR, | |
157 | }; | |
158 | ||
56e82318 | 159 | #include <asm/kvm_emulate.h> |
2b3ccfa0 | 160 | |
d657a98e ZX |
161 | #define KVM_NR_MEM_OBJS 40 |
162 | ||
42dbaa5a JK |
163 | #define KVM_NR_DB_REGS 4 |
164 | ||
165 | #define DR6_BD (1 << 13) | |
166 | #define DR6_BS (1 << 14) | |
167 | #define DR6_FIXED_1 0xffff0ff0 | |
168 | #define DR6_VOLATILE 0x0000e00f | |
169 | ||
170 | #define DR7_BP_EN_MASK 0x000000ff | |
171 | #define DR7_GE (1 << 9) | |
172 | #define DR7_GD (1 << 13) | |
173 | #define DR7_FIXED_1 0x00000400 | |
174 | #define DR7_VOLATILE 0xffff23ff | |
175 | ||
41383771 GN |
176 | /* apic attention bits */ |
177 | #define KVM_APIC_CHECK_VAPIC 0 | |
ae7a2a3f MT |
178 | /* |
179 | * The following bit is set with PV-EOI, unset on EOI. | |
180 | * We detect PV-EOI changes by guest by comparing | |
181 | * this bit with PV-EOI in guest memory. | |
182 | * See the implementation in apic_update_pv_eoi. | |
183 | */ | |
184 | #define KVM_APIC_PV_EOI_PENDING 1 | |
41383771 | 185 | |
d657a98e ZX |
186 | /* |
187 | * We don't want allocation failures within the mmu code, so we preallocate | |
188 | * enough memory for a single page fault in a cache. | |
189 | */ | |
190 | struct kvm_mmu_memory_cache { | |
191 | int nobjs; | |
192 | void *objects[KVM_NR_MEM_OBJS]; | |
193 | }; | |
194 | ||
d657a98e ZX |
195 | /* |
196 | * kvm_mmu_page_role, below, is defined as: | |
197 | * | |
198 | * bits 0:3 - total guest paging levels (2-4, or zero for real mode) | |
199 | * bits 4:7 - page table level for this shadow (1-4) | |
200 | * bits 8:9 - page table quadrant for 2-level guests | |
f6e2c02b AK |
201 | * bit 16 - direct mapping of virtual to physical mapping at gfn |
202 | * used for real mode and two-dimensional paging | |
d657a98e ZX |
203 | * bits 17:19 - common access permissions for all ptes in this shadow page |
204 | */ | |
205 | union kvm_mmu_page_role { | |
206 | unsigned word; | |
207 | struct { | |
7d76b4d3 | 208 | unsigned level:4; |
5b7e0102 | 209 | unsigned cr4_pae:1; |
7d76b4d3 JP |
210 | unsigned quadrant:2; |
211 | unsigned pad_for_nice_hex_output:6; | |
f6e2c02b | 212 | unsigned direct:1; |
7d76b4d3 | 213 | unsigned access:3; |
2e53d63a | 214 | unsigned invalid:1; |
9645bb56 | 215 | unsigned nxe:1; |
3dbe1415 | 216 | unsigned cr0_wp:1; |
411c588d | 217 | unsigned smep_andnot_wp:1; |
d657a98e ZX |
218 | }; |
219 | }; | |
220 | ||
221 | struct kvm_mmu_page { | |
222 | struct list_head link; | |
223 | struct hlist_node hash_link; | |
224 | ||
225 | /* | |
226 | * The following two entries are used to key the shadow page in the | |
227 | * hash table. | |
228 | */ | |
229 | gfn_t gfn; | |
230 | union kvm_mmu_page_role role; | |
231 | ||
232 | u64 *spt; | |
233 | /* hold the gfn of each spte inside spt */ | |
234 | gfn_t *gfns; | |
291f26bc SY |
235 | /* |
236 | * One bit set per slot which has memory | |
237 | * in this shadow page. | |
238 | */ | |
93a5cef0 | 239 | DECLARE_BITMAP(slot_bitmap, KVM_MEM_SLOTS_NUM); |
4731d4c7 | 240 | bool unsync; |
0571d366 | 241 | int root_count; /* Currently serving as active root */ |
60c8aec6 | 242 | unsigned int unsync_children; |
67052b35 | 243 | unsigned long parent_ptes; /* Reverse mapping for parent_pte */ |
0074ff63 | 244 | DECLARE_BITMAP(unsync_child_bitmap, 512); |
c2a2ac2b XG |
245 | |
246 | #ifdef CONFIG_X86_32 | |
247 | int clear_spte_count; | |
248 | #endif | |
249 | ||
a30f47cb | 250 | int write_flooding_count; |
d657a98e ZX |
251 | }; |
252 | ||
1c08364c AK |
253 | struct kvm_pio_request { |
254 | unsigned long count; | |
1c08364c AK |
255 | int in; |
256 | int port; | |
257 | int size; | |
1c08364c AK |
258 | }; |
259 | ||
d657a98e ZX |
260 | /* |
261 | * x86 supports 3 paging modes (4-level 64-bit, 3-level 64-bit, and 2-level | |
262 | * 32-bit). The kvm_mmu structure abstracts the details of the current mmu | |
263 | * mode. | |
264 | */ | |
265 | struct kvm_mmu { | |
266 | void (*new_cr3)(struct kvm_vcpu *vcpu); | |
f43addd4 | 267 | void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long root); |
5777ed34 | 268 | unsigned long (*get_cr3)(struct kvm_vcpu *vcpu); |
e4e517b4 | 269 | u64 (*get_pdptr)(struct kvm_vcpu *vcpu, int index); |
78b2c54a XG |
270 | int (*page_fault)(struct kvm_vcpu *vcpu, gva_t gva, u32 err, |
271 | bool prefault); | |
6389ee94 AK |
272 | void (*inject_page_fault)(struct kvm_vcpu *vcpu, |
273 | struct x86_exception *fault); | |
d657a98e | 274 | void (*free)(struct kvm_vcpu *vcpu); |
1871c602 | 275 | gpa_t (*gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t gva, u32 access, |
ab9ae313 | 276 | struct x86_exception *exception); |
c30a358d | 277 | gpa_t (*translate_gpa)(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access); |
e8bc217a | 278 | int (*sync_page)(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 279 | struct kvm_mmu_page *sp); |
a7052897 | 280 | void (*invlpg)(struct kvm_vcpu *vcpu, gva_t gva); |
0f53b5b1 | 281 | void (*update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
7c562522 | 282 | u64 *spte, const void *pte); |
d657a98e ZX |
283 | hpa_t root_hpa; |
284 | int root_level; | |
285 | int shadow_root_level; | |
a770f6f2 | 286 | union kvm_mmu_page_role base_role; |
c5a78f2b | 287 | bool direct_map; |
d657a98e ZX |
288 | |
289 | u64 *pae_root; | |
81407ca5 | 290 | u64 *lm_root; |
82725b20 | 291 | u64 rsvd_bits_mask[2][4]; |
ff03a073 | 292 | |
2d48a985 JR |
293 | bool nx; |
294 | ||
ff03a073 | 295 | u64 pdptrs[4]; /* pae */ |
d657a98e ZX |
296 | }; |
297 | ||
f5132b01 GN |
298 | enum pmc_type { |
299 | KVM_PMC_GP = 0, | |
300 | KVM_PMC_FIXED, | |
301 | }; | |
302 | ||
303 | struct kvm_pmc { | |
304 | enum pmc_type type; | |
305 | u8 idx; | |
306 | u64 counter; | |
307 | u64 eventsel; | |
308 | struct perf_event *perf_event; | |
309 | struct kvm_vcpu *vcpu; | |
310 | }; | |
311 | ||
312 | struct kvm_pmu { | |
313 | unsigned nr_arch_gp_counters; | |
314 | unsigned nr_arch_fixed_counters; | |
315 | unsigned available_event_types; | |
316 | u64 fixed_ctr_ctrl; | |
317 | u64 global_ctrl; | |
318 | u64 global_status; | |
319 | u64 global_ovf_ctrl; | |
320 | u64 counter_bitmask[2]; | |
321 | u64 global_ctrl_mask; | |
322 | u8 version; | |
323 | struct kvm_pmc gp_counters[X86_PMC_MAX_GENERIC]; | |
324 | struct kvm_pmc fixed_counters[X86_PMC_MAX_FIXED]; | |
325 | struct irq_work irq_work; | |
326 | u64 reprogram_pmi; | |
327 | }; | |
328 | ||
ad312c7c | 329 | struct kvm_vcpu_arch { |
5fdbf976 MT |
330 | /* |
331 | * rip and regs accesses must go through | |
332 | * kvm_{register,rip}_{read,write} functions. | |
333 | */ | |
334 | unsigned long regs[NR_VCPU_REGS]; | |
335 | u32 regs_avail; | |
336 | u32 regs_dirty; | |
34c16eec ZX |
337 | |
338 | unsigned long cr0; | |
e8467fda | 339 | unsigned long cr0_guest_owned_bits; |
34c16eec ZX |
340 | unsigned long cr2; |
341 | unsigned long cr3; | |
342 | unsigned long cr4; | |
fc78f519 | 343 | unsigned long cr4_guest_owned_bits; |
34c16eec | 344 | unsigned long cr8; |
1371d904 | 345 | u32 hflags; |
f6801dff | 346 | u64 efer; |
34c16eec ZX |
347 | u64 apic_base; |
348 | struct kvm_lapic *apic; /* kernel irqchip context */ | |
41383771 | 349 | unsigned long apic_attention; |
e1035715 | 350 | int32_t apic_arb_prio; |
34c16eec ZX |
351 | int mp_state; |
352 | int sipi_vector; | |
353 | u64 ia32_misc_enable_msr; | |
b209749f | 354 | bool tpr_access_reporting; |
34c16eec | 355 | |
14dfe855 JR |
356 | /* |
357 | * Paging state of the vcpu | |
358 | * | |
359 | * If the vcpu runs in guest mode with two level paging this still saves | |
360 | * the paging mode of the l1 guest. This context is always used to | |
361 | * handle faults. | |
362 | */ | |
34c16eec | 363 | struct kvm_mmu mmu; |
8df25a32 | 364 | |
6539e738 JR |
365 | /* |
366 | * Paging state of an L2 guest (used for nested npt) | |
367 | * | |
368 | * This context will save all necessary information to walk page tables | |
369 | * of the an L2 guest. This context is only initialized for page table | |
370 | * walking and not for faulting since we never handle l2 page faults on | |
371 | * the host. | |
372 | */ | |
373 | struct kvm_mmu nested_mmu; | |
374 | ||
14dfe855 JR |
375 | /* |
376 | * Pointer to the mmu context currently used for | |
377 | * gva_to_gpa translations. | |
378 | */ | |
379 | struct kvm_mmu *walk_mmu; | |
380 | ||
53c07b18 | 381 | struct kvm_mmu_memory_cache mmu_pte_list_desc_cache; |
34c16eec ZX |
382 | struct kvm_mmu_memory_cache mmu_page_cache; |
383 | struct kvm_mmu_memory_cache mmu_page_header_cache; | |
384 | ||
98918833 | 385 | struct fpu guest_fpu; |
2acf923e | 386 | u64 xcr0; |
34c16eec | 387 | |
34c16eec ZX |
388 | struct kvm_pio_request pio; |
389 | void *pio_data; | |
390 | ||
66fd3f7f GN |
391 | u8 event_exit_inst_len; |
392 | ||
298101da AK |
393 | struct kvm_queued_exception { |
394 | bool pending; | |
395 | bool has_error_code; | |
ce7ddec4 | 396 | bool reinject; |
298101da AK |
397 | u8 nr; |
398 | u32 error_code; | |
399 | } exception; | |
400 | ||
937a7eae AK |
401 | struct kvm_queued_interrupt { |
402 | bool pending; | |
66fd3f7f | 403 | bool soft; |
937a7eae AK |
404 | u8 nr; |
405 | } interrupt; | |
406 | ||
34c16eec ZX |
407 | int halt_request; /* real mode on Intel only */ |
408 | ||
409 | int cpuid_nent; | |
07716717 | 410 | struct kvm_cpuid_entry2 cpuid_entries[KVM_MAX_CPUID_ENTRIES]; |
34c16eec ZX |
411 | /* emulate context */ |
412 | ||
413 | struct x86_emulate_ctxt emulate_ctxt; | |
7ae441ea GN |
414 | bool emulate_regs_need_sync_to_vcpu; |
415 | bool emulate_regs_need_sync_from_vcpu; | |
18068523 GOC |
416 | |
417 | gpa_t time; | |
50d0a0f9 | 418 | struct pvclock_vcpu_time_info hv_clock; |
e48672fa | 419 | unsigned int hw_tsc_khz; |
18068523 GOC |
420 | unsigned int time_offset; |
421 | struct page *time_page; | |
c9aaa895 GC |
422 | |
423 | struct { | |
424 | u64 msr_val; | |
425 | u64 last_steal; | |
426 | u64 accum_steal; | |
427 | struct gfn_to_hva_cache stime; | |
428 | struct kvm_steal_time steal; | |
429 | } st; | |
430 | ||
1d5f066e ZA |
431 | u64 last_guest_tsc; |
432 | u64 last_kernel_ns; | |
6f526ec5 | 433 | u64 last_host_tsc; |
0dd6a6ed | 434 | u64 tsc_offset_adjustment; |
e26101b1 ZA |
435 | u64 this_tsc_nsec; |
436 | u64 this_tsc_write; | |
437 | u8 this_tsc_generation; | |
c285545f | 438 | bool tsc_catchup; |
cc578287 ZA |
439 | bool tsc_always_catchup; |
440 | s8 virtual_tsc_shift; | |
441 | u32 virtual_tsc_mult; | |
442 | u32 virtual_tsc_khz; | |
3419ffc8 | 443 | |
7460fb4a AK |
444 | atomic_t nmi_queued; /* unprocessed asynchronous NMIs */ |
445 | unsigned nmi_pending; /* NMI queued after currently running handler */ | |
446 | bool nmi_injected; /* Trying to inject an NMI this entry */ | |
9ba075a6 | 447 | |
0bed3b56 SY |
448 | struct mtrr_state_type mtrr_state; |
449 | u32 pat; | |
42dbaa5a JK |
450 | |
451 | int switch_db_regs; | |
42dbaa5a JK |
452 | unsigned long db[KVM_NR_DB_REGS]; |
453 | unsigned long dr6; | |
454 | unsigned long dr7; | |
455 | unsigned long eff_db[KVM_NR_DB_REGS]; | |
890ca9ae HY |
456 | |
457 | u64 mcg_cap; | |
458 | u64 mcg_status; | |
459 | u64 mcg_ctl; | |
460 | u64 *mce_banks; | |
94fe45da | 461 | |
bebb106a XG |
462 | /* Cache MMIO info */ |
463 | u64 mmio_gva; | |
464 | unsigned access; | |
465 | gfn_t mmio_gfn; | |
466 | ||
f5132b01 GN |
467 | struct kvm_pmu pmu; |
468 | ||
94fe45da | 469 | /* used for guest single stepping over the given code position */ |
94fe45da | 470 | unsigned long singlestep_rip; |
f92653ee | 471 | |
10388a07 GN |
472 | /* fields used by HYPER-V emulation */ |
473 | u64 hv_vapic; | |
f5f48ee1 SY |
474 | |
475 | cpumask_var_t wbinvd_dirty_mask; | |
af585b92 | 476 | |
1cb3f3ae XG |
477 | unsigned long last_retry_eip; |
478 | unsigned long last_retry_addr; | |
479 | ||
af585b92 GN |
480 | struct { |
481 | bool halted; | |
482 | gfn_t gfns[roundup_pow_of_two(ASYNC_PF_PER_VCPU)]; | |
344d9588 GN |
483 | struct gfn_to_hva_cache data; |
484 | u64 msr_val; | |
7c90705b | 485 | u32 id; |
6adba527 | 486 | bool send_user_only; |
af585b92 | 487 | } apf; |
2b036c6b BO |
488 | |
489 | /* OSVW MSRs (AMD only) */ | |
490 | struct { | |
491 | u64 length; | |
492 | u64 status; | |
493 | } osvw; | |
ae7a2a3f MT |
494 | |
495 | struct { | |
496 | u64 msr_val; | |
497 | struct gfn_to_hva_cache data; | |
498 | } pv_eoi; | |
34c16eec ZX |
499 | }; |
500 | ||
db3fe4eb TY |
501 | struct kvm_lpage_info { |
502 | unsigned long rmap_pde; | |
503 | int write_count; | |
504 | }; | |
505 | ||
506 | struct kvm_arch_memory_slot { | |
507 | struct kvm_lpage_info *lpage_info[KVM_NR_PAGE_SIZES - 1]; | |
508 | }; | |
509 | ||
fef9cce0 | 510 | struct kvm_arch { |
49d5ca26 | 511 | unsigned int n_used_mmu_pages; |
f05e70ac | 512 | unsigned int n_requested_mmu_pages; |
39de71ec | 513 | unsigned int n_max_mmu_pages; |
332b207d | 514 | unsigned int indirect_shadow_pages; |
f05e70ac ZX |
515 | struct hlist_head mmu_page_hash[KVM_NUM_MMU_PAGES]; |
516 | /* | |
517 | * Hash table of struct kvm_mmu_page. | |
518 | */ | |
519 | struct list_head active_mmu_pages; | |
4d5c5d0f | 520 | struct list_head assigned_dev_head; |
19de40a8 | 521 | struct iommu_domain *iommu_domain; |
522c68c4 | 522 | int iommu_flags; |
d7deeeb0 ZX |
523 | struct kvm_pic *vpic; |
524 | struct kvm_ioapic *vioapic; | |
7837699f | 525 | struct kvm_pit *vpit; |
cc6e462c | 526 | int vapics_in_nmi_mode; |
bfc6d222 | 527 | |
bfc6d222 ZX |
528 | unsigned int tss_addr; |
529 | struct page *apic_access_page; | |
18068523 GOC |
530 | |
531 | gpa_t wall_clock; | |
b7ebfb05 SY |
532 | |
533 | struct page *ept_identity_pagetable; | |
534 | bool ept_identity_pagetable_done; | |
b927a3ce | 535 | gpa_t ept_identity_map_addr; |
5550af4d SY |
536 | |
537 | unsigned long irq_sources_bitmap; | |
afbcf7ab | 538 | s64 kvmclock_offset; |
038f8c11 | 539 | raw_spinlock_t tsc_write_lock; |
f38e098f | 540 | u64 last_tsc_nsec; |
f38e098f | 541 | u64 last_tsc_write; |
5d3cb0f6 | 542 | u32 last_tsc_khz; |
e26101b1 ZA |
543 | u64 cur_tsc_nsec; |
544 | u64 cur_tsc_write; | |
545 | u64 cur_tsc_offset; | |
546 | u8 cur_tsc_generation; | |
ffde22ac ES |
547 | |
548 | struct kvm_xen_hvm_config xen_hvm_config; | |
55cd8e5a GN |
549 | |
550 | /* fields used by HYPER-V emulation */ | |
551 | u64 hv_guest_os_id; | |
552 | u64 hv_hypercall; | |
b034cf01 XG |
553 | |
554 | #ifdef CONFIG_KVM_MMU_AUDIT | |
555 | int audit_point; | |
556 | #endif | |
d69fb81f ZX |
557 | }; |
558 | ||
0711456c ZX |
559 | struct kvm_vm_stat { |
560 | u32 mmu_shadow_zapped; | |
561 | u32 mmu_pte_write; | |
562 | u32 mmu_pte_updated; | |
563 | u32 mmu_pde_zapped; | |
564 | u32 mmu_flooded; | |
565 | u32 mmu_recycled; | |
dfc5aa00 | 566 | u32 mmu_cache_miss; |
4731d4c7 | 567 | u32 mmu_unsync; |
0711456c | 568 | u32 remote_tlb_flush; |
05da4558 | 569 | u32 lpages; |
0711456c ZX |
570 | }; |
571 | ||
77b4c255 ZX |
572 | struct kvm_vcpu_stat { |
573 | u32 pf_fixed; | |
574 | u32 pf_guest; | |
575 | u32 tlb_flush; | |
576 | u32 invlpg; | |
577 | ||
578 | u32 exits; | |
579 | u32 io_exits; | |
580 | u32 mmio_exits; | |
581 | u32 signal_exits; | |
582 | u32 irq_window_exits; | |
f08864b4 | 583 | u32 nmi_window_exits; |
77b4c255 ZX |
584 | u32 halt_exits; |
585 | u32 halt_wakeup; | |
586 | u32 request_irq_exits; | |
587 | u32 irq_exits; | |
588 | u32 host_state_reload; | |
589 | u32 efer_reload; | |
590 | u32 fpu_reload; | |
591 | u32 insn_emulation; | |
592 | u32 insn_emulation_fail; | |
f11c3a8d | 593 | u32 hypercalls; |
fa89a817 | 594 | u32 irq_injections; |
c4abb7c9 | 595 | u32 nmi_injections; |
77b4c255 | 596 | }; |
ad312c7c | 597 | |
8a76d7f2 JR |
598 | struct x86_instruction_info; |
599 | ||
ea4a5ff8 ZX |
600 | struct kvm_x86_ops { |
601 | int (*cpu_has_kvm_support)(void); /* __init */ | |
602 | int (*disabled_by_bios)(void); /* __init */ | |
10474ae8 | 603 | int (*hardware_enable)(void *dummy); |
ea4a5ff8 ZX |
604 | void (*hardware_disable)(void *dummy); |
605 | void (*check_processor_compatibility)(void *rtn); | |
606 | int (*hardware_setup)(void); /* __init */ | |
607 | void (*hardware_unsetup)(void); /* __exit */ | |
774ead3a | 608 | bool (*cpu_has_accelerated_tpr)(void); |
0e851880 | 609 | void (*cpuid_update)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
610 | |
611 | /* Create, but do not attach this VCPU */ | |
612 | struct kvm_vcpu *(*vcpu_create)(struct kvm *kvm, unsigned id); | |
613 | void (*vcpu_free)(struct kvm_vcpu *vcpu); | |
614 | int (*vcpu_reset)(struct kvm_vcpu *vcpu); | |
615 | ||
616 | void (*prepare_guest_switch)(struct kvm_vcpu *vcpu); | |
617 | void (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu); | |
618 | void (*vcpu_put)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 | 619 | |
355be0b9 JK |
620 | void (*set_guest_debug)(struct kvm_vcpu *vcpu, |
621 | struct kvm_guest_debug *dbg); | |
ea4a5ff8 ZX |
622 | int (*get_msr)(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata); |
623 | int (*set_msr)(struct kvm_vcpu *vcpu, u32 msr_index, u64 data); | |
624 | u64 (*get_segment_base)(struct kvm_vcpu *vcpu, int seg); | |
625 | void (*get_segment)(struct kvm_vcpu *vcpu, | |
626 | struct kvm_segment *var, int seg); | |
2e4d2653 | 627 | int (*get_cpl)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
628 | void (*set_segment)(struct kvm_vcpu *vcpu, |
629 | struct kvm_segment *var, int seg); | |
630 | void (*get_cs_db_l_bits)(struct kvm_vcpu *vcpu, int *db, int *l); | |
e8467fda | 631 | void (*decache_cr0_guest_bits)(struct kvm_vcpu *vcpu); |
aff48baa | 632 | void (*decache_cr3)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
633 | void (*decache_cr4_guest_bits)(struct kvm_vcpu *vcpu); |
634 | void (*set_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0); | |
635 | void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3); | |
5e1746d6 | 636 | int (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4); |
ea4a5ff8 | 637 | void (*set_efer)(struct kvm_vcpu *vcpu, u64 efer); |
89a27f4d GN |
638 | void (*get_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); |
639 | void (*set_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); | |
640 | void (*get_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); | |
641 | void (*set_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); | |
020df079 | 642 | void (*set_dr7)(struct kvm_vcpu *vcpu, unsigned long value); |
5fdbf976 | 643 | void (*cache_reg)(struct kvm_vcpu *vcpu, enum kvm_reg reg); |
ea4a5ff8 ZX |
644 | unsigned long (*get_rflags)(struct kvm_vcpu *vcpu); |
645 | void (*set_rflags)(struct kvm_vcpu *vcpu, unsigned long rflags); | |
6b52d186 | 646 | void (*fpu_activate)(struct kvm_vcpu *vcpu); |
02daab21 | 647 | void (*fpu_deactivate)(struct kvm_vcpu *vcpu); |
ea4a5ff8 ZX |
648 | |
649 | void (*tlb_flush)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 | 650 | |
851ba692 AK |
651 | void (*run)(struct kvm_vcpu *vcpu); |
652 | int (*handle_exit)(struct kvm_vcpu *vcpu); | |
ea4a5ff8 | 653 | void (*skip_emulated_instruction)(struct kvm_vcpu *vcpu); |
2809f5d2 GC |
654 | void (*set_interrupt_shadow)(struct kvm_vcpu *vcpu, int mask); |
655 | u32 (*get_interrupt_shadow)(struct kvm_vcpu *vcpu, int mask); | |
ea4a5ff8 ZX |
656 | void (*patch_hypercall)(struct kvm_vcpu *vcpu, |
657 | unsigned char *hypercall_addr); | |
66fd3f7f | 658 | void (*set_irq)(struct kvm_vcpu *vcpu); |
95ba8273 | 659 | void (*set_nmi)(struct kvm_vcpu *vcpu); |
298101da | 660 | void (*queue_exception)(struct kvm_vcpu *vcpu, unsigned nr, |
ce7ddec4 JR |
661 | bool has_error_code, u32 error_code, |
662 | bool reinject); | |
b463a6f7 | 663 | void (*cancel_injection)(struct kvm_vcpu *vcpu); |
78646121 | 664 | int (*interrupt_allowed)(struct kvm_vcpu *vcpu); |
95ba8273 | 665 | int (*nmi_allowed)(struct kvm_vcpu *vcpu); |
3cfc3092 JK |
666 | bool (*get_nmi_mask)(struct kvm_vcpu *vcpu); |
667 | void (*set_nmi_mask)(struct kvm_vcpu *vcpu, bool masked); | |
95ba8273 GN |
668 | void (*enable_nmi_window)(struct kvm_vcpu *vcpu); |
669 | void (*enable_irq_window)(struct kvm_vcpu *vcpu); | |
670 | void (*update_cr8_intercept)(struct kvm_vcpu *vcpu, int tpr, int irr); | |
ea4a5ff8 | 671 | int (*set_tss_addr)(struct kvm *kvm, unsigned int addr); |
67253af5 | 672 | int (*get_tdp_level)(void); |
4b12f0de | 673 | u64 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio); |
17cc3935 | 674 | int (*get_lpage_level)(void); |
4e47c7a6 | 675 | bool (*rdtscp_supported)(void); |
f1e2b260 | 676 | void (*adjust_tsc_offset)(struct kvm_vcpu *vcpu, s64 adjustment, bool host); |
344f414f | 677 | |
1c97f0a0 JR |
678 | void (*set_tdp_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3); |
679 | ||
d4330ef2 JR |
680 | void (*set_supported_cpuid)(u32 func, struct kvm_cpuid_entry2 *entry); |
681 | ||
f5f48ee1 SY |
682 | bool (*has_wbinvd_exit)(void); |
683 | ||
cc578287 | 684 | void (*set_tsc_khz)(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale); |
99e3e30a ZA |
685 | void (*write_tsc_offset)(struct kvm_vcpu *vcpu, u64 offset); |
686 | ||
857e4099 | 687 | u64 (*compute_tsc_offset)(struct kvm_vcpu *vcpu, u64 target_tsc); |
d5c1785d | 688 | u64 (*read_l1_tsc)(struct kvm_vcpu *vcpu); |
857e4099 | 689 | |
586f9607 | 690 | void (*get_exit_info)(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2); |
8a76d7f2 JR |
691 | |
692 | int (*check_intercept)(struct kvm_vcpu *vcpu, | |
693 | struct x86_instruction_info *info, | |
694 | enum x86_intercept_stage stage); | |
ea4a5ff8 ZX |
695 | }; |
696 | ||
af585b92 | 697 | struct kvm_arch_async_pf { |
7c90705b | 698 | u32 token; |
af585b92 | 699 | gfn_t gfn; |
fb67e14f | 700 | unsigned long cr3; |
c4806acd | 701 | bool direct_map; |
af585b92 GN |
702 | }; |
703 | ||
97896d04 ZX |
704 | extern struct kvm_x86_ops *kvm_x86_ops; |
705 | ||
f1e2b260 MT |
706 | static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, |
707 | s64 adjustment) | |
708 | { | |
709 | kvm_x86_ops->adjust_tsc_offset(vcpu, adjustment, false); | |
710 | } | |
711 | ||
712 | static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment) | |
713 | { | |
714 | kvm_x86_ops->adjust_tsc_offset(vcpu, adjustment, true); | |
715 | } | |
716 | ||
54f1585a ZX |
717 | int kvm_mmu_module_init(void); |
718 | void kvm_mmu_module_exit(void); | |
719 | ||
720 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu); | |
721 | int kvm_mmu_create(struct kvm_vcpu *vcpu); | |
722 | int kvm_mmu_setup(struct kvm_vcpu *vcpu); | |
7b52345e | 723 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, |
4b12f0de | 724 | u64 dirty_mask, u64 nx_mask, u64 x_mask); |
54f1585a ZX |
725 | |
726 | int kvm_mmu_reset_context(struct kvm_vcpu *vcpu); | |
727 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot); | |
5dc99b23 TY |
728 | void kvm_mmu_write_protect_pt_masked(struct kvm *kvm, |
729 | struct kvm_memory_slot *slot, | |
730 | gfn_t gfn_offset, unsigned long mask); | |
54f1585a | 731 | void kvm_mmu_zap_all(struct kvm *kvm); |
3ad82a7e | 732 | unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm); |
54f1585a ZX |
733 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages); |
734 | ||
ff03a073 | 735 | int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3); |
cc4b6871 | 736 | |
3200f405 | 737 | int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa, |
9f811285 | 738 | const void *val, int bytes); |
4b12f0de | 739 | u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn); |
2f333bcb MT |
740 | |
741 | extern bool tdp_enabled; | |
9f811285 | 742 | |
a3e06bbe LJ |
743 | u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu); |
744 | ||
92a1f12d JR |
745 | /* control of guest tsc rate supported? */ |
746 | extern bool kvm_has_tsc_control; | |
747 | /* minimum supported tsc_khz for guests */ | |
748 | extern u32 kvm_min_guest_tsc_khz; | |
749 | /* maximum supported tsc_khz for guests */ | |
750 | extern u32 kvm_max_guest_tsc_khz; | |
751 | ||
54f1585a ZX |
752 | enum emulation_result { |
753 | EMULATE_DONE, /* no further processing */ | |
754 | EMULATE_DO_MMIO, /* kvm_run filled with mmio request */ | |
755 | EMULATE_FAIL, /* can't emulate this instruction */ | |
756 | }; | |
757 | ||
571008da SY |
758 | #define EMULTYPE_NO_DECODE (1 << 0) |
759 | #define EMULTYPE_TRAP_UD (1 << 1) | |
ba8afb6b | 760 | #define EMULTYPE_SKIP (1 << 2) |
1cb3f3ae | 761 | #define EMULTYPE_RETRY (1 << 3) |
dc25e89e AP |
762 | int x86_emulate_instruction(struct kvm_vcpu *vcpu, unsigned long cr2, |
763 | int emulation_type, void *insn, int insn_len); | |
51d8b661 AP |
764 | |
765 | static inline int emulate_instruction(struct kvm_vcpu *vcpu, | |
766 | int emulation_type) | |
767 | { | |
dc25e89e | 768 | return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0); |
51d8b661 AP |
769 | } |
770 | ||
f2b4b7dd | 771 | void kvm_enable_efer_bits(u64); |
54f1585a ZX |
772 | int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *data); |
773 | int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data); | |
774 | ||
775 | struct x86_emulate_ctxt; | |
776 | ||
cf8f70bf | 777 | int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port); |
54f1585a ZX |
778 | void kvm_emulate_cpuid(struct kvm_vcpu *vcpu); |
779 | int kvm_emulate_halt(struct kvm_vcpu *vcpu); | |
f5f48ee1 | 780 | int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu); |
54f1585a | 781 | |
3e6e0aab | 782 | void kvm_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg); |
c697518a | 783 | int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg); |
3e6e0aab | 784 | |
7f3d35fd KW |
785 | int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index, |
786 | int reason, bool has_error_code, u32 error_code); | |
37817f29 | 787 | |
49a9b07e | 788 | int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); |
2390218b | 789 | int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3); |
a83b29c6 | 790 | int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); |
eea1cff9 | 791 | int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8); |
020df079 GN |
792 | int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val); |
793 | int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val); | |
2d3ad1f4 AK |
794 | unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu); |
795 | void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw); | |
54f1585a | 796 | void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l); |
2acf923e | 797 | int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr); |
54f1585a ZX |
798 | |
799 | int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata); | |
800 | int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data); | |
801 | ||
91586a3b JK |
802 | unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu); |
803 | void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags); | |
022cd0e8 | 804 | bool kvm_rdpmc(struct kvm_vcpu *vcpu); |
91586a3b | 805 | |
298101da AK |
806 | void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr); |
807 | void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); | |
ce7ddec4 JR |
808 | void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr); |
809 | void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code); | |
6389ee94 | 810 | void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault); |
ec92fe44 JR |
811 | int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
812 | gfn_t gfn, void *data, int offset, int len, | |
813 | u32 access); | |
6389ee94 | 814 | void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault); |
0a79b009 | 815 | bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl); |
298101da | 816 | |
4925663a | 817 | int kvm_pic_set_irq(void *opaque, int irq, int level); |
3de42dc0 | 818 | |
3419ffc8 SY |
819 | void kvm_inject_nmi(struct kvm_vcpu *vcpu); |
820 | ||
10ab25cd | 821 | int fx_init(struct kvm_vcpu *vcpu); |
54f1585a | 822 | |
d835dfec | 823 | void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu); |
54f1585a | 824 | void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
f57f2ef5 | 825 | const u8 *new, int bytes); |
1cb3f3ae | 826 | int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn); |
54f1585a ZX |
827 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva); |
828 | void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu); | |
829 | int kvm_mmu_load(struct kvm_vcpu *vcpu); | |
830 | void kvm_mmu_unload(struct kvm_vcpu *vcpu); | |
0ba73cda | 831 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu); |
e459e322 | 832 | gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access); |
ab9ae313 AK |
833 | gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, |
834 | struct x86_exception *exception); | |
835 | gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, | |
836 | struct x86_exception *exception); | |
837 | gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, | |
838 | struct x86_exception *exception); | |
839 | gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, | |
840 | struct x86_exception *exception); | |
54f1585a ZX |
841 | |
842 | int kvm_emulate_hypercall(struct kvm_vcpu *vcpu); | |
843 | ||
dc25e89e AP |
844 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t gva, u32 error_code, |
845 | void *insn, int insn_len); | |
a7052897 | 846 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva); |
34c16eec | 847 | |
18552672 | 848 | void kvm_enable_tdp(void); |
5f4cb662 | 849 | void kvm_disable_tdp(void); |
18552672 | 850 | |
de7d789a | 851 | int complete_pio(struct kvm_vcpu *vcpu); |
f850e2e6 | 852 | bool kvm_check_iopl(struct kvm_vcpu *vcpu); |
ec6d273d | 853 | |
e459e322 XG |
854 | static inline gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access) |
855 | { | |
856 | return gpa; | |
857 | } | |
858 | ||
ec6d273d ZX |
859 | static inline struct kvm_mmu_page *page_header(hpa_t shadow_page) |
860 | { | |
861 | struct page *page = pfn_to_page(shadow_page >> PAGE_SHIFT); | |
862 | ||
863 | return (struct kvm_mmu_page *)page_private(page); | |
864 | } | |
865 | ||
d6e88aec | 866 | static inline u16 kvm_read_ldt(void) |
ec6d273d ZX |
867 | { |
868 | u16 ldt; | |
869 | asm("sldt %0" : "=g"(ldt)); | |
870 | return ldt; | |
871 | } | |
872 | ||
d6e88aec | 873 | static inline void kvm_load_ldt(u16 sel) |
ec6d273d ZX |
874 | { |
875 | asm("lldt %0" : : "rm"(sel)); | |
876 | } | |
ec6d273d | 877 | |
ec6d273d ZX |
878 | #ifdef CONFIG_X86_64 |
879 | static inline unsigned long read_msr(unsigned long msr) | |
880 | { | |
881 | u64 value; | |
882 | ||
883 | rdmsrl(msr, value); | |
884 | return value; | |
885 | } | |
886 | #endif | |
887 | ||
ec6d273d ZX |
888 | static inline u32 get_rdx_init_val(void) |
889 | { | |
890 | return 0x600; /* P6 family */ | |
891 | } | |
892 | ||
c1a5d4f9 AK |
893 | static inline void kvm_inject_gp(struct kvm_vcpu *vcpu, u32 error_code) |
894 | { | |
895 | kvm_queue_exception_e(vcpu, GP_VECTOR, error_code); | |
896 | } | |
897 | ||
ec6d273d ZX |
898 | #define TSS_IOPB_BASE_OFFSET 0x66 |
899 | #define TSS_BASE_SIZE 0x68 | |
900 | #define TSS_IOPB_SIZE (65536 / 8) | |
901 | #define TSS_REDIRECTION_SIZE (256 / 8) | |
7d76b4d3 JP |
902 | #define RMODE_TSS_SIZE \ |
903 | (TSS_BASE_SIZE + TSS_REDIRECTION_SIZE + TSS_IOPB_SIZE + 1) | |
53e0aa7b | 904 | |
37817f29 IE |
905 | enum { |
906 | TASK_SWITCH_CALL = 0, | |
907 | TASK_SWITCH_IRET = 1, | |
908 | TASK_SWITCH_JMP = 2, | |
909 | TASK_SWITCH_GATE = 3, | |
910 | }; | |
911 | ||
1371d904 | 912 | #define HF_GIF_MASK (1 << 0) |
3d6368ef AG |
913 | #define HF_HIF_MASK (1 << 1) |
914 | #define HF_VINTR_MASK (1 << 2) | |
95ba8273 | 915 | #define HF_NMI_MASK (1 << 3) |
44c11430 | 916 | #define HF_IRET_MASK (1 << 4) |
ec9e60b2 | 917 | #define HF_GUEST_MASK (1 << 5) /* VCPU is in guest-mode */ |
1371d904 | 918 | |
4ecac3fd AK |
919 | /* |
920 | * Hardware virtualization extension instructions may fault if a | |
921 | * reboot turns off virtualization while processes are running. | |
922 | * Trap the fault and ignore the instruction if that happens. | |
923 | */ | |
b7c4145b AK |
924 | asmlinkage void kvm_spurious_fault(void); |
925 | extern bool kvm_rebooting; | |
4ecac3fd | 926 | |
5e520e62 | 927 | #define ____kvm_handle_fault_on_reboot(insn, cleanup_insn) \ |
4ecac3fd | 928 | "666: " insn "\n\t" \ |
b7c4145b | 929 | "668: \n\t" \ |
18b13e54 | 930 | ".pushsection .fixup, \"ax\" \n" \ |
4ecac3fd | 931 | "667: \n\t" \ |
5e520e62 | 932 | cleanup_insn "\n\t" \ |
b7c4145b AK |
933 | "cmpb $0, kvm_rebooting \n\t" \ |
934 | "jne 668b \n\t" \ | |
8ceed347 | 935 | __ASM_SIZE(push) " $666b \n\t" \ |
b7c4145b | 936 | "call kvm_spurious_fault \n\t" \ |
4ecac3fd | 937 | ".popsection \n\t" \ |
3ee89722 | 938 | _ASM_EXTABLE(666b, 667b) |
4ecac3fd | 939 | |
5e520e62 AK |
940 | #define __kvm_handle_fault_on_reboot(insn) \ |
941 | ____kvm_handle_fault_on_reboot(insn, "") | |
942 | ||
e930bffe AA |
943 | #define KVM_ARCH_WANT_MMU_NOTIFIER |
944 | int kvm_unmap_hva(struct kvm *kvm, unsigned long hva); | |
945 | int kvm_age_hva(struct kvm *kvm, unsigned long hva); | |
8ee53820 | 946 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva); |
3da0dd43 | 947 | void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte); |
82725b20 | 948 | int cpuid_maxphyaddr(struct kvm_vcpu *vcpu); |
a1b37100 GN |
949 | int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu); |
950 | int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu); | |
0b71785d | 951 | int kvm_cpu_get_interrupt(struct kvm_vcpu *v); |
e930bffe | 952 | |
18863bdd | 953 | void kvm_define_shared_msr(unsigned index, u32 msr); |
d5696725 | 954 | void kvm_set_shared_msr(unsigned index, u64 val, u64 mask); |
18863bdd | 955 | |
f92653ee JK |
956 | bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip); |
957 | ||
af585b92 GN |
958 | void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu, |
959 | struct kvm_async_pf *work); | |
960 | void kvm_arch_async_page_present(struct kvm_vcpu *vcpu, | |
961 | struct kvm_async_pf *work); | |
56028d08 GN |
962 | void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, |
963 | struct kvm_async_pf *work); | |
7c90705b | 964 | bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu); |
af585b92 GN |
965 | extern bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn); |
966 | ||
db8fcefa AP |
967 | void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err); |
968 | ||
f5132b01 GN |
969 | int kvm_is_in_guest(void); |
970 | ||
971 | void kvm_pmu_init(struct kvm_vcpu *vcpu); | |
972 | void kvm_pmu_destroy(struct kvm_vcpu *vcpu); | |
973 | void kvm_pmu_reset(struct kvm_vcpu *vcpu); | |
974 | void kvm_pmu_cpuid_update(struct kvm_vcpu *vcpu); | |
975 | bool kvm_pmu_msr(struct kvm_vcpu *vcpu, u32 msr); | |
976 | int kvm_pmu_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *data); | |
977 | int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, u32 msr, u64 data); | |
978 | int kvm_pmu_read_pmc(struct kvm_vcpu *vcpu, unsigned pmc, u64 *data); | |
979 | void kvm_handle_pmu_event(struct kvm_vcpu *vcpu); | |
980 | void kvm_deliver_pmi(struct kvm_vcpu *vcpu); | |
981 | ||
1965aae3 | 982 | #endif /* _ASM_X86_KVM_HOST_H */ |