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1965aae3 PA |
1 | #ifndef _ASM_X86_MCE_H |
2 | #define _ASM_X86_MCE_H | |
e2f43029 | 3 | |
999b697b | 4 | #include <linux/types.h> |
e2f43029 | 5 | #include <asm/ioctls.h> |
e2f43029 TG |
6 | |
7 | /* | |
8 | * Machine Check support for x86 | |
9 | */ | |
10 | ||
2b90e77e | 11 | /* MCG_CAP register defines */ |
01c6680a | 12 | #define MCG_BANKCNT_MASK 0xff /* Number of Banks */ |
e4876839 | 13 | #define MCG_CTL_P (1ULL<<8) /* MCG_CTL register available */ |
01c6680a TG |
14 | #define MCG_EXT_P (1ULL<<9) /* Extended registers available */ |
15 | #define MCG_CMCI_P (1ULL<<10) /* CMCI supported */ | |
16 | #define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */ | |
17 | #define MCG_EXT_CNT_SHIFT 16 | |
18 | #define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT) | |
ed7290d0 | 19 | #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ |
e2f43029 | 20 | |
2b90e77e | 21 | /* MCG_STATUS register defines */ |
06b851d9 IM |
22 | #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ |
23 | #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ | |
24 | #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ | |
e2f43029 | 25 | |
2b90e77e | 26 | /* MCi_STATUS register defines */ |
06b851d9 IM |
27 | #define MCI_STATUS_VAL (1ULL<<63) /* valid error */ |
28 | #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ | |
29 | #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ | |
30 | #define MCI_STATUS_EN (1ULL<<60) /* error enabled */ | |
31 | #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ | |
32 | #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ | |
33 | #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ | |
ed7290d0 AK |
34 | #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ |
35 | #define MCI_STATUS_AR (1ULL<<55) /* Action required */ | |
736edce5 TL |
36 | #define MCACOD 0xffff /* MCA Error Code */ |
37 | ||
38 | /* Architecturally defined codes from SDM Vol. 3B Chapter 15 */ | |
39 | #define MCACOD_SCRUB 0x00C0 /* 0xC0-0xCF Memory Scrubbing */ | |
40 | #define MCACOD_SCRUBMSK 0xfff0 | |
41 | #define MCACOD_L3WB 0x017A /* L3 Explicit Writeback */ | |
42 | #define MCACOD_DATA 0x0134 /* Data Load */ | |
43 | #define MCACOD_INSTR 0x0150 /* Instruction Fetch */ | |
ed7290d0 | 44 | |
2b90e77e HS |
45 | /* MCi_MISC register defines */ |
46 | #define MCI_MISC_ADDR_LSB(m) ((m) & 0x3f) | |
47 | #define MCI_MISC_ADDR_MODE(m) (((m) >> 6) & 7) | |
48 | #define MCI_MISC_ADDR_SEGOFF 0 /* segment offset */ | |
49 | #define MCI_MISC_ADDR_LINEAR 1 /* linear address */ | |
50 | #define MCI_MISC_ADDR_PHYS 2 /* physical address */ | |
51 | #define MCI_MISC_ADDR_MEM 3 /* memory address */ | |
52 | #define MCI_MISC_ADDR_GENERIC 7 /* generic */ | |
e2f43029 | 53 | |
1f9a0bd4 HY |
54 | /* CTL2 register defines */ |
55 | #define MCI_CTL2_CMCI_EN (1ULL << 30) | |
3c417588 | 56 | #define MCI_CTL2_CMCI_THRESHOLD_MASK 0x7fffULL |
1f9a0bd4 | 57 | |
5b7e88ed HY |
58 | #define MCJ_CTX_MASK 3 |
59 | #define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK) | |
60 | #define MCJ_CTX_RANDOM 0 /* inject context: random */ | |
2c29d9dd CG |
61 | #define MCJ_CTX_PROCESS 0x1 /* inject context: process */ |
62 | #define MCJ_CTX_IRQ 0x2 /* inject context: IRQ */ | |
63 | #define MCJ_NMI_BROADCAST 0x4 /* do NMI broadcasting */ | |
64 | #define MCJ_EXCEPTION 0x8 /* raise as exception */ | |
65 | #define MCJ_IRQ_BRAODCAST 0x10 /* do IRQ broadcasting */ | |
5b7e88ed | 66 | |
e2f43029 TG |
67 | /* Fields are zero when not available */ |
68 | struct mce { | |
69 | __u64 status; | |
70 | __u64 misc; | |
71 | __u64 addr; | |
72 | __u64 mcgstatus; | |
65ea5b03 | 73 | __u64 ip; |
e2f43029 | 74 | __u64 tsc; /* cpu time stamp counter */ |
8ee08347 AK |
75 | __u64 time; /* wall time_t when error was detected */ |
76 | __u8 cpuvendor; /* cpu vendor as encoded in system.h */ | |
5b7e88ed HY |
77 | __u8 inject_flags; /* software inject flags */ |
78 | __u16 pad; | |
8ee08347 | 79 | __u32 cpuid; /* CPUID 1 EAX */ |
e2f43029 TG |
80 | __u8 cs; /* code segment */ |
81 | __u8 bank; /* machine check bank */ | |
d620c67f | 82 | __u8 cpu; /* cpu number; obsolete; use extcpu now */ |
e2f43029 | 83 | __u8 finished; /* entry is valid */ |
d620c67f | 84 | __u32 extcpu; /* linux cpu number that detected the error */ |
8ee08347 AK |
85 | __u32 socketid; /* CPU socket ID */ |
86 | __u32 apicid; /* CPU initial apic ID */ | |
87 | __u64 mcgcap; /* MCGCAP MSR: machine check capabilities of CPU */ | |
e2f43029 TG |
88 | }; |
89 | ||
90 | /* | |
91 | * This structure contains all data related to the MCE log. Also | |
92 | * carries a signature to make it easier to find from external | |
93 | * debugging tools. Each entry is only valid when its finished flag | |
94 | * is set. | |
95 | */ | |
96 | ||
97 | #define MCE_LOG_LEN 32 | |
98 | ||
99 | struct mce_log { | |
100 | char signature[12]; /* "MACHINECHECK" */ | |
101 | unsigned len; /* = MCE_LOG_LEN */ | |
102 | unsigned next; | |
103 | unsigned flags; | |
f6fb0ac0 | 104 | unsigned recordlen; /* length of struct mce */ |
e2f43029 TG |
105 | struct mce entry[MCE_LOG_LEN]; |
106 | }; | |
107 | ||
108 | #define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */ | |
109 | ||
110 | #define MCE_LOG_SIGNATURE "MACHINECHECK" | |
111 | ||
112 | #define MCE_GET_RECORD_LEN _IOR('M', 1, int) | |
113 | #define MCE_GET_LOG_LEN _IOR('M', 2, int) | |
114 | #define MCE_GETCLEAR_FLAGS _IOR('M', 3, int) | |
115 | ||
116 | /* Software defined banks */ | |
117 | #define MCE_EXTENDED_BANK 128 | |
118 | #define MCE_THERMAL_BANK MCE_EXTENDED_BANK + 0 | |
57639bed | 119 | #define K8_MCE_THRESHOLD_BASE (MCE_EXTENDED_BANK + 1) |
fb253195 | 120 | |
e2f43029 | 121 | #ifdef __KERNEL__ |
d203f0b8 BP |
122 | |
123 | struct mca_config { | |
124 | bool dont_log_ce; | |
7af19e4a BP |
125 | bool cmci_disabled; |
126 | bool ignore_ce; | |
1462594b BP |
127 | bool disabled; |
128 | bool ser; | |
129 | bool bios_cmci_threshold; | |
d203f0b8 | 130 | u8 banks; |
84c2559d | 131 | s8 bootlog; |
d203f0b8 | 132 | int tolerant; |
84c2559d | 133 | int monarch_timeout; |
7af19e4a | 134 | int panic_timeout; |
84c2559d | 135 | u32 rip_msr; |
d203f0b8 BP |
136 | }; |
137 | ||
7af19e4a | 138 | extern struct mca_config mca_cfg; |
3653ada5 BP |
139 | extern void mce_register_decode_chain(struct notifier_block *nb); |
140 | extern void mce_unregister_decode_chain(struct notifier_block *nb); | |
df39a2e4 | 141 | |
9e55e44e HS |
142 | #include <linux/percpu.h> |
143 | #include <linux/init.h> | |
60063497 | 144 | #include <linux/atomic.h> |
9e55e44e | 145 | |
c6978369 | 146 | extern int mce_p5_enabled; |
e2f43029 | 147 | |
58995d2d | 148 | #ifdef CONFIG_X86_MCE |
a2202aa2 | 149 | int mcheck_init(void); |
5e09954a | 150 | void mcheck_cpu_init(struct cpuinfo_x86 *c); |
58995d2d | 151 | #else |
a2202aa2 | 152 | static inline int mcheck_init(void) { return 0; } |
5e09954a | 153 | static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {} |
58995d2d HS |
154 | #endif |
155 | ||
9e55e44e HS |
156 | #ifdef CONFIG_X86_ANCIENT_MCE |
157 | void intel_p5_mcheck_init(struct cpuinfo_x86 *c); | |
158 | void winchip_mcheck_init(struct cpuinfo_x86 *c); | |
c6978369 | 159 | static inline void enable_p5_mce(void) { mce_p5_enabled = 1; } |
9e55e44e HS |
160 | #else |
161 | static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {} | |
162 | static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {} | |
c6978369 | 163 | static inline void enable_p5_mce(void) {} |
9e55e44e HS |
164 | #endif |
165 | ||
b5f2fa4e | 166 | void mce_setup(struct mce *m); |
e2f43029 | 167 | void mce_log(struct mce *m); |
d6126ef5 | 168 | DECLARE_PER_CPU(struct device *, mce_device); |
e2f43029 | 169 | |
41fdff32 | 170 | /* |
3ccdccfa AK |
171 | * Maximum banks number. |
172 | * This is the limit of the current register layout on | |
173 | * Intel CPUs. | |
41fdff32 | 174 | */ |
3ccdccfa | 175 | #define MAX_NR_BANKS 32 |
41fdff32 | 176 | |
e2f43029 TG |
177 | #ifdef CONFIG_X86_MCE_INTEL |
178 | void mce_intel_feature_init(struct cpuinfo_x86 *c); | |
88ccbedd AK |
179 | void cmci_clear(void); |
180 | void cmci_reenable(void); | |
181 | void cmci_rediscover(int dying); | |
182 | void cmci_recheck(void); | |
e2f43029 TG |
183 | #else |
184 | static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { } | |
88ccbedd AK |
185 | static inline void cmci_clear(void) {} |
186 | static inline void cmci_reenable(void) {} | |
187 | static inline void cmci_rediscover(int dying) {} | |
188 | static inline void cmci_recheck(void) {} | |
e2f43029 TG |
189 | #endif |
190 | ||
191 | #ifdef CONFIG_X86_MCE_AMD | |
192 | void mce_amd_feature_init(struct cpuinfo_x86 *c); | |
193 | #else | |
194 | static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { } | |
195 | #endif | |
196 | ||
38736072 | 197 | int mce_available(struct cpuinfo_x86 *c); |
88ccbedd | 198 | |
01ca79f1 | 199 | DECLARE_PER_CPU(unsigned, mce_exception_count); |
ca84f696 | 200 | DECLARE_PER_CPU(unsigned, mce_poll_count); |
01ca79f1 | 201 | |
e2f43029 TG |
202 | extern atomic_t mce_entry; |
203 | ||
ee031c31 AK |
204 | typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS); |
205 | DECLARE_PER_CPU(mce_banks_t, mce_poll_banks); | |
206 | ||
b79109c3 AK |
207 | enum mcp_flags { |
208 | MCP_TIMESTAMP = (1 << 0), /* log time stamp */ | |
209 | MCP_UC = (1 << 1), /* log uncorrected errors */ | |
5679af4c | 210 | MCP_DONTLOG = (1 << 2), /* only clear, don't log */ |
b79109c3 | 211 | }; |
38736072 | 212 | void machine_check_poll(enum mcp_flags flags, mce_banks_t *b); |
b79109c3 | 213 | |
9ff36ee9 | 214 | int mce_notify_irq(void); |
9b1beaf2 | 215 | void mce_notify_process(void); |
e2f43029 | 216 | |
ea149b36 | 217 | DECLARE_PER_CPU(struct mce, injectm); |
66f5ddf3 LT |
218 | |
219 | extern void register_mce_write_callback(ssize_t (*)(struct file *filp, | |
220 | const char __user *ubuf, | |
221 | size_t usize, loff_t *off)); | |
ea149b36 | 222 | |
58995d2d HS |
223 | /* |
224 | * Exception handler | |
225 | */ | |
226 | ||
227 | /* Call the installed machine check handler for this CPU setup. */ | |
228 | extern void (*machine_check_vector)(struct pt_regs *, long error_code); | |
229 | void do_machine_check(struct pt_regs *, long); | |
230 | ||
231 | /* | |
232 | * Threshold handler | |
233 | */ | |
e2f43029 | 234 | |
b2762686 | 235 | extern void (*mce_threshold_vector)(void); |
58995d2d | 236 | extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); |
b2762686 | 237 | |
e8ce2c5e HS |
238 | /* |
239 | * Thermal handler | |
240 | */ | |
241 | ||
e8ce2c5e HS |
242 | void intel_init_thermal(struct cpuinfo_x86 *c); |
243 | ||
e8ce2c5e | 244 | void mce_log_therm_throt_event(__u64 status); |
a2202aa2 | 245 | |
9e76a97e D |
246 | /* Interrupt Handler for core thermal thresholds */ |
247 | extern int (*platform_thermal_notify)(__u64 msr_val); | |
248 | ||
a2202aa2 YW |
249 | #ifdef CONFIG_X86_THERMAL_VECTOR |
250 | extern void mcheck_intel_therm_init(void); | |
251 | #else | |
252 | static inline void mcheck_intel_therm_init(void) { } | |
253 | #endif | |
254 | ||
d334a491 HY |
255 | /* |
256 | * Used by APEI to report memory error via /dev/mcelog | |
257 | */ | |
258 | ||
259 | struct cper_sec_mem_err; | |
260 | extern void apei_mce_report_mem_error(int corrected, | |
261 | struct cper_sec_mem_err *mem_err); | |
262 | ||
e2f43029 | 263 | #endif /* __KERNEL__ */ |
1965aae3 | 264 | #endif /* _ASM_X86_MCE_H */ |