[deliverable/linux.git] / arch / x86 / include / asm / mce.h

#ifndef _ASM_X86_MCE_H
#define _ASM_X86_MCE_H

#include <linux/types.h>
#include <asm/ioctls.h>

/*
 * Machine Check support for x86
 */

/* MCG_CAP register defines */
#define MCG_BANKCNT_MASK	0xff         /* Number of Banks */
#define MCG_CTL_P		(1ULL<<8)    /* MCG_CTL register available */
#define MCG_EXT_P		(1ULL<<9)    /* Extended registers available */
#define MCG_CMCI_P		(1ULL<<10)   /* CMCI supported */
#define MCG_EXT_CNT_MASK	0xff0000     /* Number of Extended registers */
#define MCG_EXT_CNT_SHIFT	16
#define MCG_EXT_CNT(c)		(((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
#define MCG_SER_P	 	(1ULL<<24)   /* MCA recovery/new status bits */

/* MCG_STATUS register defines */
#define MCG_STATUS_RIPV  (1ULL<<0)   /* restart ip valid */
#define MCG_STATUS_EIPV  (1ULL<<1)   /* ip points to correct instruction */
#define MCG_STATUS_MCIP  (1ULL<<2)   /* machine check in progress */

/* MCi_STATUS register defines */
#define MCI_STATUS_VAL   (1ULL<<63)  /* valid error */
#define MCI_STATUS_OVER  (1ULL<<62)  /* previous errors lost */
#define MCI_STATUS_UC    (1ULL<<61)  /* uncorrected error */
#define MCI_STATUS_EN    (1ULL<<60)  /* error enabled */
#define MCI_STATUS_MISCV (1ULL<<59)  /* misc error reg. valid */
#define MCI_STATUS_ADDRV (1ULL<<58)  /* addr reg. valid */
#define MCI_STATUS_PCC   (1ULL<<57)  /* processor context corrupt */
#define MCI_STATUS_S	 (1ULL<<56)  /* Signaled machine check */
#define MCI_STATUS_AR	 (1ULL<<55)  /* Action required */

/* MCi_MISC register defines */
#define MCI_MISC_ADDR_LSB(m)	((m) & 0x3f)
#define MCI_MISC_ADDR_MODE(m)	(((m) >> 6) & 7)
#define  MCI_MISC_ADDR_SEGOFF	0	/* segment offset */
#define  MCI_MISC_ADDR_LINEAR	1	/* linear address */
#define  MCI_MISC_ADDR_PHYS	2	/* physical address */
#define  MCI_MISC_ADDR_MEM	3	/* memory address */
#define  MCI_MISC_ADDR_GENERIC	7	/* generic */

/* CTL2 register defines */
#define MCI_CTL2_CMCI_EN		(1ULL << 30)
#define MCI_CTL2_CMCI_THRESHOLD_MASK	0x7fffULL

#define MCJ_CTX_MASK		3
#define MCJ_CTX(flags)		((flags) & MCJ_CTX_MASK)
#define MCJ_CTX_RANDOM		0    /* inject context: random */
#define MCJ_CTX_PROCESS		0x1  /* inject context: process */
#define MCJ_CTX_IRQ		0x2  /* inject context: IRQ */
#define MCJ_NMI_BROADCAST	0x4  /* do NMI broadcasting */
#define MCJ_EXCEPTION		0x8  /* raise as exception */
#define MCJ_IRQ_BRAODCAST	0x10 /* do IRQ broadcasting */

/* Fields are zero when not available */
struct mce {
	__u64 status;
	__u64 misc;
	__u64 addr;
	__u64 mcgstatus;
	__u64 ip;
	__u64 tsc;	/* cpu time stamp counter */
	__u64 time;	/* wall time_t when error was detected */
	__u8  cpuvendor;	/* cpu vendor as encoded in system.h */
	__u8  inject_flags;	/* software inject flags */
	__u16  pad;
	__u32 cpuid;	/* CPUID 1 EAX */
	__u8  cs;		/* code segment */
	__u8  bank;	/* machine check bank */
	__u8  cpu;	/* cpu number; obsolete; use extcpu now */
	__u8  finished;   /* entry is valid */
	__u32 extcpu;	/* linux cpu number that detected the error */
	__u32 socketid;	/* CPU socket ID */
	__u32 apicid;	/* CPU initial apic ID */
	__u64 mcgcap;	/* MCGCAP MSR: machine check capabilities of CPU */
};

/*
 * This structure contains all data related to the MCE log.  Also
 * carries a signature to make it easier to find from external
 * debugging tools.  Each entry is only valid when its finished flag
 * is set.
 */

#define MCE_LOG_LEN 32

struct mce_log {
	char signature[12]; /* "MACHINECHECK" */
	unsigned len;	    /* = MCE_LOG_LEN */
	unsigned next;
	unsigned flags;
	unsigned recordlen;	/* length of struct mce */
	struct mce entry[MCE_LOG_LEN];
};

#define MCE_OVERFLOW 0		/* bit 0 in flags means overflow */

#define MCE_LOG_SIGNATURE	"MACHINECHECK"

#define MCE_GET_RECORD_LEN   _IOR('M', 1, int)
#define MCE_GET_LOG_LEN      _IOR('M', 2, int)
#define MCE_GETCLEAR_FLAGS   _IOR('M', 3, int)

/* Software defined banks */
#define MCE_EXTENDED_BANK	128
#define MCE_THERMAL_BANK	MCE_EXTENDED_BANK + 0

#define K8_MCE_THRESHOLD_BASE      (MCE_EXTENDED_BANK + 1)      /* MCE_AMD */
#define K8_MCE_THRESHOLD_BANK_0    (MCE_THRESHOLD_BASE + 0 * 9)
#define K8_MCE_THRESHOLD_BANK_1    (MCE_THRESHOLD_BASE + 1 * 9)
#define K8_MCE_THRESHOLD_BANK_2    (MCE_THRESHOLD_BASE + 2 * 9)
#define K8_MCE_THRESHOLD_BANK_3    (MCE_THRESHOLD_BASE + 3 * 9)
#define K8_MCE_THRESHOLD_BANK_4    (MCE_THRESHOLD_BASE + 4 * 9)
#define K8_MCE_THRESHOLD_BANK_5    (MCE_THRESHOLD_BASE + 5 * 9)
#define K8_MCE_THRESHOLD_DRAM_ECC  (MCE_THRESHOLD_BANK_4 + 0)


#ifdef __KERNEL__

extern void mce_register_decode_chain(struct notifier_block *nb);
extern void mce_unregister_decode_chain(struct notifier_block *nb);

#include <linux/percpu.h>
#include <linux/init.h>
#include <linux/atomic.h>

extern int mce_disabled;
extern int mce_p5_enabled;

#ifdef CONFIG_X86_MCE
int mcheck_init(void);
void mcheck_cpu_init(struct cpuinfo_x86 *c);
#else
static inline int mcheck_init(void) { return 0; }
static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {}
#endif

#ifdef CONFIG_X86_ANCIENT_MCE
void intel_p5_mcheck_init(struct cpuinfo_x86 *c);
void winchip_mcheck_init(struct cpuinfo_x86 *c);
static inline void enable_p5_mce(void) { mce_p5_enabled = 1; }
#else
static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {}
static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {}
static inline void enable_p5_mce(void) {}
#endif

void mce_setup(struct mce *m);
void mce_log(struct mce *m);
extern struct device *mce_device[CONFIG_NR_CPUS];

/*
 * Maximum banks number.
 * This is the limit of the current register layout on
 * Intel CPUs.
 */
#define MAX_NR_BANKS 32

#ifdef CONFIG_X86_MCE_INTEL
extern int mce_cmci_disabled;
extern int mce_ignore_ce;
void mce_intel_feature_init(struct cpuinfo_x86 *c);
void cmci_clear(void);
void cmci_reenable(void);
void cmci_rediscover(int dying);
void cmci_recheck(void);
#else
static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
static inline void cmci_clear(void) {}
static inline void cmci_reenable(void) {}
static inline void cmci_rediscover(int dying) {}
static inline void cmci_recheck(void) {}
#endif

#ifdef CONFIG_X86_MCE_AMD
void mce_amd_feature_init(struct cpuinfo_x86 *c);
#else
static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
#endif

int mce_available(struct cpuinfo_x86 *c);

DECLARE_PER_CPU(unsigned, mce_exception_count);
DECLARE_PER_CPU(unsigned, mce_poll_count);

extern atomic_t mce_entry;

typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);

enum mcp_flags {
	MCP_TIMESTAMP = (1 << 0),	/* log time stamp */
	MCP_UC = (1 << 1),		/* log uncorrected errors */
	MCP_DONTLOG = (1 << 2),		/* only clear, don't log */
};
void machine_check_poll(enum mcp_flags flags, mce_banks_t *b);

int mce_notify_irq(void);
void mce_notify_process(void);

DECLARE_PER_CPU(struct mce, injectm);

extern void register_mce_write_callback(ssize_t (*)(struct file *filp,
				    const char __user *ubuf,
				    size_t usize, loff_t *off));

/*
 * Exception handler
 */

/* Call the installed machine check handler for this CPU setup. */
extern void (*machine_check_vector)(struct pt_regs *, long error_code);
void do_machine_check(struct pt_regs *, long);

/*
 * Threshold handler
 */

extern void (*mce_threshold_vector)(void);
extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);

/*
 * Thermal handler
 */

void intel_init_thermal(struct cpuinfo_x86 *c);

void mce_log_therm_throt_event(__u64 status);

/* Interrupt Handler for core thermal thresholds */
extern int (*platform_thermal_notify)(__u64 msr_val);

#ifdef CONFIG_X86_THERMAL_VECTOR
extern void mcheck_intel_therm_init(void);
#else
static inline void mcheck_intel_therm_init(void) { }
#endif

/*
 * Used by APEI to report memory error via /dev/mcelog
 */

struct cper_sec_mem_err;
extern void apei_mce_report_mem_error(int corrected,
				      struct cper_sec_mem_err *mem_err);

#endif /* __KERNEL__ */
#endif /* _ASM_X86_MCE_H */
Commit	Line	Data
1965aae3 PA	1	#ifndef _ASM_X86_MCE_H
1965aae3 PA	2	#define _ASM_X86_MCE_H
e2f43029	3
999b697b	4	#include <linux/types.h>
e2f43029	5	#include <asm/ioctls.h>
e2f43029 TG	6
	7	/*
	8	* Machine Check support for x86
	9	*/
	10
2b90e77e	11	/* MCG_CAP register defines */
01c6680a	12	#define MCG_BANKCNT_MASK 0xff /* Number of Banks */
e4876839	13	#define MCG_CTL_P (1ULL<<8) /* MCG_CTL register available */
01c6680a TG	14	#define MCG_EXT_P (1ULL<<9) /* Extended registers available */
	15	#define MCG_CMCI_P (1ULL<<10) /* CMCI supported */
	16	#define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */
	17	#define MCG_EXT_CNT_SHIFT 16
	18	#define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
ed7290d0	19	#define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */
e2f43029	20
2b90e77e	21	/* MCG_STATUS register defines */
06b851d9 IM	22	#define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
	23	#define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
	24	#define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
e2f43029	25
2b90e77e	26	/* MCi_STATUS register defines */
06b851d9 IM	27	#define MCI_STATUS_VAL (1ULL<<63) /* valid error */
	28	#define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
	29	#define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
	30	#define MCI_STATUS_EN (1ULL<<60) /* error enabled */
	31	#define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
	32	#define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
	33	#define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */
ed7290d0 AK	34	#define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */
	35	#define MCI_STATUS_AR (1ULL<<55) /* Action required */
	36
2b90e77e HS	37	/* MCi_MISC register defines */
	38	#define MCI_MISC_ADDR_LSB(m) ((m) & 0x3f)
	39	#define MCI_MISC_ADDR_MODE(m) (((m) >> 6) & 7)
	40	#define MCI_MISC_ADDR_SEGOFF 0 /* segment offset */
	41	#define MCI_MISC_ADDR_LINEAR 1 /* linear address */
	42	#define MCI_MISC_ADDR_PHYS 2 /* physical address */
	43	#define MCI_MISC_ADDR_MEM 3 /* memory address */
	44	#define MCI_MISC_ADDR_GENERIC 7 /* generic */
e2f43029	45
1f9a0bd4 HY	46	/* CTL2 register defines */
1f9a0bd4 HY	47	#define MCI_CTL2_CMCI_EN (1ULL << 30)
3c417588	48	#define MCI_CTL2_CMCI_THRESHOLD_MASK 0x7fffULL
1f9a0bd4	49
5b7e88ed HY	50	#define MCJ_CTX_MASK 3
	51	#define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK)
	52	#define MCJ_CTX_RANDOM 0 /* inject context: random */
2c29d9dd CG	53	#define MCJ_CTX_PROCESS 0x1 /* inject context: process */
	54	#define MCJ_CTX_IRQ 0x2 /* inject context: IRQ */
	55	#define MCJ_NMI_BROADCAST 0x4 /* do NMI broadcasting */
	56	#define MCJ_EXCEPTION 0x8 /* raise as exception */
	57	#define MCJ_IRQ_BRAODCAST 0x10 /* do IRQ broadcasting */
5b7e88ed	58
e2f43029 TG	59	/* Fields are zero when not available */
	60	struct mce {
	61	__u64 status;
	62	__u64 misc;
	63	__u64 addr;
	64	__u64 mcgstatus;
65ea5b03	65	__u64 ip;
e2f43029	66	__u64 tsc; /* cpu time stamp counter */
8ee08347 AK	67	__u64 time; /* wall time_t when error was detected */
8ee08347 AK	68	__u8 cpuvendor; /* cpu vendor as encoded in system.h */
5b7e88ed HY	69	__u8 inject_flags; /* software inject flags */
5b7e88ed HY	70	__u16 pad;
8ee08347	71	__u32 cpuid; /* CPUID 1 EAX */
e2f43029 TG	72	__u8 cs; /* code segment */
e2f43029 TG	73	__u8 bank; /* machine check bank */
d620c67f	74	__u8 cpu; /* cpu number; obsolete; use extcpu now */
e2f43029	75	__u8 finished; /* entry is valid */
d620c67f	76	__u32 extcpu; /* linux cpu number that detected the error */
8ee08347 AK	77	__u32 socketid; /* CPU socket ID */
	78	__u32 apicid; /* CPU initial apic ID */
	79	__u64 mcgcap; /* MCGCAP MSR: machine check capabilities of CPU */
e2f43029 TG	80	};
	81
	82	/*
	83	* This structure contains all data related to the MCE log. Also
	84	* carries a signature to make it easier to find from external
	85	* debugging tools. Each entry is only valid when its finished flag
	86	* is set.
	87	*/
	88
	89	#define MCE_LOG_LEN 32
	90
	91	struct mce_log {
	92	char signature[12]; /* "MACHINECHECK" */
	93	unsigned len; /* = MCE_LOG_LEN */
	94	unsigned next;
	95	unsigned flags;
f6fb0ac0	96	unsigned recordlen; /* length of struct mce */
e2f43029 TG	97	struct mce entry[MCE_LOG_LEN];
	98	};
	99
	100	#define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */
	101
	102	#define MCE_LOG_SIGNATURE "MACHINECHECK"
	103
	104	#define MCE_GET_RECORD_LEN _IOR('M', 1, int)
	105	#define MCE_GET_LOG_LEN _IOR('M', 2, int)
	106	#define MCE_GETCLEAR_FLAGS _IOR('M', 3, int)
	107
	108	/* Software defined banks */
	109	#define MCE_EXTENDED_BANK 128
	110	#define MCE_THERMAL_BANK MCE_EXTENDED_BANK + 0
	111
	112	#define K8_MCE_THRESHOLD_BASE (MCE_EXTENDED_BANK + 1) /* MCE_AMD */
	113	#define K8_MCE_THRESHOLD_BANK_0 (MCE_THRESHOLD_BASE + 0 * 9)
	114	#define K8_MCE_THRESHOLD_BANK_1 (MCE_THRESHOLD_BASE + 1 * 9)
	115	#define K8_MCE_THRESHOLD_BANK_2 (MCE_THRESHOLD_BASE + 2 * 9)
	116	#define K8_MCE_THRESHOLD_BANK_3 (MCE_THRESHOLD_BASE + 3 * 9)
	117	#define K8_MCE_THRESHOLD_BANK_4 (MCE_THRESHOLD_BASE + 4 * 9)
	118	#define K8_MCE_THRESHOLD_BANK_5 (MCE_THRESHOLD_BASE + 5 * 9)
	119	#define K8_MCE_THRESHOLD_DRAM_ECC (MCE_THRESHOLD_BANK_4 + 0)
	120
fb253195	121
e2f43029 TG	122	#ifdef __KERNEL__
e2f43029 TG	123
3653ada5 BP	124	extern void mce_register_decode_chain(struct notifier_block *nb);
3653ada5 BP	125	extern void mce_unregister_decode_chain(struct notifier_block *nb);
df39a2e4	126
9e55e44e HS	127	#include <linux/percpu.h>
9e55e44e HS	128	#include <linux/init.h>
60063497	129	#include <linux/atomic.h>
9e55e44e	130
e2f43029	131	extern int mce_disabled;
c6978369	132	extern int mce_p5_enabled;
e2f43029	133
58995d2d	134	#ifdef CONFIG_X86_MCE
a2202aa2	135	int mcheck_init(void);
5e09954a	136	void mcheck_cpu_init(struct cpuinfo_x86 *c);
58995d2d	137	#else
a2202aa2	138	static inline int mcheck_init(void) { return 0; }
5e09954a	139	static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {}
58995d2d HS	140	#endif
58995d2d HS	141
9e55e44e HS	142	#ifdef CONFIG_X86_ANCIENT_MCE
	143	void intel_p5_mcheck_init(struct cpuinfo_x86 *c);
	144	void winchip_mcheck_init(struct cpuinfo_x86 *c);
c6978369	145	static inline void enable_p5_mce(void) { mce_p5_enabled = 1; }
9e55e44e HS	146	#else
	147	static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {}
	148	static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {}
c6978369	149	static inline void enable_p5_mce(void) {}
9e55e44e HS	150	#endif
9e55e44e HS	151
b5f2fa4e	152	void mce_setup(struct mce *m);
e2f43029	153	void mce_log(struct mce *m);
e032d807	154	extern struct device *mce_device[CONFIG_NR_CPUS];
e2f43029	155
41fdff32	156	/*
3ccdccfa AK	157	* Maximum banks number.
	158	* This is the limit of the current register layout on
	159	* Intel CPUs.
41fdff32	160	*/
3ccdccfa	161	#define MAX_NR_BANKS 32
41fdff32	162
e2f43029	163	#ifdef CONFIG_X86_MCE_INTEL
62fdac59 HS	164	extern int mce_cmci_disabled;
62fdac59 HS	165	extern int mce_ignore_ce;
e2f43029	166	void mce_intel_feature_init(struct cpuinfo_x86 *c);
88ccbedd AK	167	void cmci_clear(void);
	168	void cmci_reenable(void);
	169	void cmci_rediscover(int dying);
	170	void cmci_recheck(void);
e2f43029 TG	171	#else
e2f43029 TG	172	static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
88ccbedd AK	173	static inline void cmci_clear(void) {}
	174	static inline void cmci_reenable(void) {}
	175	static inline void cmci_rediscover(int dying) {}
	176	static inline void cmci_recheck(void) {}
e2f43029 TG	177	#endif
	178
	179	#ifdef CONFIG_X86_MCE_AMD
	180	void mce_amd_feature_init(struct cpuinfo_x86 *c);
	181	#else
	182	static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
	183	#endif
	184
38736072	185	int mce_available(struct cpuinfo_x86 *c);
88ccbedd	186
01ca79f1	187	DECLARE_PER_CPU(unsigned, mce_exception_count);
ca84f696	188	DECLARE_PER_CPU(unsigned, mce_poll_count);
01ca79f1	189
e2f43029 TG	190	extern atomic_t mce_entry;
e2f43029 TG	191
ee031c31 AK	192	typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
	193	DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);
	194
b79109c3 AK	195	enum mcp_flags {
	196	MCP_TIMESTAMP = (1 << 0), /* log time stamp */
	197	MCP_UC = (1 << 1), /* log uncorrected errors */
5679af4c	198	MCP_DONTLOG = (1 << 2), /* only clear, don't log */
b79109c3	199	};
38736072	200	void machine_check_poll(enum mcp_flags flags, mce_banks_t *b);
b79109c3	201
9ff36ee9	202	int mce_notify_irq(void);
9b1beaf2	203	void mce_notify_process(void);
e2f43029	204
ea149b36	205	DECLARE_PER_CPU(struct mce, injectm);
66f5ddf3 LT	206
	207	extern void register_mce_write_callback(ssize_t ()(struct file filp,
	208	const char __user *ubuf,
	209	size_t usize, loff_t *off));
ea149b36	210
58995d2d HS	211	/*
	212	* Exception handler
	213	*/
	214
	215	/* Call the installed machine check handler for this CPU setup. */
	216	extern void (machine_check_vector)(struct pt_regs , long error_code);
	217	void do_machine_check(struct pt_regs *, long);
	218
	219	/*
	220	* Threshold handler
	221	*/
e2f43029	222
b2762686	223	extern void (*mce_threshold_vector)(void);
58995d2d	224	extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
b2762686	225
e8ce2c5e HS	226	/*
	227	* Thermal handler
	228	*/
	229
e8ce2c5e HS	230	void intel_init_thermal(struct cpuinfo_x86 *c);
e8ce2c5e HS	231
e8ce2c5e	232	void mce_log_therm_throt_event(__u64 status);
a2202aa2	233
9e76a97e D	234	/* Interrupt Handler for core thermal thresholds */
	235	extern int (*platform_thermal_notify)(__u64 msr_val);
	236
a2202aa2 YW	237	#ifdef CONFIG_X86_THERMAL_VECTOR
	238	extern void mcheck_intel_therm_init(void);
	239	#else
	240	static inline void mcheck_intel_therm_init(void) { }
	241	#endif
	242
d334a491 HY	243	/*
	244	* Used by APEI to report memory error via /dev/mcelog
	245	*/
	246
	247	struct cper_sec_mem_err;
	248	extern void apei_mce_report_mem_error(int corrected,
	249	struct cper_sec_mem_err *mem_err);
	250
e2f43029	251	#endif /* __KERNEL__ */
1965aae3	252	#endif /* _ASM_X86_MCE_H */