[deliverable/linux.git] / arch / x86 / include / asm / mce.h

#ifndef _ASM_X86_MCE_H
#define _ASM_X86_MCE_H

#include <linux/types.h>
#include <asm/ioctls.h>

/*
 * Machine Check support for x86
 */

#define MCG_BANKCNT_MASK	0xff         /* Number of Banks */
#define MCG_CTL_P		(1ULL<<8)    /* MCG_CAP register available */
#define MCG_EXT_P		(1ULL<<9)    /* Extended registers available */
#define MCG_CMCI_P		(1ULL<<10)   /* CMCI supported */
#define MCG_EXT_CNT_MASK	0xff0000     /* Number of Extended registers */
#define MCG_EXT_CNT_SHIFT	16
#define MCG_EXT_CNT(c)		(((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)

#define MCG_STATUS_RIPV  (1ULL<<0)   /* restart ip valid */
#define MCG_STATUS_EIPV  (1ULL<<1)   /* ip points to correct instruction */
#define MCG_STATUS_MCIP  (1ULL<<2)   /* machine check in progress */

#define MCI_STATUS_VAL   (1ULL<<63)  /* valid error */
#define MCI_STATUS_OVER  (1ULL<<62)  /* previous errors lost */
#define MCI_STATUS_UC    (1ULL<<61)  /* uncorrected error */
#define MCI_STATUS_EN    (1ULL<<60)  /* error enabled */
#define MCI_STATUS_MISCV (1ULL<<59)  /* misc error reg. valid */
#define MCI_STATUS_ADDRV (1ULL<<58)  /* addr reg. valid */
#define MCI_STATUS_PCC   (1ULL<<57)  /* processor context corrupt */

/* Fields are zero when not available */
struct mce {
	__u64 status;
	__u64 misc;
	__u64 addr;
	__u64 mcgstatus;
	__u64 ip;
	__u64 tsc;	/* cpu time stamp counter */
	__u64 time;	/* wall time_t when error was detected */
	__u8  cpuvendor;	/* cpu vendor as encoded in system.h */
	__u8  pad1;
	__u16 pad2;
	__u32 cpuid;	/* CPUID 1 EAX */
	__u8  cs;		/* code segment */
	__u8  bank;	/* machine check bank */
	__u8  cpu;	/* cpu number; obsolete; use extcpu now */
	__u8  finished;   /* entry is valid */
	__u32 extcpu;	/* linux cpu number that detected the error */
	__u32 socketid;	/* CPU socket ID */
	__u32 apicid;	/* CPU initial apic ID */
	__u64 mcgcap;	/* MCGCAP MSR: machine check capabilities of CPU */
};

/*
 * This structure contains all data related to the MCE log.  Also
 * carries a signature to make it easier to find from external
 * debugging tools.  Each entry is only valid when its finished flag
 * is set.
 */

#define MCE_LOG_LEN 32

struct mce_log {
	char signature[12]; /* "MACHINECHECK" */
	unsigned len;	    /* = MCE_LOG_LEN */
	unsigned next;
	unsigned flags;
	unsigned recordlen;	/* length of struct mce */
	struct mce entry[MCE_LOG_LEN];
};

#define MCE_OVERFLOW 0		/* bit 0 in flags means overflow */

#define MCE_LOG_SIGNATURE	"MACHINECHECK"

#define MCE_GET_RECORD_LEN   _IOR('M', 1, int)
#define MCE_GET_LOG_LEN      _IOR('M', 2, int)
#define MCE_GETCLEAR_FLAGS   _IOR('M', 3, int)

/* Software defined banks */
#define MCE_EXTENDED_BANK	128
#define MCE_THERMAL_BANK	MCE_EXTENDED_BANK + 0

#define K8_MCE_THRESHOLD_BASE      (MCE_EXTENDED_BANK + 1)      /* MCE_AMD */
#define K8_MCE_THRESHOLD_BANK_0    (MCE_THRESHOLD_BASE + 0 * 9)
#define K8_MCE_THRESHOLD_BANK_1    (MCE_THRESHOLD_BASE + 1 * 9)
#define K8_MCE_THRESHOLD_BANK_2    (MCE_THRESHOLD_BASE + 2 * 9)
#define K8_MCE_THRESHOLD_BANK_3    (MCE_THRESHOLD_BASE + 3 * 9)
#define K8_MCE_THRESHOLD_BANK_4    (MCE_THRESHOLD_BASE + 4 * 9)
#define K8_MCE_THRESHOLD_BANK_5    (MCE_THRESHOLD_BASE + 5 * 9)
#define K8_MCE_THRESHOLD_DRAM_ECC  (MCE_THRESHOLD_BANK_4 + 0)

#ifdef __KERNEL__

extern int mce_disabled;

#include <asm/atomic.h>
#include <linux/percpu.h>

void mce_setup(struct mce *m);
void mce_log(struct mce *m);
DECLARE_PER_CPU(struct sys_device, mce_dev);
extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);

/*
 * To support more than 128 would need to escape the predefined
 * Linux defined extended banks first.
 */
#define MAX_NR_BANKS (MCE_EXTENDED_BANK - 1)

#ifdef CONFIG_X86_MCE_INTEL
void mce_intel_feature_init(struct cpuinfo_x86 *c);
void cmci_clear(void);
void cmci_reenable(void);
void cmci_rediscover(int dying);
void cmci_recheck(void);
#else
static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
static inline void cmci_clear(void) {}
static inline void cmci_reenable(void) {}
static inline void cmci_rediscover(int dying) {}
static inline void cmci_recheck(void) {}
#endif

#ifdef CONFIG_X86_MCE_AMD
void mce_amd_feature_init(struct cpuinfo_x86 *c);
#else
static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
#endif

int mce_available(struct cpuinfo_x86 *c);

DECLARE_PER_CPU(unsigned, mce_exception_count);
DECLARE_PER_CPU(unsigned, mce_poll_count);

void mce_log_therm_throt_event(__u64 status);

extern atomic_t mce_entry;

void do_machine_check(struct pt_regs *, long);

typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);

enum mcp_flags {
	MCP_TIMESTAMP = (1 << 0),	/* log time stamp */
	MCP_UC = (1 << 1),		/* log uncorrected errors */
	MCP_DONTLOG = (1 << 2),		/* only clear, don't log */
};
void machine_check_poll(enum mcp_flags flags, mce_banks_t *b);

int mce_notify_user(void);

DECLARE_PER_CPU(struct mce, injectm);
extern struct file_operations mce_chrdev_ops;

#ifdef CONFIG_X86_MCE
void mcheck_init(struct cpuinfo_x86 *c);
#else
#define mcheck_init(c) do { } while (0)
#endif

extern void (*mce_threshold_vector)(void);

#endif /* __KERNEL__ */
#endif /* _ASM_X86_MCE_H */
Commit	Line	Data
1965aae3 PA	1	#ifndef _ASM_X86_MCE_H
1965aae3 PA	2	#define _ASM_X86_MCE_H
e2f43029	3
999b697b	4	#include <linux/types.h>
e2f43029	5	#include <asm/ioctls.h>
e2f43029 TG	6
	7	/*
	8	* Machine Check support for x86
	9	*/
	10
01c6680a TG	11	#define MCG_BANKCNT_MASK 0xff /* Number of Banks */
	12	#define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */
	13	#define MCG_EXT_P (1ULL<<9) /* Extended registers available */
	14	#define MCG_CMCI_P (1ULL<<10) /* CMCI supported */
	15	#define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */
	16	#define MCG_EXT_CNT_SHIFT 16
	17	#define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
e2f43029	18
06b851d9 IM	19	#define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
	20	#define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
	21	#define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
e2f43029	22
06b851d9 IM	23	#define MCI_STATUS_VAL (1ULL<<63) /* valid error */
	24	#define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
	25	#define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
	26	#define MCI_STATUS_EN (1ULL<<60) /* error enabled */
	27	#define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
	28	#define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
	29	#define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */
e2f43029 TG	30
	31	/* Fields are zero when not available */
	32	struct mce {
	33	__u64 status;
	34	__u64 misc;
	35	__u64 addr;
	36	__u64 mcgstatus;
65ea5b03	37	__u64 ip;
e2f43029	38	__u64 tsc; /* cpu time stamp counter */
8ee08347 AK	39	__u64 time; /* wall time_t when error was detected */
	40	__u8 cpuvendor; /* cpu vendor as encoded in system.h */
	41	__u8 pad1;
	42	__u16 pad2;
	43	__u32 cpuid; /* CPUID 1 EAX */
e2f43029 TG	44	__u8 cs; /* code segment */
e2f43029 TG	45	__u8 bank; /* machine check bank */
d620c67f	46	__u8 cpu; /* cpu number; obsolete; use extcpu now */
e2f43029	47	__u8 finished; /* entry is valid */
d620c67f	48	__u32 extcpu; /* linux cpu number that detected the error */
8ee08347 AK	49	__u32 socketid; /* CPU socket ID */
	50	__u32 apicid; /* CPU initial apic ID */
	51	__u64 mcgcap; /* MCGCAP MSR: machine check capabilities of CPU */
e2f43029 TG	52	};
	53
	54	/*
	55	* This structure contains all data related to the MCE log. Also
	56	* carries a signature to make it easier to find from external
	57	* debugging tools. Each entry is only valid when its finished flag
	58	* is set.
	59	*/
	60
	61	#define MCE_LOG_LEN 32
	62
	63	struct mce_log {
	64	char signature[12]; /* "MACHINECHECK" */
	65	unsigned len; /* = MCE_LOG_LEN */
	66	unsigned next;
	67	unsigned flags;
f6fb0ac0	68	unsigned recordlen; /* length of struct mce */
e2f43029 TG	69	struct mce entry[MCE_LOG_LEN];
	70	};
	71
	72	#define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */
	73
	74	#define MCE_LOG_SIGNATURE "MACHINECHECK"
	75
	76	#define MCE_GET_RECORD_LEN _IOR('M', 1, int)
	77	#define MCE_GET_LOG_LEN _IOR('M', 2, int)
	78	#define MCE_GETCLEAR_FLAGS _IOR('M', 3, int)
	79
	80	/* Software defined banks */
	81	#define MCE_EXTENDED_BANK 128
	82	#define MCE_THERMAL_BANK MCE_EXTENDED_BANK + 0
	83
	84	#define K8_MCE_THRESHOLD_BASE (MCE_EXTENDED_BANK + 1) /* MCE_AMD */
	85	#define K8_MCE_THRESHOLD_BANK_0 (MCE_THRESHOLD_BASE + 0 * 9)
	86	#define K8_MCE_THRESHOLD_BANK_1 (MCE_THRESHOLD_BASE + 1 * 9)
	87	#define K8_MCE_THRESHOLD_BANK_2 (MCE_THRESHOLD_BASE + 2 * 9)
	88	#define K8_MCE_THRESHOLD_BANK_3 (MCE_THRESHOLD_BASE + 3 * 9)
	89	#define K8_MCE_THRESHOLD_BANK_4 (MCE_THRESHOLD_BASE + 4 * 9)
	90	#define K8_MCE_THRESHOLD_BANK_5 (MCE_THRESHOLD_BASE + 5 * 9)
	91	#define K8_MCE_THRESHOLD_DRAM_ECC (MCE_THRESHOLD_BANK_4 + 0)
	92
e2f43029 TG	93	#ifdef __KERNEL__
e2f43029 TG	94
e2f43029	95	extern int mce_disabled;
e2f43029 TG	96
e2f43029 TG	97	#include <asm/atomic.h>
01ca79f1	98	#include <linux/percpu.h>
e2f43029	99
b5f2fa4e	100	void mce_setup(struct mce *m);
e2f43029	101	void mce_log(struct mce *m);
cb491fca	102	DECLARE_PER_CPU(struct sys_device, mce_dev);
8735728e	103	extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
e2f43029	104
41fdff32 AK	105	/*
	106	* To support more than 128 would need to escape the predefined
	107	* Linux defined extended banks first.
	108	*/
	109	#define MAX_NR_BANKS (MCE_EXTENDED_BANK - 1)
	110
e2f43029 TG	111	#ifdef CONFIG_X86_MCE_INTEL
e2f43029 TG	112	void mce_intel_feature_init(struct cpuinfo_x86 *c);
88ccbedd AK	113	void cmci_clear(void);
	114	void cmci_reenable(void);
	115	void cmci_rediscover(int dying);
	116	void cmci_recheck(void);
e2f43029 TG	117	#else
e2f43029 TG	118	static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
88ccbedd AK	119	static inline void cmci_clear(void) {}
	120	static inline void cmci_reenable(void) {}
	121	static inline void cmci_rediscover(int dying) {}
	122	static inline void cmci_recheck(void) {}
e2f43029 TG	123	#endif
	124
	125	#ifdef CONFIG_X86_MCE_AMD
	126	void mce_amd_feature_init(struct cpuinfo_x86 *c);
	127	#else
	128	static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
	129	#endif
	130
38736072	131	int mce_available(struct cpuinfo_x86 *c);
88ccbedd	132
01ca79f1	133	DECLARE_PER_CPU(unsigned, mce_exception_count);
ca84f696	134	DECLARE_PER_CPU(unsigned, mce_poll_count);
01ca79f1	135
b5f2fa4e	136	void mce_log_therm_throt_event(__u64 status);
e2f43029 TG	137
	138	extern atomic_t mce_entry;
	139
38736072	140	void do_machine_check(struct pt_regs *, long);
b79109c3	141
ee031c31 AK	142	typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
	143	DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);
	144
b79109c3 AK	145	enum mcp_flags {
	146	MCP_TIMESTAMP = (1 << 0), /* log time stamp */
	147	MCP_UC = (1 << 1), /* log uncorrected errors */
5679af4c	148	MCP_DONTLOG = (1 << 2), /* only clear, don't log */
b79109c3	149	};
38736072	150	void machine_check_poll(enum mcp_flags flags, mce_banks_t *b);
b79109c3	151
38736072	152	int mce_notify_user(void);
e2f43029	153
ea149b36 AK	154	DECLARE_PER_CPU(struct mce, injectm);
	155	extern struct file_operations mce_chrdev_ops;
	156
af7a78e9	157	#ifdef CONFIG_X86_MCE
38736072	158	void mcheck_init(struct cpuinfo_x86 *c);
af7a78e9 TG	159	#else
	160	#define mcheck_init(c) do { } while (0)
	161	#endif
e2f43029	162
b2762686 AK	163	extern void (*mce_threshold_vector)(void);
b2762686 AK	164
e2f43029	165	#endif /* __KERNEL__ */
1965aae3	166	#endif /* _ASM_X86_MCE_H */