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1965aae3 PA |
1 | #ifndef _ASM_X86_MPSPEC_H |
2 | #define _ASM_X86_MPSPEC_H | |
c2805aa1 | 3 | |
86c9835b IM |
4 | #include <linux/init.h> |
5 | ||
c2805aa1 TG |
6 | #include <asm/mpspec_def.h> |
7 | ||
11494547 | 8 | extern int apic_version[MAX_APICS]; |
a1ae299d | 9 | extern int pic_mode; |
11494547 | 10 | |
96a388de | 11 | #ifdef CONFIG_X86_32 |
b2af018f IM |
12 | |
13 | /* | |
14 | * Summit or generic (i.e. installer) kernels need lots of bus entries. | |
15 | * Maximum 256 PCI busses, plus 1 ISA bus in each of 4 cabinets. | |
16 | */ | |
17 | #if CONFIG_BASE_SMALL == 0 | |
18 | # define MAX_MP_BUSSES 260 | |
19 | #else | |
20 | # define MAX_MP_BUSSES 32 | |
21 | #endif | |
22 | ||
23 | #define MAX_IRQ_SOURCES 256 | |
c2805aa1 | 24 | |
c2805aa1 | 25 | extern unsigned int def_to_bigsmp; |
ae9d983b | 26 | extern u8 apicid_2_node[]; |
c2805aa1 | 27 | |
d49c4288 YL |
28 | #ifdef CONFIG_X86_NUMAQ |
29 | extern int mp_bus_id_to_node[MAX_MP_BUSSES]; | |
30 | extern int mp_bus_id_to_local[MAX_MP_BUSSES]; | |
31 | extern int quad_local_to_mp_bus_id [NR_CPUS/4][4]; | |
32 | #endif | |
33 | ||
b2af018f | 34 | #define MAX_APICID 256 |
ae9d983b | 35 | |
b2af018f | 36 | #else /* CONFIG_X86_64: */ |
c2805aa1 | 37 | |
b2af018f | 38 | #define MAX_MP_BUSSES 256 |
c2805aa1 | 39 | /* Each PCI slot may be a combo card with its own bus. 4 IRQ pins per slot. */ |
b2af018f | 40 | #define MAX_IRQ_SOURCES (MAX_MP_BUSSES * 4) |
c2805aa1 | 41 | |
b2af018f | 42 | #endif /* CONFIG_X86_64 */ |
ab530e1f | 43 | |
8643f9d0 YL |
44 | extern void early_find_smp_config(void); |
45 | extern void early_get_smp_config(void); | |
46 | ||
c0a282c2 AS |
47 | #if defined(CONFIG_MCA) || defined(CONFIG_EISA) |
48 | extern int mp_bus_id_to_type[MAX_MP_BUSSES]; | |
49 | #endif | |
50 | ||
a6333c3c | 51 | extern DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); |
c0a282c2 | 52 | |
c2805aa1 | 53 | extern unsigned int boot_cpu_physical_apicid; |
e0da3364 | 54 | extern unsigned int max_physical_apicid; |
c2805aa1 | 55 | extern int smp_found_config; |
c2805aa1 TG |
56 | extern int mpc_default_type; |
57 | extern unsigned long mp_lapic_addr; | |
58 | ||
c2805aa1 | 59 | extern void get_smp_config(void); |
550fe4f1 | 60 | |
af1cf204 | 61 | #ifdef CONFIG_X86_MPPARSE |
550fe4f1 | 62 | extern void find_smp_config(void); |
2944e16b | 63 | extern void early_reserve_e820_mpc_new(void); |
abfe0af9 | 64 | extern int enable_update_mptable; |
fd6c6661 | 65 | extern int default_mpc_apic_id(struct mpc_cpu *m); |
72302142 | 66 | extern void default_smp_read_mpc_oem(struct mpc_table *mpc); |
90e1c696 TG |
67 | # ifdef CONFIG_X86_IO_APIC |
68 | extern void default_mpc_oem_bus_info(struct mpc_bus *m, char *str); | |
69 | # else | |
70 | # define default_mpc_oem_bus_info NULL | |
71 | # endif | |
af1cf204 | 72 | #else |
550fe4f1 | 73 | static inline void find_smp_config(void) { } |
af1cf204 | 74 | static inline void early_reserve_e820_mpc_new(void) { } |
abfe0af9 | 75 | #define enable_update_mptable 0 |
fd6c6661 | 76 | #define default_mpc_apic_id NULL |
72302142 | 77 | #define default_smp_read_mpc_oem NULL |
90e1c696 | 78 | #define default_mpc_oem_bus_info NULL |
af1cf204 | 79 | #endif |
c2805aa1 | 80 | |
903dcb5a | 81 | void __cpuinit generic_processor_info(int apicid, int version); |
c2805aa1 | 82 | #ifdef CONFIG_ACPI |
a65d1d64 | 83 | extern void mp_register_ioapic(int id, u32 address, u32 gsi_base); |
c2805aa1 TG |
84 | extern void mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, |
85 | u32 gsi); | |
86 | extern void mp_config_acpi_legacy_irqs(void); | |
a2f809b0 YL |
87 | struct device; |
88 | extern int mp_register_gsi(struct device *dev, u32 gsi, int edge_level, | |
89 | int active_high_low); | |
cc6c5006 | 90 | extern int acpi_probe_gsi(void); |
835fc943 | 91 | #ifdef CONFIG_X86_IO_APIC |
4924e228 | 92 | extern int mp_find_ioapic(int gsi); |
c3e137d1 | 93 | extern int mp_find_ioapic_pin(int ioapic, int gsi); |
835fc943 | 94 | #endif |
cc6c5006 YL |
95 | #else /* !CONFIG_ACPI: */ |
96 | static inline int acpi_probe_gsi(void) | |
97 | { | |
98 | return 0; | |
99 | } | |
c2805aa1 TG |
100 | #endif /* CONFIG_ACPI */ |
101 | ||
102 | #define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_APICS) | |
103 | ||
30971e17 | 104 | struct physid_mask { |
c2805aa1 TG |
105 | unsigned long mask[PHYSID_ARRAY_SIZE]; |
106 | }; | |
107 | ||
108 | typedef struct physid_mask physid_mask_t; | |
109 | ||
110 | #define physid_set(physid, map) set_bit(physid, (map).mask) | |
111 | #define physid_clear(physid, map) clear_bit(physid, (map).mask) | |
112 | #define physid_isset(physid, map) test_bit(physid, (map).mask) | |
30971e17 | 113 | #define physid_test_and_set(physid, map) \ |
c2805aa1 TG |
114 | test_and_set_bit(physid, (map).mask) |
115 | ||
30971e17 | 116 | #define physids_and(dst, src1, src2) \ |
c2805aa1 TG |
117 | bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_APICS) |
118 | ||
30971e17 | 119 | #define physids_or(dst, src1, src2) \ |
c2805aa1 TG |
120 | bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_APICS) |
121 | ||
30971e17 | 122 | #define physids_clear(map) \ |
c2805aa1 TG |
123 | bitmap_zero((map).mask, MAX_APICS) |
124 | ||
30971e17 | 125 | #define physids_complement(dst, src) \ |
c2805aa1 TG |
126 | bitmap_complement((dst).mask, (src).mask, MAX_APICS) |
127 | ||
30971e17 | 128 | #define physids_empty(map) \ |
c2805aa1 TG |
129 | bitmap_empty((map).mask, MAX_APICS) |
130 | ||
30971e17 | 131 | #define physids_equal(map1, map2) \ |
c2805aa1 TG |
132 | bitmap_equal((map1).mask, (map2).mask, MAX_APICS) |
133 | ||
30971e17 | 134 | #define physids_weight(map) \ |
c2805aa1 TG |
135 | bitmap_weight((map).mask, MAX_APICS) |
136 | ||
30971e17 | 137 | #define physids_shift_right(d, s, n) \ |
c2805aa1 TG |
138 | bitmap_shift_right((d).mask, (s).mask, n, MAX_APICS) |
139 | ||
30971e17 | 140 | #define physids_shift_left(d, s, n) \ |
c2805aa1 TG |
141 | bitmap_shift_left((d).mask, (s).mask, n, MAX_APICS) |
142 | ||
143 | #define physids_coerce(map) ((map).mask[0]) | |
144 | ||
145 | #define physids_promote(physids) \ | |
146 | ({ \ | |
147 | physid_mask_t __physid_mask = PHYSID_MASK_NONE; \ | |
148 | __physid_mask.mask[0] = physids; \ | |
149 | __physid_mask; \ | |
150 | }) | |
151 | ||
b6df1b8b | 152 | /* Note: will create very large stack frames if physid_mask_t is big */ |
c2805aa1 TG |
153 | #define physid_mask_of_physid(physid) \ |
154 | ({ \ | |
155 | physid_mask_t __physid_mask = PHYSID_MASK_NONE; \ | |
156 | physid_set(physid, __physid_mask); \ | |
157 | __physid_mask; \ | |
158 | }) | |
159 | ||
b6df1b8b JS |
160 | static inline void physid_set_mask_of_physid(int physid, physid_mask_t *map) |
161 | { | |
162 | physids_clear(*map); | |
163 | physid_set(physid, *map); | |
164 | } | |
165 | ||
c2805aa1 TG |
166 | #define PHYSID_MASK_ALL { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} } |
167 | #define PHYSID_MASK_NONE { {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} } | |
168 | ||
169 | extern physid_mask_t phys_cpu_present_map; | |
170 | ||
fb5b33c9 IM |
171 | extern int generic_mps_oem_check(struct mpc_table *, char *, char *); |
172 | ||
173 | extern int default_acpi_madt_oem_check(char *, char *); | |
174 | ||
1965aae3 | 175 | #endif /* _ASM_X86_MPSPEC_H */ |