[deliverable/linux.git] / arch / x86 / include / asm / mpspec_def.h

#ifndef _ASM_X86_MPSPEC_DEF_H
#define _ASM_X86_MPSPEC_DEF_H

/*
 * Structure definitions for SMP machines following the
 * Intel Multiprocessing Specification 1.1 and 1.4.
 */

/*
 * This tag identifies where the SMP configuration
 * information is.
 */

#define SMP_MAGIC_IDENT	(('_'<<24) | ('P'<<16) | ('M'<<8) | '_')

#ifdef CONFIG_X86_32
# define MAX_MPC_ENTRY 1024
# define MAX_APICS      256
#else
# if NR_CPUS <= 255
#  define MAX_APICS     255
# else
#  define MAX_APICS   32768
# endif
#endif

struct intel_mp_floating {
	char mpf_signature[4];		/* "_MP_"			*/
	unsigned int mpf_physptr;	/* Configuration table address	*/
	unsigned char mpf_length;	/* Our length (paragraphs)	*/
	unsigned char mpf_specification;/* Specification version	*/
	unsigned char mpf_checksum;	/* Checksum (makes sum 0)	*/
	unsigned char mpf_feature1;	/* Standard or configuration ?	*/
	unsigned char mpf_feature2;	/* Bit7 set for IMCR|PIC	*/
	unsigned char mpf_feature3;	/* Unused (0)			*/
	unsigned char mpf_feature4;	/* Unused (0)			*/
	unsigned char mpf_feature5;	/* Unused (0)			*/
};

#define MPC_SIGNATURE "PCMP"

struct mpc_table {
	char signature[4];
	unsigned short length;		/* Size of table */
	char spec;			/* 0x01 */
	char checksum;
	char oem[8];
	char productid[12];
	unsigned int oemptr;		/* 0 if not present */
	unsigned short oemsize;		/* 0 if not present */
	unsigned short oemcount;
	unsigned int lapic;		/* APIC address */
	unsigned int reserved;
};

/* Followed by entries */

#define	MP_PROCESSOR		0
#define	MP_BUS			1
#define	MP_IOAPIC		2
#define	MP_INTSRC		3
#define	MP_LINTSRC		4
/* Used by IBM NUMA-Q to describe node locality */
#define	MP_TRANSLATION		192

#define CPU_ENABLED		1	/* Processor is available */
#define CPU_BOOTPROCESSOR	2	/* Processor is the BP */

#define CPU_STEPPING_MASK	0x000F
#define CPU_MODEL_MASK		0x00F0
#define CPU_FAMILY_MASK		0x0F00

struct mpc_cpu {
	unsigned char type;
	unsigned char apicid;		/* Local APIC number */
	unsigned char apicver;		/* Its versions */
	unsigned char cpuflag;
	unsigned int cpufeature;
	unsigned int featureflag;	/* CPUID feature value */
	unsigned int reserved[2];
};

struct mpc_bus {
	unsigned char type;
	unsigned char busid;
	unsigned char bustype[6];
};

/* List of Bus Type string values, Intel MP Spec. */
#define BUSTYPE_EISA	"EISA"
#define BUSTYPE_ISA	"ISA"
#define BUSTYPE_INTERN	"INTERN"	/* Internal BUS */
#define BUSTYPE_MCA	"MCA"
#define BUSTYPE_VL	"VL"		/* Local bus */
#define BUSTYPE_PCI	"PCI"
#define BUSTYPE_PCMCIA	"PCMCIA"
#define BUSTYPE_CBUS	"CBUS"
#define BUSTYPE_CBUSII	"CBUSII"
#define BUSTYPE_FUTURE	"FUTURE"
#define BUSTYPE_MBI	"MBI"
#define BUSTYPE_MBII	"MBII"
#define BUSTYPE_MPI	"MPI"
#define BUSTYPE_MPSA	"MPSA"
#define BUSTYPE_NUBUS	"NUBUS"
#define BUSTYPE_TC	"TC"
#define BUSTYPE_VME	"VME"
#define BUSTYPE_XPRESS	"XPRESS"

#define MPC_APIC_USABLE		0x01

struct mpc_ioapic {
	unsigned char type;
	unsigned char apicid;
	unsigned char apicver;
	unsigned char flags;
	unsigned int apicaddr;
};

struct mpc_intsrc {
	unsigned char type;
	unsigned char irqtype;
	unsigned short irqflag;
	unsigned char srcbus;
	unsigned char srcbusirq;
	unsigned char dstapic;
	unsigned char dstirq;
};

enum mp_irq_source_types {
	mp_INT = 0,
	mp_NMI = 1,
	mp_SMI = 2,
	mp_ExtINT = 3
};

#define MP_IRQDIR_DEFAULT	0
#define MP_IRQDIR_HIGH		1
#define MP_IRQDIR_LOW		3

#define MP_APIC_ALL	0xFF

struct mpc_lintsrc {
	unsigned char type;
	unsigned char irqtype;
	unsigned short irqflag;
	unsigned char srcbusid;
	unsigned char srcbusirq;
	unsigned char destapic;
	unsigned char destapiclint;
};

#define MPC_OEM_SIGNATURE "_OEM"

struct mpc_oemtable {
	char signature[4];
	unsigned short length;		/* Size of table */
	char  rev;			/* 0x01 */
	char  checksum;
	char  mpc[8];
};

/*
 *	Default configurations
 *
 *	1	2 CPU ISA 82489DX
 *	2	2 CPU EISA 82489DX neither IRQ 0 timer nor IRQ 13 DMA chaining
 *	3	2 CPU EISA 82489DX
 *	4	2 CPU MCA 82489DX
 *	5	2 CPU ISA+PCI
 *	6	2 CPU EISA+PCI
 *	7	2 CPU MCA+PCI
 */

enum mp_bustype {
	MP_BUS_ISA = 1,
	MP_BUS_EISA,
	MP_BUS_PCI,
	MP_BUS_MCA,
};
#endif /* _ASM_X86_MPSPEC_DEF_H */
Commit	Line	Data
1965aae3 PA	1	#ifndef _ASM_X86_MPSPEC_DEF_H
1965aae3 PA	2	#define _ASM_X86_MPSPEC_DEF_H
1da177e4 LT	3
	4	/*
	5	* Structure definitions for SMP machines following the
	6	* Intel Multiprocessing Specification 1.1 and 1.4.
	7	*/
	8
	9	/*
	10	* This tag identifies where the SMP configuration
64883ab0	11	* information is.
1da177e4	12	*/
64883ab0	13
8f08403e	14	#define SMP_MAGIC_IDENT (('_'<<24) \| ('P'<<16) \| ('M'<<8) \| '_')
1da177e4	15
64883ab0 TG	16	#ifdef CONFIG_X86_32
	17	# define MAX_MPC_ENTRY 1024
	18	# define MAX_APICS 256
	19	#else
ab9c0bb8 JS	20	# if NR_CPUS <= 255
	21	# define MAX_APICS 255
	22	# else
	23	# define MAX_APICS 32768
	24	# endif
64883ab0	25	#endif
1da177e4	26
8f08403e	27	struct intel_mp_floating {
64883ab0 TG	28	char mpf_signature[4]; /* "_MP_" */
64883ab0 TG	29	unsigned int mpf_physptr; /* Configuration table address */
1da177e4 LT	30	unsigned char mpf_length; /* Our length (paragraphs) */
	31	unsigned char mpf_specification;/* Specification version */
	32	unsigned char mpf_checksum; /* Checksum (makes sum 0) */
64883ab0	33	unsigned char mpf_feature1; /* Standard or configuration ? */
1da177e4 LT	34	unsigned char mpf_feature2; /* Bit7 set for IMCR\|PIC */
	35	unsigned char mpf_feature3; /* Unused (0) */
	36	unsigned char mpf_feature4; /* Unused (0) */
	37	unsigned char mpf_feature5; /* Unused (0) */
	38	};
	39
64883ab0 TG	40	#define MPC_SIGNATURE "PCMP"
64883ab0 TG	41
f29521e4	42	struct mpc_table {
6c65da50 JSR	43	char signature[4];
	44	unsigned short length; /* Size of table */
	45	char spec; /* 0x01 */
	46	char checksum;
	47	char oem[8];
	48	char productid[12];
	49	unsigned int oemptr; /* 0 if not present */
	50	unsigned short oemsize; /* 0 if not present */
	51	unsigned short oemcount;
	52	unsigned int lapic; /* APIC address */
64883ab0	53	unsigned int reserved;
1da177e4 LT	54	};
	55
	56	/* Followed by entries */
	57
64883ab0 TG	58	#define MP_PROCESSOR 0
	59	#define MP_BUS 1
	60	#define MP_IOAPIC 2
	61	#define MP_INTSRC 3
	62	#define MP_LINTSRC 4
	63	/* Used by IBM NUMA-Q to describe node locality */
	64	#define MP_TRANSLATION 192
	65
	66	#define CPU_ENABLED 1 /* Processor is available */
	67	#define CPU_BOOTPROCESSOR 2 /* Processor is the BP */
	68
	69	#define CPU_STEPPING_MASK 0x000F
	70	#define CPU_MODEL_MASK 0x00F0
	71	#define CPU_FAMILY_MASK 0x0F00
1da177e4	72
f4f21b71	73	struct mpc_cpu {
c4563826 JSR	74	unsigned char type;
	75	unsigned char apicid; /* Local APIC number */
	76	unsigned char apicver; /* Its versions */
	77	unsigned char cpuflag;
	78	unsigned int cpufeature;
	79	unsigned int featureflag; /* CPUID feature value */
	80	unsigned int reserved[2];
1da177e4 LT	81	};
1da177e4 LT	82
00fb8606	83	struct mpc_bus {
d4c715fa JSR	84	unsigned char type;
	85	unsigned char busid;
	86	unsigned char bustype[6];
1da177e4 LT	87	};
	88
	89	/* List of Bus Type string values, Intel MP Spec. */
	90	#define BUSTYPE_EISA "EISA"
	91	#define BUSTYPE_ISA "ISA"
	92	#define BUSTYPE_INTERN "INTERN" /* Internal BUS */
	93	#define BUSTYPE_MCA "MCA"
	94	#define BUSTYPE_VL "VL" /* Local bus */
	95	#define BUSTYPE_PCI "PCI"
	96	#define BUSTYPE_PCMCIA "PCMCIA"
	97	#define BUSTYPE_CBUS "CBUS"
	98	#define BUSTYPE_CBUSII "CBUSII"
	99	#define BUSTYPE_FUTURE "FUTURE"
	100	#define BUSTYPE_MBI "MBI"
	101	#define BUSTYPE_MBII "MBII"
	102	#define BUSTYPE_MPI "MPI"
	103	#define BUSTYPE_MPSA "MPSA"
	104	#define BUSTYPE_NUBUS "NUBUS"
	105	#define BUSTYPE_TC "TC"
	106	#define BUSTYPE_VME "VME"
	107	#define BUSTYPE_XPRESS "XPRESS"
1da177e4	108
64883ab0 TG	109	#define MPC_APIC_USABLE 0x01
64883ab0 TG	110
2b85b5fb	111	struct mpc_ioapic {
5df82c7d JSR	112	unsigned char type;
	113	unsigned char apicid;
	114	unsigned char apicver;
	115	unsigned char flags;
	116	unsigned int apicaddr;
1da177e4 LT	117	};
1da177e4 LT	118
540d4e72	119	struct mpc_intsrc {
e253b396 JSR	120	unsigned char type;
	121	unsigned char irqtype;
	122	unsigned short irqflag;
	123	unsigned char srcbus;
	124	unsigned char srcbusirq;
	125	unsigned char dstapic;
	126	unsigned char dstirq;
1da177e4 LT	127	};
	128
	129	enum mp_irq_source_types {
	130	mp_INT = 0,
	131	mp_NMI = 1,
	132	mp_SMI = 2,
	133	mp_ExtINT = 3
	134	};
	135
	136	#define MP_IRQDIR_DEFAULT 0
	137	#define MP_IRQDIR_HIGH 1
	138	#define MP_IRQDIR_LOW 3
	139
64883ab0	140	#define MP_APIC_ALL 0xFF
1da177e4	141
8fb2952b	142	struct mpc_lintsrc {
b5ced7cd JSR	143	unsigned char type;
	144	unsigned char irqtype;
	145	unsigned short irqflag;
	146	unsigned char srcbusid;
	147	unsigned char srcbusirq;
	148	unsigned char destapic;
	149	unsigned char destapiclint;
1da177e4 LT	150	};
1da177e4 LT	151
64883ab0 TG	152	#define MPC_OEM_SIGNATURE "_OEM"
64883ab0 TG	153
b0e239ff	154	struct mpc_oemtable {
a1d0272a JSR	155	char signature[4];
	156	unsigned short length; /* Size of table */
	157	char rev; /* 0x01 */
	158	char checksum;
	159	char mpc[8];
1da177e4 LT	160	};
1da177e4 LT	161
1da177e4 LT	162	/*
	163	* Default configurations
	164	*
	165	* 1 2 CPU ISA 82489DX
	166	* 2 2 CPU EISA 82489DX neither IRQ 0 timer nor IRQ 13 DMA chaining
	167	* 3 2 CPU EISA 82489DX
	168	* 4 2 CPU MCA 82489DX
	169	* 5 2 CPU ISA+PCI
	170	* 6 2 CPU EISA+PCI
	171	* 7 2 CPU MCA+PCI
	172	*/
	173
	174	enum mp_bustype {
	175	MP_BUS_ISA = 1,
	176	MP_BUS_EISA,
	177	MP_BUS_PCI,
	178	MP_BUS_MCA,
1da177e4	179	};
1965aae3	180	#endif /* _ASM_X86_MPSPEC_DEF_H */