Commit | Line | Data |
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1965aae3 PA |
1 | #ifndef _ASM_X86_MSR_H |
2 | #define _ASM_X86_MSR_H | |
be7baf80 | 3 | |
b72e7464 | 4 | #include "msr-index.h" |
be7baf80 | 5 | |
8f12dea6 | 6 | #ifndef __ASSEMBLY__ |
c210d249 GOC |
7 | |
8 | #include <asm/asm.h> | |
9 | #include <asm/errno.h> | |
6bc1096d | 10 | #include <asm/cpumask.h> |
b72e7464 | 11 | #include <uapi/asm/msr.h> |
6bc1096d BP |
12 | |
13 | struct msr { | |
14 | union { | |
15 | struct { | |
16 | u32 l; | |
17 | u32 h; | |
18 | }; | |
19 | u64 q; | |
20 | }; | |
21 | }; | |
c210d249 | 22 | |
6ede31e0 BP |
23 | struct msr_info { |
24 | u32 msr_no; | |
25 | struct msr reg; | |
26 | struct msr *msrs; | |
27 | int err; | |
28 | }; | |
29 | ||
30 | struct msr_regs_info { | |
31 | u32 *regs; | |
32 | int err; | |
33 | }; | |
34 | ||
1e160cc3 | 35 | static inline unsigned long long native_read_tscp(unsigned int *aux) |
8f12dea6 GOC |
36 | { |
37 | unsigned long low, high; | |
abb0ade0 JP |
38 | asm volatile(".byte 0x0f,0x01,0xf9" |
39 | : "=a" (low), "=d" (high), "=c" (*aux)); | |
41aefdcc | 40 | return low | ((u64)high << 32); |
8f12dea6 GOC |
41 | } |
42 | ||
c210d249 | 43 | /* |
d4f1b103 JS |
44 | * both i386 and x86_64 returns 64-bit value in edx:eax, but gcc's "A" |
45 | * constraint has different meanings. For i386, "A" means exactly | |
46 | * edx:eax, while for x86_64 it doesn't mean rdx:rax or edx:eax. Instead, | |
47 | * it means rax *or* rdx. | |
c210d249 GOC |
48 | */ |
49 | #ifdef CONFIG_X86_64 | |
50 | #define DECLARE_ARGS(val, low, high) unsigned low, high | |
abb0ade0 | 51 | #define EAX_EDX_VAL(val, low, high) ((low) | ((u64)(high) << 32)) |
c210d249 GOC |
52 | #define EAX_EDX_ARGS(val, low, high) "a" (low), "d" (high) |
53 | #define EAX_EDX_RET(val, low, high) "=a" (low), "=d" (high) | |
54 | #else | |
55 | #define DECLARE_ARGS(val, low, high) unsigned long long val | |
56 | #define EAX_EDX_VAL(val, low, high) (val) | |
57 | #define EAX_EDX_ARGS(val, low, high) "A" (val) | |
58 | #define EAX_EDX_RET(val, low, high) "=A" (val) | |
8f12dea6 GOC |
59 | #endif |
60 | ||
be7baf80 TG |
61 | static inline unsigned long long native_read_msr(unsigned int msr) |
62 | { | |
c210d249 | 63 | DECLARE_ARGS(val, low, high); |
be7baf80 | 64 | |
c210d249 GOC |
65 | asm volatile("rdmsr" : EAX_EDX_RET(val, low, high) : "c" (msr)); |
66 | return EAX_EDX_VAL(val, low, high); | |
be7baf80 TG |
67 | } |
68 | ||
69 | static inline unsigned long long native_read_msr_safe(unsigned int msr, | |
70 | int *err) | |
71 | { | |
c210d249 | 72 | DECLARE_ARGS(val, low, high); |
be7baf80 | 73 | |
08970fc4 | 74 | asm volatile("2: rdmsr ; xor %[err],%[err]\n" |
be7baf80 TG |
75 | "1:\n\t" |
76 | ".section .fixup,\"ax\"\n\t" | |
08970fc4 | 77 | "3: mov %[fault],%[err] ; jmp 1b\n\t" |
be7baf80 | 78 | ".previous\n\t" |
abb0ade0 | 79 | _ASM_EXTABLE(2b, 3b) |
08970fc4 | 80 | : [err] "=r" (*err), EAX_EDX_RET(val, low, high) |
0cc0213e | 81 | : "c" (msr), [fault] "i" (-EIO)); |
c210d249 | 82 | return EAX_EDX_VAL(val, low, high); |
be7baf80 TG |
83 | } |
84 | ||
c9dcda5c GOC |
85 | static inline void native_write_msr(unsigned int msr, |
86 | unsigned low, unsigned high) | |
be7baf80 | 87 | { |
af2b1c60 | 88 | asm volatile("wrmsr" : : "c" (msr), "a"(low), "d" (high) : "memory"); |
be7baf80 TG |
89 | } |
90 | ||
0ca59dd9 FW |
91 | /* Can be uninlined because referenced by paravirt */ |
92 | notrace static inline int native_write_msr_safe(unsigned int msr, | |
c9dcda5c | 93 | unsigned low, unsigned high) |
be7baf80 TG |
94 | { |
95 | int err; | |
08970fc4 | 96 | asm volatile("2: wrmsr ; xor %[err],%[err]\n" |
be7baf80 TG |
97 | "1:\n\t" |
98 | ".section .fixup,\"ax\"\n\t" | |
08970fc4 | 99 | "3: mov %[fault],%[err] ; jmp 1b\n\t" |
be7baf80 | 100 | ".previous\n\t" |
abb0ade0 | 101 | _ASM_EXTABLE(2b, 3b) |
08970fc4 | 102 | : [err] "=a" (err) |
c9dcda5c | 103 | : "c" (msr), "0" (low), "d" (high), |
0cc0213e | 104 | [fault] "i" (-EIO) |
af2b1c60 | 105 | : "memory"); |
be7baf80 TG |
106 | return err; |
107 | } | |
108 | ||
1f975f78 AP |
109 | extern int rdmsr_safe_regs(u32 regs[8]); |
110 | extern int wrmsr_safe_regs(u32 regs[8]); | |
132ec92f | 111 | |
c6e5ca35 | 112 | static __always_inline unsigned long long native_read_tsc(void) |
92767af0 IM |
113 | { |
114 | DECLARE_ARGS(val, low, high); | |
115 | ||
92767af0 | 116 | asm volatile("rdtsc" : EAX_EDX_RET(val, low, high)); |
92767af0 IM |
117 | |
118 | return EAX_EDX_VAL(val, low, high); | |
119 | } | |
120 | ||
b8d1fae7 | 121 | static inline unsigned long long native_read_pmc(int counter) |
be7baf80 | 122 | { |
c210d249 GOC |
123 | DECLARE_ARGS(val, low, high); |
124 | ||
125 | asm volatile("rdpmc" : EAX_EDX_RET(val, low, high) : "c" (counter)); | |
126 | return EAX_EDX_VAL(val, low, high); | |
be7baf80 TG |
127 | } |
128 | ||
129 | #ifdef CONFIG_PARAVIRT | |
130 | #include <asm/paravirt.h> | |
96a388de | 131 | #else |
be7baf80 TG |
132 | #include <linux/errno.h> |
133 | /* | |
134 | * Access to machine-specific registers (available on 586 and better only) | |
135 | * Note: the rd* operations modify the parameters directly (without using | |
136 | * pointer indirection), this allows gcc to optimize better | |
137 | */ | |
138 | ||
1423bed2 | 139 | #define rdmsr(msr, low, high) \ |
abb0ade0 JP |
140 | do { \ |
141 | u64 __val = native_read_msr((msr)); \ | |
1423bed2 BP |
142 | (void)((low) = (u32)__val); \ |
143 | (void)((high) = (u32)(__val >> 32)); \ | |
abb0ade0 | 144 | } while (0) |
be7baf80 | 145 | |
c9dcda5c | 146 | static inline void wrmsr(unsigned msr, unsigned low, unsigned high) |
be7baf80 | 147 | { |
c9dcda5c | 148 | native_write_msr(msr, low, high); |
be7baf80 TG |
149 | } |
150 | ||
abb0ade0 JP |
151 | #define rdmsrl(msr, val) \ |
152 | ((val) = native_read_msr((msr))) | |
be7baf80 | 153 | |
c210d249 | 154 | #define wrmsrl(msr, val) \ |
abb0ade0 | 155 | native_write_msr((msr), (u32)((u64)(val)), (u32)((u64)(val) >> 32)) |
be7baf80 TG |
156 | |
157 | /* wrmsr with exception handling */ | |
c9dcda5c | 158 | static inline int wrmsr_safe(unsigned msr, unsigned low, unsigned high) |
be7baf80 | 159 | { |
c9dcda5c | 160 | return native_write_msr_safe(msr, low, high); |
be7baf80 TG |
161 | } |
162 | ||
060feb65 | 163 | /* rdmsr with exception handling */ |
1423bed2 | 164 | #define rdmsr_safe(msr, low, high) \ |
abb0ade0 JP |
165 | ({ \ |
166 | int __err; \ | |
167 | u64 __val = native_read_msr_safe((msr), &__err); \ | |
1423bed2 BP |
168 | (*low) = (u32)__val; \ |
169 | (*high) = (u32)(__val >> 32); \ | |
abb0ade0 JP |
170 | __err; \ |
171 | }) | |
be7baf80 | 172 | |
1de87bd4 AK |
173 | static inline int rdmsrl_safe(unsigned msr, unsigned long long *p) |
174 | { | |
175 | int err; | |
176 | ||
177 | *p = native_read_msr_safe(msr, &err); | |
178 | return err; | |
179 | } | |
177fed1e | 180 | |
abb0ade0 JP |
181 | #define rdpmc(counter, low, high) \ |
182 | do { \ | |
183 | u64 _l = native_read_pmc((counter)); \ | |
184 | (low) = (u32)_l; \ | |
185 | (high) = (u32)(_l >> 32); \ | |
186 | } while (0) | |
be7baf80 | 187 | |
1ff4d58a AK |
188 | #define rdpmcl(counter, val) ((val) = native_read_pmc(counter)) |
189 | ||
9261e050 AL |
190 | #endif /* !CONFIG_PARAVIRT */ |
191 | ||
192 | #define rdtscl(low) \ | |
193 | ((low) = (u32)native_read_tsc()) | |
194 | ||
cf991de2 AL |
195 | /* |
196 | * 64-bit version of wrmsr_safe(): | |
197 | */ | |
198 | static inline int wrmsrl_safe(u32 msr, u64 val) | |
199 | { | |
200 | return wrmsr_safe(msr, (u32)val, (u32)(val >> 32)); | |
201 | } | |
be7baf80 | 202 | |
1423bed2 | 203 | #define write_tsc(low, high) wrmsr(MSR_IA32_TSC, (low), (high)) |
be7baf80 | 204 | |
5df97400 | 205 | #define write_rdtscp_aux(val) wrmsr(MSR_TSC_AUX, (val), 0) |
be7baf80 | 206 | |
50542251 BP |
207 | struct msr *msrs_alloc(void); |
208 | void msrs_free(struct msr *msrs); | |
22085a66 BP |
209 | int msr_set_bit(u32 msr, u8 bit); |
210 | int msr_clear_bit(u32 msr, u8 bit); | |
50542251 | 211 | |
be7baf80 | 212 | #ifdef CONFIG_SMP |
c6f31932 PA |
213 | int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); |
214 | int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); | |
1a6b991a JP |
215 | int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); |
216 | int wrmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 q); | |
b8a47541 BP |
217 | void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs); |
218 | void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs); | |
be7baf80 TG |
219 | int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); |
220 | int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); | |
1a6b991a JP |
221 | int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); |
222 | int wrmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q); | |
8b956bf1 PA |
223 | int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); |
224 | int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); | |
be7baf80 | 225 | #else /* CONFIG_SMP */ |
c6f31932 | 226 | static inline int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h) |
be7baf80 TG |
227 | { |
228 | rdmsr(msr_no, *l, *h); | |
c6f31932 | 229 | return 0; |
be7baf80 | 230 | } |
c6f31932 | 231 | static inline int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) |
be7baf80 TG |
232 | { |
233 | wrmsr(msr_no, l, h); | |
c6f31932 | 234 | return 0; |
be7baf80 | 235 | } |
1a6b991a JP |
236 | static inline int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) |
237 | { | |
238 | rdmsrl(msr_no, *q); | |
239 | return 0; | |
240 | } | |
241 | static inline int wrmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 q) | |
242 | { | |
243 | wrmsrl(msr_no, q); | |
244 | return 0; | |
245 | } | |
0d0fbbdd | 246 | static inline void rdmsr_on_cpus(const struct cpumask *m, u32 msr_no, |
b034c19f BP |
247 | struct msr *msrs) |
248 | { | |
249 | rdmsr_on_cpu(0, msr_no, &(msrs[0].l), &(msrs[0].h)); | |
250 | } | |
0d0fbbdd | 251 | static inline void wrmsr_on_cpus(const struct cpumask *m, u32 msr_no, |
b034c19f BP |
252 | struct msr *msrs) |
253 | { | |
254 | wrmsr_on_cpu(0, msr_no, msrs[0].l, msrs[0].h); | |
255 | } | |
abb0ade0 JP |
256 | static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, |
257 | u32 *l, u32 *h) | |
be7baf80 TG |
258 | { |
259 | return rdmsr_safe(msr_no, l, h); | |
260 | } | |
261 | static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) | |
262 | { | |
263 | return wrmsr_safe(msr_no, l, h); | |
264 | } | |
1a6b991a JP |
265 | static inline int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) |
266 | { | |
267 | return rdmsrl_safe(msr_no, q); | |
268 | } | |
269 | static inline int wrmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q) | |
270 | { | |
271 | return wrmsrl_safe(msr_no, q); | |
272 | } | |
8b956bf1 PA |
273 | static inline int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) |
274 | { | |
275 | return rdmsr_safe_regs(regs); | |
276 | } | |
277 | static inline int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) | |
278 | { | |
279 | return wrmsr_safe_regs(regs); | |
280 | } | |
be7baf80 | 281 | #endif /* CONFIG_SMP */ |
ff55df53 | 282 | #endif /* __ASSEMBLY__ */ |
1965aae3 | 283 | #endif /* _ASM_X86_MSR_H */ |