[deliverable/linux.git] / arch / x86 / include / asm / mwait.h

#ifndef _ASM_X86_MWAIT_H
#define _ASM_X86_MWAIT_H

#include <linux/sched.h>

#define MWAIT_SUBSTATE_MASK		0xf
#define MWAIT_CSTATE_MASK		0xf
#define MWAIT_SUBSTATE_SIZE		4
#define MWAIT_HINT2CSTATE(hint)		(((hint) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK)
#define MWAIT_HINT2SUBSTATE(hint)	((hint) & MWAIT_CSTATE_MASK)

#define CPUID_MWAIT_LEAF		5
#define CPUID5_ECX_EXTENSIONS_SUPPORTED 0x1
#define CPUID5_ECX_INTERRUPT_BREAK	0x2

#define MWAIT_ECX_INTERRUPT_BREAK	0x1

static inline void __monitor(const void *eax, unsigned long ecx,
			     unsigned long edx)
{
	/* "monitor %eax, %ecx, %edx;" */
	asm volatile(".byte 0x0f, 0x01, 0xc8;"
		     :: "a" (eax), "c" (ecx), "d"(edx));
}

static inline void __mwait(unsigned long eax, unsigned long ecx)
{
	/* "mwait %eax, %ecx;" */
	asm volatile(".byte 0x0f, 0x01, 0xc9;"
		     :: "a" (eax), "c" (ecx));
}

static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
{
	trace_hardirqs_on();
	/* "mwait %eax, %ecx;" */
	asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
		     :: "a" (eax), "c" (ecx));
}

/*
 * This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
 * which can obviate IPI to trigger checking of need_resched.
 * We execute MONITOR against need_resched and enter optimized wait state
 * through MWAIT. Whenever someone changes need_resched, we would be woken
 * up from MWAIT (without an IPI).
 *
 * New with Core Duo processors, MWAIT can take some hints based on CPU
 * capability.
 */
static inline void mwait_idle_with_hints(unsigned long eax, unsigned long ecx)
{
	if (!current_set_polling_and_test()) {
		if (static_cpu_has_bug(X86_BUG_CLFLUSH_MONITOR)) {
			mb();
			clflush((void *)&current_thread_info()->flags);
			mb();
		}

		__monitor((void *)&current_thread_info()->flags, 0, 0);
		if (!need_resched())
			__mwait(eax, ecx);
	}
	current_clr_polling();
}

#endif /* _ASM_X86_MWAIT_H */
Commit	Line	Data
bc83cccc PA	1	#ifndef _ASM_X86_MWAIT_H
	2	#define _ASM_X86_MWAIT_H
	3
16824255 PZ	4	#include <linux/sched.h>
16824255 PZ	5
bc83cccc PA	6	#define MWAIT_SUBSTATE_MASK 0xf
	7	#define MWAIT_CSTATE_MASK 0xf
	8	#define MWAIT_SUBSTATE_SIZE 4
e022e7eb LB	9	#define MWAIT_HINT2CSTATE(hint) (((hint) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK)
e022e7eb LB	10	#define MWAIT_HINT2SUBSTATE(hint) ((hint) & MWAIT_CSTATE_MASK)
bc83cccc PA	11
	12	#define CPUID_MWAIT_LEAF 5
	13	#define CPUID5_ECX_EXTENSIONS_SUPPORTED 0x1
	14	#define CPUID5_ECX_INTERRUPT_BREAK 0x2
	15
	16	#define MWAIT_ECX_INTERRUPT_BREAK 0x1
	17
16824255 PZ	18	static inline void __monitor(const void *eax, unsigned long ecx,
	19	unsigned long edx)
	20	{
	21	/* "monitor %eax, %ecx, %edx;" */
	22	asm volatile(".byte 0x0f, 0x01, 0xc8;"
	23	:: "a" (eax), "c" (ecx), "d"(edx));
	24	}
	25
	26	static inline void __mwait(unsigned long eax, unsigned long ecx)
	27	{
	28	/* "mwait %eax, %ecx;" */
	29	asm volatile(".byte 0x0f, 0x01, 0xc9;"
	30	:: "a" (eax), "c" (ecx));
	31	}
	32
b253149b LB	33	static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
	34	{
	35	trace_hardirqs_on();
	36	/* "mwait %eax, %ecx;" */
	37	asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
	38	:: "a" (eax), "c" (ecx));
	39	}
	40
16824255 PZ	41	/*
	42	* This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
	43	* which can obviate IPI to trigger checking of need_resched.
	44	* We execute MONITOR against need_resched and enter optimized wait state
	45	* through MWAIT. Whenever someone changes need_resched, we would be woken
	46	* up from MWAIT (without an IPI).
	47	*
	48	* New with Core Duo processors, MWAIT can take some hints based on CPU
	49	* capability.
	50	*/
	51	static inline void mwait_idle_with_hints(unsigned long eax, unsigned long ecx)
	52	{
	53	if (!current_set_polling_and_test()) {
9b13a93d	54	if (static_cpu_has_bug(X86_BUG_CLFLUSH_MONITOR)) {
7e98b719	55	mb();
16824255	56	clflush((void *)&current_thread_info()->flags);
7e98b719 PA	57	mb();
7e98b719 PA	58	}
16824255 PZ	59
	60	__monitor((void *)&current_thread_info()->flags, 0, 0);
	61	if (!need_resched())
	62	__mwait(eax, ecx);
	63	}
8cb75e0c	64	current_clr_polling();
16824255 PZ	65	}
16824255 PZ	66
bc83cccc	67	#endif /* _ASM_X86_MWAIT_H */