[deliverable/linux.git] / arch / x86 / include / asm / numaq / apic.h

#ifndef __ASM_NUMAQ_APIC_H
#define __ASM_NUMAQ_APIC_H

#include <asm/io.h>
#include <linux/mmzone.h>
#include <linux/nodemask.h>

#define APIC_DFR_VALUE	(APIC_DFR_CLUSTER)

static inline const cpumask_t *numaq_target_cpus(void)
{
	return &CPU_MASK_ALL;
}

static inline unsigned long
numaq_check_apicid_used(physid_mask_t bitmap, int apicid)
{
	return physid_isset(apicid, bitmap);
}
static inline unsigned long numaq_check_apicid_present(int bit)
{
	return physid_isset(bit, phys_cpu_present_map);
}
#define apicid_cluster(apicid) (apicid & 0xF0)

static inline int numaq_apic_id_registered(void)
{
	return 1;
}

static inline void numaq_init_apic_ldr(void)
{
	/* Already done in NUMA-Q firmware */
}

static inline void setup_apic_routing(void)
{
	printk("Enabling APIC mode:  %s.  Using %d I/O APICs\n",
		"NUMA-Q", nr_ioapics);
}

/*
 * Skip adding the timer int on secondary nodes, which causes
 * a small but painful rift in the time-space continuum.
 */
static inline int multi_timer_check(int apic, int irq)
{
	return apic != 0 && irq == 0;
}

static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_map)
{
	/* We don't have a good way to do this yet - hack */
	return physids_promote(0xFUL);
}

/* Mapping from cpu number to logical apicid */
extern u8 cpu_2_logical_apicid[];
static inline int cpu_to_logical_apicid(int cpu)
{
	if (cpu >= nr_cpu_ids)
		return BAD_APICID;
	return (int)cpu_2_logical_apicid[cpu];
}

/*
 * Supporting over 60 cpus on NUMA-Q requires a locality-dependent
 * cpu to APIC ID relation to properly interact with the intelligent
 * mode of the cluster controller.
 */
static inline int cpu_present_to_apicid(int mps_cpu)
{
	if (mps_cpu < 60)
		return ((mps_cpu >> 2) << 4) | (1 << (mps_cpu & 0x3));
	else
		return BAD_APICID;
}

static inline int apicid_to_node(int logical_apicid) 
{
	return logical_apicid >> 4;
}

static inline physid_mask_t apicid_to_cpu_present(int logical_apicid)
{
	int node = apicid_to_node(logical_apicid);
	int cpu = __ffs(logical_apicid & 0xf);

	return physid_mask_of_physid(cpu + 4*node);
}

extern void *xquad_portio;

static inline void setup_portio_remap(void)
{
	int num_quads = num_online_nodes();

	if (num_quads <= 1)
       		return;

	printk("Remapping cross-quad port I/O for %d quads\n", num_quads);
	xquad_portio = ioremap(XQUAD_PORTIO_BASE, num_quads*XQUAD_PORTIO_QUAD);
	printk("xquad_portio vaddr 0x%08lx, len %08lx\n",
		(u_long) xquad_portio, (u_long) num_quads*XQUAD_PORTIO_QUAD);
}

static inline int check_phys_apicid_present(int boot_cpu_physical_apicid)
{
	return (1);
}

static inline void enable_apic_mode(void)
{
}

/*
 * We use physical apicids here, not logical, so just return the default
 * physical broadcast to stop people from breaking us
 */
static inline unsigned int cpu_mask_to_apicid(const cpumask_t *cpumask)
{
	return (int) 0xF;
}

static inline unsigned int cpu_mask_to_apicid_and(const struct cpumask *cpumask,
						  const struct cpumask *andmask)
{
	return (int) 0xF;
}

/* No NUMA-Q box has a HT CPU, but it can't hurt to use the default code. */
static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
{
	return cpuid_apic >> index_msb;
}

#endif /* __ASM_NUMAQ_APIC_H */
Commit	Line	Data
edb181ac YL	1	#ifndef __ASM_NUMAQ_APIC_H
edb181ac YL	2	#define __ASM_NUMAQ_APIC_H
1da177e4 LT	3
	4	#include <asm/io.h>
	5	#include <linux/mmzone.h>
	6	#include <linux/nodemask.h>
	7
	8	#define APIC_DFR_VALUE (APIC_DFR_CLUSTER)
	9
0a9cc20b	10	static inline const cpumask_t *numaq_target_cpus(void)
1da177e4	11	{
e7986739	12	return &CPU_MASK_ALL;
1da177e4 LT	13	}
1da177e4 LT	14
d1d7cae8 IM	15	static inline unsigned long
d1d7cae8 IM	16	numaq_check_apicid_used(physid_mask_t bitmap, int apicid)
d49c4288 YL	17	{
	18	return physid_isset(apicid, bitmap);
	19	}
d1d7cae8	20	static inline unsigned long numaq_check_apicid_present(int bit)
d49c4288 YL	21	{
	22	return physid_isset(bit, phys_cpu_present_map);
	23	}
1da177e4 LT	24	#define apicid_cluster(apicid) (apicid & 0xF0)
1da177e4 LT	25
7ed248da	26	static inline int numaq_apic_id_registered(void)
1da177e4 LT	27	{
	28	return 1;
	29	}
	30
a5c43296	31	static inline void numaq_init_apic_ldr(void)
1da177e4 LT	32	{
	33	/* Already done in NUMA-Q firmware */
	34	}
	35
3c43f039	36	static inline void setup_apic_routing(void)
1da177e4 LT	37	{
	38	printk("Enabling APIC mode: %s. Using %d I/O APICs\n",
	39	"NUMA-Q", nr_ioapics);
	40	}
	41
	42	/*
	43	* Skip adding the timer int on secondary nodes, which causes
	44	* a small but painful rift in the time-space continuum.
	45	*/
	46	static inline int multi_timer_check(int apic, int irq)
	47	{
	48	return apic != 0 && irq == 0;
	49	}
	50
	51	static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_map)
	52	{
	53	/* We don't have a good way to do this yet - hack */
	54	return physids_promote(0xFUL);
	55	}
	56
	57	/* Mapping from cpu number to logical apicid */
	58	extern u8 cpu_2_logical_apicid[];
	59	static inline int cpu_to_logical_apicid(int cpu)
	60	{
9628937d MT	61	if (cpu >= nr_cpu_ids)
9628937d MT	62	return BAD_APICID;
1da177e4 LT	63	return (int)cpu_2_logical_apicid[cpu];
	64	}
	65
	66	/*
	67	* Supporting over 60 cpus on NUMA-Q requires a locality-dependent
	68	* cpu to APIC ID relation to properly interact with the intelligent
	69	* mode of the cluster controller.
	70	*/
	71	static inline int cpu_present_to_apicid(int mps_cpu)
	72	{
	73	if (mps_cpu < 60)
	74	return ((mps_cpu >> 2) << 4) \| (1 << (mps_cpu & 0x3));
	75	else
	76	return BAD_APICID;
	77	}
	78
1da177e4 LT	79	static inline int apicid_to_node(int logical_apicid)
	80	{
	81	return logical_apicid >> 4;
	82	}
	83
	84	static inline physid_mask_t apicid_to_cpu_present(int logical_apicid)
	85	{
	86	int node = apicid_to_node(logical_apicid);
	87	int cpu = __ffs(logical_apicid & 0xf);
	88
	89	return physid_mask_of_physid(cpu + 4*node);
	90	}
	91
c7e844f0 AK	92	extern void *xquad_portio;
c7e844f0 AK	93
1da177e4 LT	94	static inline void setup_portio_remap(void)
	95	{
	96	int num_quads = num_online_nodes();
	97
	98	if (num_quads <= 1)
	99	return;
	100
	101	printk("Remapping cross-quad port I/O for %d quads\n", num_quads);
	102	xquad_portio = ioremap(XQUAD_PORTIO_BASE, num_quads*XQUAD_PORTIO_QUAD);
	103	printk("xquad_portio vaddr 0x%08lx, len %08lx\n",
	104	(u_long) xquad_portio, (u_long) num_quads*XQUAD_PORTIO_QUAD);
	105	}
	106
	107	static inline int check_phys_apicid_present(int boot_cpu_physical_apicid)
	108	{
	109	return (1);
	110	}
	111
	112	static inline void enable_apic_mode(void)
	113	{
	114	}
	115
	116	/*
	117	* We use physical apicids here, not logical, so just return the default
	118	* physical broadcast to stop people from breaking us
	119	*/
e7986739	120	static inline unsigned int cpu_mask_to_apicid(const cpumask_t *cpumask)
1da177e4 LT	121	{
	122	return (int) 0xF;
	123	}
	124
6eeb7c5a MT	125	static inline unsigned int cpu_mask_to_apicid_and(const struct cpumask *cpumask,
6eeb7c5a MT	126	const struct cpumask *andmask)
95d313cf MT	127	{
	128	return (int) 0xF;
	129	}
	130
1da177e4 LT	131	/* No NUMA-Q box has a HT CPU, but it can't hurt to use the default code. */
	132	static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
	133	{
	134	return cpuid_apic >> index_msb;
	135	}
	136
edb181ac	137	#endif /* __ASM_NUMAQ_APIC_H */