Merge branch 'regmap-linus' into regmap-next
[deliverable/linux.git] / arch / x86 / include / asm / pci_x86.h
CommitLineData
1da177e4
LT
1/*
2 * Low-Level PCI Access for i386 machines.
3 *
4 * (c) 1999 Martin Mares <mj@ucw.cz>
5 */
6
7#undef DEBUG
8
9#ifdef DEBUG
10#define DBG(x...) printk(x)
11#else
12#define DBG(x...)
13#endif
14
15#define PCI_PROBE_BIOS 0x0001
16#define PCI_PROBE_CONF1 0x0002
17#define PCI_PROBE_CONF2 0x0004
18#define PCI_PROBE_MMCONF 0x0008
79e453d4 19#define PCI_PROBE_MASK 0x000f
0637a70a 20#define PCI_PROBE_NOEARLY 0x0010
1da177e4 21
1da177e4
LT
22#define PCI_NO_CHECKS 0x0400
23#define PCI_USE_PIRQ_MASK 0x0800
24#define PCI_ASSIGN_ROMS 0x1000
25#define PCI_BIOS_IRQ_SCAN 0x2000
26#define PCI_ASSIGN_ALL_BUSSES 0x4000
036fff4c 27#define PCI_CAN_SKIP_ISA_ALIGN 0x8000
236e946b 28#define PCI_USE__CRS 0x10000
5f0b2976 29#define PCI_CHECK_ENABLE_AMD_MMCONF 0x20000
3a27dd1c 30#define PCI_HAS_IO_ECS 0x40000
dc7c65db 31#define PCI_NOASSIGN_ROMS 0x80000
7bc5e3f2 32#define PCI_ROOT_NO_CRS 0x100000
7bd1c365 33#define PCI_NOASSIGN_BARS 0x200000
1da177e4
LT
34
35extern unsigned int pci_probe;
120bb424 36extern unsigned long pirq_table_addr;
1da177e4 37
6b4b78fe
MD
38enum pci_bf_sort_state {
39 pci_bf_sort_default,
40 pci_force_nobf,
41 pci_force_bf,
42 pci_dmi_bf,
43};
44
1da177e4
LT
45/* pci-i386.c */
46
47extern unsigned int pcibios_max_latency;
48
49void pcibios_resource_survey(void);
44de3395 50void pcibios_set_cache_line_size(void);
1da177e4
LT
51
52/* pci-pc.c */
53
54extern int pcibios_last_bus;
55extern struct pci_bus *pci_root_bus;
56extern struct pci_ops pci_root_ops;
57
5707b24a
AR
58void pcibios_scan_specific_bus(int busn);
59
1da177e4
LT
60/* pci-irq.c */
61
62struct irq_info {
63 u8 bus, devfn; /* Bus, device and function */
64 struct {
82487711
JSR
65 u8 link; /* IRQ line ID, chipset dependent,
66 0 = not routed */
1da177e4
LT
67 u16 bitmap; /* Available IRQs */
68 } __attribute__((packed)) irq[4];
69 u8 slot; /* Slot number, 0=onboard */
70 u8 rfu;
71} __attribute__((packed));
72
73struct irq_routing_table {
74 u32 signature; /* PIRQ_SIGNATURE should be here */
75 u16 version; /* PIRQ_VERSION */
76 u16 size; /* Table size in bytes */
77 u8 rtr_bus, rtr_devfn; /* Where the interrupt router lies */
82487711
JSR
78 u16 exclusive_irqs; /* IRQs devoted exclusively to
79 PCI usage */
80 u16 rtr_vendor, rtr_device; /* Vendor and device ID of
81 interrupt router */
1da177e4
LT
82 u32 miniport_data; /* Crap */
83 u8 rfu[11];
82487711 84 u8 checksum; /* Modulo 256 checksum must give 0 */
1da177e4
LT
85 struct irq_info slots[0];
86} __attribute__((packed));
87
88extern unsigned int pcibios_irq_mask;
89
d19f61f0 90extern raw_spinlock_t pci_config_lock;
1da177e4
LT
91
92extern int (*pcibios_enable_irq)(struct pci_dev *dev);
87bec66b 93extern void (*pcibios_disable_irq)(struct pci_dev *dev);
928cf8c6 94
b6ce068a
MW
95struct pci_raw_ops {
96 int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn,
97 int reg, int len, u32 *val);
98 int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn,
99 int reg, int len, u32 val);
100};
101
102extern struct pci_raw_ops *raw_pci_ops;
103extern struct pci_raw_ops *raw_pci_ext_ops;
104
105extern struct pci_raw_ops pci_direct_conf1;
14d7ca5c 106extern bool port_cf9_safe;
928cf8c6 107
8dd779b1 108/* arch_initcall level */
5e544d61
AK
109extern int pci_direct_probe(void);
110extern void pci_direct_init(int type);
92c05fc1 111extern void pci_pcbios_init(void);
8dd779b1
RR
112extern void __init dmi_check_pciprobe(void);
113extern void __init dmi_check_skip_isa_align(void);
114
115/* some common used subsys_initcalls */
116extern int __init pci_acpi_init(void);
ab3b3793 117extern void __init pcibios_irq_init(void);
8dd779b1 118extern int __init pcibios_init(void);
b72d0db9 119extern int pci_legacy_init(void);
9325a28c 120extern void pcibios_fixup_irqs(void);
5e544d61 121
b7867394
OG
122/* pci-mmconfig.c */
123
56ddf4d3
BH
124/* "PCI MMCONFIG %04x [bus %02x-%02x]" */
125#define PCI_MMCFG_RESOURCE_NAME_LEN (22 + 4 + 2 + 2)
126
d215a9c8 127struct pci_mmcfg_region {
ff097ddd 128 struct list_head list;
56ddf4d3 129 struct resource res;
d215a9c8 130 u64 address;
3f0f5503 131 char __iomem *virt;
d7e6b66f
BH
132 u16 segment;
133 u8 start_bus;
134 u8 end_bus;
56ddf4d3 135 char name[PCI_MMCFG_RESOURCE_NAME_LEN];
d215a9c8
BH
136};
137
429d512e 138extern int __init pci_mmcfg_arch_init(void);
0b64ad71 139extern void __init pci_mmcfg_arch_free(void);
f6e1d8cc 140extern struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus);
3320ad99 141
ff097ddd 142extern struct list_head pci_mmcfg_list;
c4bf2f37 143
df5eb1d6
BH
144#define PCI_MMCFG_BUS_OFFSET(bus) ((bus) << 20)
145
3320ad99 146/*
147 * AMD Fam10h CPUs are buggy, and cannot access MMIO config space
148 * on their northbrige except through the * %eax register. As such, you MUST
149 * NOT use normal IOMEM accesses, you need to only use the magic mmio-config
150 * accessor functions.
151 * In fact just use pci_config_*, nothing else please.
152 */
153static inline unsigned char mmio_config_readb(void __iomem *pos)
154{
155 u8 val;
156 asm volatile("movb (%1),%%al" : "=a" (val) : "r" (pos));
157 return val;
158}
159
160static inline unsigned short mmio_config_readw(void __iomem *pos)
161{
162 u16 val;
163 asm volatile("movw (%1),%%ax" : "=a" (val) : "r" (pos));
164 return val;
165}
166
167static inline unsigned int mmio_config_readl(void __iomem *pos)
168{
169 u32 val;
170 asm volatile("movl (%1),%%eax" : "=a" (val) : "r" (pos));
171 return val;
172}
173
174static inline void mmio_config_writeb(void __iomem *pos, u8 val)
175{
82487711 176 asm volatile("movb %%al,(%1)" : : "a" (val), "r" (pos) : "memory");
3320ad99 177}
178
179static inline void mmio_config_writew(void __iomem *pos, u16 val)
180{
82487711 181 asm volatile("movw %%ax,(%1)" : : "a" (val), "r" (pos) : "memory");
3320ad99 182}
183
184static inline void mmio_config_writel(void __iomem *pos, u32 val)
185{
82487711 186 asm volatile("movl %%eax,(%1)" : : "a" (val), "r" (pos) : "memory");
3320ad99 187}
b72d0db9
TG
188
189#ifdef CONFIG_PCI
190# ifdef CONFIG_ACPI
191# define x86_default_pci_init pci_acpi_init
192# else
193# define x86_default_pci_init pci_legacy_init
194# endif
ab3b3793 195# define x86_default_pci_init_irq pcibios_irq_init
9325a28c 196# define x86_default_pci_fixup_irqs pcibios_fixup_irqs
b72d0db9
TG
197#else
198# define x86_default_pci_init NULL
ab3b3793 199# define x86_default_pci_init_irq NULL
9325a28c 200# define x86_default_pci_fixup_irqs NULL
b72d0db9 201#endif
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