[deliverable/linux.git] / arch / x86 / include / asm / pci_x86.h

/*
 *	Low-Level PCI Access for i386 machines.
 *
 *	(c) 1999 Martin Mares <mj@ucw.cz>
 */

#undef DEBUG

#ifdef DEBUG
#define DBG(x...) printk(x)
#else
#define DBG(x...)
#endif

#define PCI_PROBE_BIOS		0x0001
#define PCI_PROBE_CONF1		0x0002
#define PCI_PROBE_CONF2		0x0004
#define PCI_PROBE_MMCONF	0x0008
#define PCI_PROBE_MASK		0x000f
#define PCI_PROBE_NOEARLY	0x0010

#define PCI_NO_CHECKS		0x0400
#define PCI_USE_PIRQ_MASK	0x0800
#define PCI_ASSIGN_ROMS		0x1000
#define PCI_BIOS_IRQ_SCAN	0x2000
#define PCI_ASSIGN_ALL_BUSSES	0x4000
#define PCI_CAN_SKIP_ISA_ALIGN	0x8000
#define PCI_USE__CRS		0x10000
#define PCI_CHECK_ENABLE_AMD_MMCONF	0x20000
#define PCI_HAS_IO_ECS		0x40000
#define PCI_NOASSIGN_ROMS	0x80000
#define PCI_ROOT_NO_CRS		0x100000
#define PCI_NOASSIGN_BARS	0x200000

extern unsigned int pci_probe;
extern unsigned long pirq_table_addr;

enum pci_bf_sort_state {
	pci_bf_sort_default,
	pci_force_nobf,
	pci_force_bf,
	pci_dmi_bf,
};

/* pci-i386.c */

extern unsigned int pcibios_max_latency;

void pcibios_resource_survey(void);

/* pci-pc.c */

extern int pcibios_last_bus;
extern struct pci_bus *pci_root_bus;
extern struct pci_ops pci_root_ops;

void pcibios_scan_specific_bus(int busn);

/* pci-irq.c */

struct irq_info {
	u8 bus, devfn;			/* Bus, device and function */
	struct {
		u8 link;		/* IRQ line ID, chipset dependent,
					   0 = not routed */
		u16 bitmap;		/* Available IRQs */
	} __attribute__((packed)) irq[4];
	u8 slot;			/* Slot number, 0=onboard */
	u8 rfu;
} __attribute__((packed));

struct irq_routing_table {
	u32 signature;			/* PIRQ_SIGNATURE should be here */
	u16 version;			/* PIRQ_VERSION */
	u16 size;			/* Table size in bytes */
	u8 rtr_bus, rtr_devfn;		/* Where the interrupt router lies */
	u16 exclusive_irqs;		/* IRQs devoted exclusively to
					   PCI usage */
	u16 rtr_vendor, rtr_device;	/* Vendor and device ID of
					   interrupt router */
	u32 miniport_data;		/* Crap */
	u8 rfu[11];
	u8 checksum;			/* Modulo 256 checksum must give 0 */
	struct irq_info slots[0];
} __attribute__((packed));

extern unsigned int pcibios_irq_mask;

extern raw_spinlock_t pci_config_lock;

extern int (*pcibios_enable_irq)(struct pci_dev *dev);
extern void (*pcibios_disable_irq)(struct pci_dev *dev);

struct pci_raw_ops {
	int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn,
						int reg, int len, u32 *val);
	int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn,
						int reg, int len, u32 val);
};

extern struct pci_raw_ops *raw_pci_ops;
extern struct pci_raw_ops *raw_pci_ext_ops;

extern struct pci_raw_ops pci_direct_conf1;
extern bool port_cf9_safe;

/* arch_initcall level */
extern int pci_direct_probe(void);
extern void pci_direct_init(int type);
extern void pci_pcbios_init(void);
extern void __init dmi_check_pciprobe(void);
extern void __init dmi_check_skip_isa_align(void);

/* some common used subsys_initcalls */
extern int __init pci_acpi_init(void);
extern void __init pcibios_irq_init(void);
extern int __init pcibios_init(void);
extern int pci_legacy_init(void);
extern void pcibios_fixup_irqs(void);

/* pci-mmconfig.c */

/* "PCI MMCONFIG %04x [bus %02x-%02x]" */
#define PCI_MMCFG_RESOURCE_NAME_LEN (22 + 4 + 2 + 2)

struct pci_mmcfg_region {
	struct list_head list;
	struct resource res;
	u64 address;
	char __iomem *virt;
	u16 segment;
	u8 start_bus;
	u8 end_bus;
	char name[PCI_MMCFG_RESOURCE_NAME_LEN];
};

extern int __init pci_mmcfg_arch_init(void);
extern void __init pci_mmcfg_arch_free(void);
extern struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus);

extern struct list_head pci_mmcfg_list;

#define PCI_MMCFG_BUS_OFFSET(bus)      ((bus) << 20)

/*
 * AMD Fam10h CPUs are buggy, and cannot access MMIO config space
 * on their northbrige except through the * %eax register. As such, you MUST
 * NOT use normal IOMEM accesses, you need to only use the magic mmio-config
 * accessor functions.
 * In fact just use pci_config_*, nothing else please.
 */
static inline unsigned char mmio_config_readb(void __iomem *pos)
{
	u8 val;
	asm volatile("movb (%1),%%al" : "=a" (val) : "r" (pos));
	return val;
}

static inline unsigned short mmio_config_readw(void __iomem *pos)
{
	u16 val;
	asm volatile("movw (%1),%%ax" : "=a" (val) : "r" (pos));
	return val;
}

static inline unsigned int mmio_config_readl(void __iomem *pos)
{
	u32 val;
	asm volatile("movl (%1),%%eax" : "=a" (val) : "r" (pos));
	return val;
}

static inline void mmio_config_writeb(void __iomem *pos, u8 val)
{
	asm volatile("movb %%al,(%1)" : : "a" (val), "r" (pos) : "memory");
}

static inline void mmio_config_writew(void __iomem *pos, u16 val)
{
	asm volatile("movw %%ax,(%1)" : : "a" (val), "r" (pos) : "memory");
}

static inline void mmio_config_writel(void __iomem *pos, u32 val)
{
	asm volatile("movl %%eax,(%1)" : : "a" (val), "r" (pos) : "memory");
}

#ifdef CONFIG_PCI
# ifdef CONFIG_ACPI
#  define x86_default_pci_init		pci_acpi_init
# else
#  define x86_default_pci_init		pci_legacy_init
# endif
# define x86_default_pci_init_irq	pcibios_irq_init
# define x86_default_pci_fixup_irqs	pcibios_fixup_irqs
#else
# define x86_default_pci_init		NULL
# define x86_default_pci_init_irq	NULL
# define x86_default_pci_fixup_irqs	NULL
#endif
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Low-Level PCI Access for i386 machines.
	3	*
	4	* (c) 1999 Martin Mares <mj@ucw.cz>
	5	*/
	6
	7	#undef DEBUG
	8
	9	#ifdef DEBUG
	10	#define DBG(x...) printk(x)
	11	#else
	12	#define DBG(x...)
	13	#endif
	14
	15	#define PCI_PROBE_BIOS 0x0001
	16	#define PCI_PROBE_CONF1 0x0002
	17	#define PCI_PROBE_CONF2 0x0004
	18	#define PCI_PROBE_MMCONF 0x0008
79e453d4	19	#define PCI_PROBE_MASK 0x000f
0637a70a	20	#define PCI_PROBE_NOEARLY 0x0010
1da177e4	21
1da177e4 LT	22	#define PCI_NO_CHECKS 0x0400
	23	#define PCI_USE_PIRQ_MASK 0x0800
	24	#define PCI_ASSIGN_ROMS 0x1000
	25	#define PCI_BIOS_IRQ_SCAN 0x2000
	26	#define PCI_ASSIGN_ALL_BUSSES 0x4000
036fff4c	27	#define PCI_CAN_SKIP_ISA_ALIGN 0x8000
236e946b	28	#define PCI_USE__CRS 0x10000
5f0b2976	29	#define PCI_CHECK_ENABLE_AMD_MMCONF 0x20000
3a27dd1c	30	#define PCI_HAS_IO_ECS 0x40000
dc7c65db	31	#define PCI_NOASSIGN_ROMS 0x80000
7bc5e3f2	32	#define PCI_ROOT_NO_CRS 0x100000
7bd1c365	33	#define PCI_NOASSIGN_BARS 0x200000
1da177e4 LT	34
1da177e4 LT	35	extern unsigned int pci_probe;
120bb424	36	extern unsigned long pirq_table_addr;
1da177e4	37
6b4b78fe MD	38	enum pci_bf_sort_state {
	39	pci_bf_sort_default,
	40	pci_force_nobf,
	41	pci_force_bf,
	42	pci_dmi_bf,
	43	};
	44
1da177e4 LT	45	/* pci-i386.c */
	46
	47	extern unsigned int pcibios_max_latency;
	48
	49	void pcibios_resource_survey(void);
1da177e4 LT	50
	51	/* pci-pc.c */
	52
	53	extern int pcibios_last_bus;
	54	extern struct pci_bus *pci_root_bus;
	55	extern struct pci_ops pci_root_ops;
	56
5707b24a AR	57	void pcibios_scan_specific_bus(int busn);
5707b24a AR	58
1da177e4 LT	59	/* pci-irq.c */
	60
	61	struct irq_info {
	62	u8 bus, devfn; /* Bus, device and function */
	63	struct {
82487711 JSR	64	u8 link; /* IRQ line ID, chipset dependent,
82487711 JSR	65	0 = not routed */
1da177e4 LT	66	u16 bitmap; /* Available IRQs */
	67	} __attribute__((packed)) irq[4];
	68	u8 slot; /* Slot number, 0=onboard */
	69	u8 rfu;
	70	} __attribute__((packed));
	71
	72	struct irq_routing_table {
	73	u32 signature; /* PIRQ_SIGNATURE should be here */
	74	u16 version; /* PIRQ_VERSION */
	75	u16 size; /* Table size in bytes */
	76	u8 rtr_bus, rtr_devfn; /* Where the interrupt router lies */
82487711 JSR	77	u16 exclusive_irqs; /* IRQs devoted exclusively to
	78	PCI usage */
	79	u16 rtr_vendor, rtr_device; /* Vendor and device ID of
	80	interrupt router */
1da177e4 LT	81	u32 miniport_data; /* Crap */
1da177e4 LT	82	u8 rfu[11];
82487711	83	u8 checksum; /* Modulo 256 checksum must give 0 */
1da177e4 LT	84	struct irq_info slots[0];
	85	} __attribute__((packed));
	86
	87	extern unsigned int pcibios_irq_mask;
	88
d19f61f0	89	extern raw_spinlock_t pci_config_lock;
1da177e4 LT	90
1da177e4 LT	91	extern int (pcibios_enable_irq)(struct pci_dev dev);
87bec66b	92	extern void (pcibios_disable_irq)(struct pci_dev dev);
928cf8c6	93
b6ce068a MW	94	struct pci_raw_ops {
	95	int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn,
	96	int reg, int len, u32 *val);
	97	int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn,
	98	int reg, int len, u32 val);
	99	};
	100
	101	extern struct pci_raw_ops *raw_pci_ops;
	102	extern struct pci_raw_ops *raw_pci_ext_ops;
	103
	104	extern struct pci_raw_ops pci_direct_conf1;
14d7ca5c	105	extern bool port_cf9_safe;
928cf8c6	106
8dd779b1	107	/* arch_initcall level */
5e544d61 AK	108	extern int pci_direct_probe(void);
5e544d61 AK	109	extern void pci_direct_init(int type);
92c05fc1	110	extern void pci_pcbios_init(void);
8dd779b1 RR	111	extern void __init dmi_check_pciprobe(void);
	112	extern void __init dmi_check_skip_isa_align(void);
	113
	114	/* some common used subsys_initcalls */
	115	extern int __init pci_acpi_init(void);
ab3b3793	116	extern void __init pcibios_irq_init(void);
8dd779b1	117	extern int __init pcibios_init(void);
b72d0db9	118	extern int pci_legacy_init(void);
9325a28c	119	extern void pcibios_fixup_irqs(void);
5e544d61	120
b7867394 OG	121	/* pci-mmconfig.c */
b7867394 OG	122
56ddf4d3 BH	123	/* "PCI MMCONFIG %04x [bus %02x-%02x]" */
	124	#define PCI_MMCFG_RESOURCE_NAME_LEN (22 + 4 + 2 + 2)
	125
d215a9c8	126	struct pci_mmcfg_region {
ff097ddd	127	struct list_head list;
56ddf4d3	128	struct resource res;
d215a9c8	129	u64 address;
3f0f5503	130	char __iomem *virt;
d7e6b66f BH	131	u16 segment;
	132	u8 start_bus;
	133	u8 end_bus;
56ddf4d3	134	char name[PCI_MMCFG_RESOURCE_NAME_LEN];
d215a9c8 BH	135	};
d215a9c8 BH	136
429d512e	137	extern int __init pci_mmcfg_arch_init(void);
0b64ad71	138	extern void __init pci_mmcfg_arch_free(void);
f6e1d8cc	139	extern struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus);
3320ad99	140
ff097ddd	141	extern struct list_head pci_mmcfg_list;
c4bf2f37	142
df5eb1d6 BH	143	#define PCI_MMCFG_BUS_OFFSET(bus) ((bus) << 20)
df5eb1d6 BH	144
3320ad99	145	/*
	146	* AMD Fam10h CPUs are buggy, and cannot access MMIO config space
	147	* on their northbrige except through the * %eax register. As such, you MUST
	148	* NOT use normal IOMEM accesses, you need to only use the magic mmio-config
	149	* accessor functions.
	150	* In fact just use pci_config_*, nothing else please.
	151	*/
	152	static inline unsigned char mmio_config_readb(void __iomem *pos)
	153	{
	154	u8 val;
	155	asm volatile("movb (%1),%%al" : "=a" (val) : "r" (pos));
	156	return val;
	157	}
	158
	159	static inline unsigned short mmio_config_readw(void __iomem *pos)
	160	{
	161	u16 val;
	162	asm volatile("movw (%1),%%ax" : "=a" (val) : "r" (pos));
	163	return val;
	164	}
	165
	166	static inline unsigned int mmio_config_readl(void __iomem *pos)
	167	{
	168	u32 val;
	169	asm volatile("movl (%1),%%eax" : "=a" (val) : "r" (pos));
	170	return val;
	171	}
	172
	173	static inline void mmio_config_writeb(void __iomem *pos, u8 val)
	174	{
82487711	175	asm volatile("movb %%al,(%1)" : : "a" (val), "r" (pos) : "memory");
3320ad99	176	}
	177
	178	static inline void mmio_config_writew(void __iomem *pos, u16 val)
	179	{
82487711	180	asm volatile("movw %%ax,(%1)" : : "a" (val), "r" (pos) : "memory");
3320ad99	181	}
	182
	183	static inline void mmio_config_writel(void __iomem *pos, u32 val)
	184	{
82487711	185	asm volatile("movl %%eax,(%1)" : : "a" (val), "r" (pos) : "memory");
3320ad99	186	}
b72d0db9 TG	187
	188	#ifdef CONFIG_PCI
	189	# ifdef CONFIG_ACPI
	190	# define x86_default_pci_init pci_acpi_init
	191	# else
	192	# define x86_default_pci_init pci_legacy_init
	193	# endif
ab3b3793	194	# define x86_default_pci_init_irq pcibios_irq_init
9325a28c	195	# define x86_default_pci_fixup_irqs pcibios_fixup_irqs
b72d0db9 TG	196	#else
b72d0db9 TG	197	# define x86_default_pci_init NULL
ab3b3793	198	# define x86_default_pci_init_irq NULL
9325a28c	199	# define x86_default_pci_fixup_irqs NULL
b72d0db9	200	#endif