[deliverable/linux.git] / arch / x86 / include / asm / pci_x86.h

/*
 *	Low-Level PCI Access for i386 machines.
 *
 *	(c) 1999 Martin Mares <mj@ucw.cz>
 */

#undef DEBUG

#ifdef DEBUG
#define DBG(x...) printk(x)
#else
#define DBG(x...)
#endif

#define PCI_PROBE_BIOS		0x0001
#define PCI_PROBE_CONF1		0x0002
#define PCI_PROBE_CONF2		0x0004
#define PCI_PROBE_MMCONF	0x0008
#define PCI_PROBE_MASK		0x000f
#define PCI_PROBE_NOEARLY	0x0010

#define PCI_NO_CHECKS		0x0400
#define PCI_USE_PIRQ_MASK	0x0800
#define PCI_ASSIGN_ROMS		0x1000
#define PCI_BIOS_IRQ_SCAN	0x2000
#define PCI_ASSIGN_ALL_BUSSES	0x4000
#define PCI_CAN_SKIP_ISA_ALIGN	0x8000
#define PCI_USE__CRS		0x10000
#define PCI_CHECK_ENABLE_AMD_MMCONF	0x20000
#define PCI_HAS_IO_ECS		0x40000
#define PCI_NOASSIGN_ROMS	0x80000
#define PCI_ROOT_NO_CRS		0x100000

extern unsigned int pci_probe;
extern unsigned long pirq_table_addr;

enum pci_bf_sort_state {
	pci_bf_sort_default,
	pci_force_nobf,
	pci_force_bf,
	pci_dmi_bf,
};

/* pci-i386.c */

extern unsigned int pcibios_max_latency;

void pcibios_resource_survey(void);

/* pci-pc.c */

extern int pcibios_last_bus;
extern struct pci_bus *pci_root_bus;
extern struct pci_ops pci_root_ops;

/* pci-irq.c */

struct irq_info {
	u8 bus, devfn;			/* Bus, device and function */
	struct {
		u8 link;		/* IRQ line ID, chipset dependent,
					   0 = not routed */
		u16 bitmap;		/* Available IRQs */
	} __attribute__((packed)) irq[4];
	u8 slot;			/* Slot number, 0=onboard */
	u8 rfu;
} __attribute__((packed));

struct irq_routing_table {
	u32 signature;			/* PIRQ_SIGNATURE should be here */
	u16 version;			/* PIRQ_VERSION */
	u16 size;			/* Table size in bytes */
	u8 rtr_bus, rtr_devfn;		/* Where the interrupt router lies */
	u16 exclusive_irqs;		/* IRQs devoted exclusively to
					   PCI usage */
	u16 rtr_vendor, rtr_device;	/* Vendor and device ID of
					   interrupt router */
	u32 miniport_data;		/* Crap */
	u8 rfu[11];
	u8 checksum;			/* Modulo 256 checksum must give 0 */
	struct irq_info slots[0];
} __attribute__((packed));

extern unsigned int pcibios_irq_mask;

extern spinlock_t pci_config_lock;

extern int (*pcibios_enable_irq)(struct pci_dev *dev);
extern void (*pcibios_disable_irq)(struct pci_dev *dev);

struct pci_raw_ops {
	int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn,
						int reg, int len, u32 *val);
	int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn,
						int reg, int len, u32 val);
};

extern struct pci_raw_ops *raw_pci_ops;
extern struct pci_raw_ops *raw_pci_ext_ops;

extern struct pci_raw_ops pci_direct_conf1;
extern bool port_cf9_safe;

/* arch_initcall level */
extern int pci_direct_probe(void);
extern void pci_direct_init(int type);
extern void pci_pcbios_init(void);
extern void __init dmi_check_pciprobe(void);
extern void __init dmi_check_skip_isa_align(void);

/* some common used subsys_initcalls */
extern int __init pci_acpi_init(void);
extern void __init pcibios_irq_init(void);
extern int __init pcibios_init(void);
extern int pci_legacy_init(void);
extern void pcibios_fixup_irqs(void);

/* pci-mmconfig.c */

/* "PCI MMCONFIG %04x [bus %02x-%02x]" */
#define PCI_MMCFG_RESOURCE_NAME_LEN (22 + 4 + 2 + 2)

struct pci_mmcfg_region {
	struct list_head list;
	struct resource res;
	u64 address;
	char __iomem *virt;
	u16 segment;
	u8 start_bus;
	u8 end_bus;
	char name[PCI_MMCFG_RESOURCE_NAME_LEN];
};

extern int __init pci_mmcfg_arch_init(void);
extern void __init pci_mmcfg_arch_free(void);
extern struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus);

extern struct list_head pci_mmcfg_list;

#define PCI_MMCFG_BUS_OFFSET(bus)      ((bus) << 20)

/*
 * AMD Fam10h CPUs are buggy, and cannot access MMIO config space
 * on their northbrige except through the * %eax register. As such, you MUST
 * NOT use normal IOMEM accesses, you need to only use the magic mmio-config
 * accessor functions.
 * In fact just use pci_config_*, nothing else please.
 */
static inline unsigned char mmio_config_readb(void __iomem *pos)
{
	u8 val;
	asm volatile("movb (%1),%%al" : "=a" (val) : "r" (pos));
	return val;
}

static inline unsigned short mmio_config_readw(void __iomem *pos)
{
	u16 val;
	asm volatile("movw (%1),%%ax" : "=a" (val) : "r" (pos));
	return val;
}

static inline unsigned int mmio_config_readl(void __iomem *pos)
{
	u32 val;
	asm volatile("movl (%1),%%eax" : "=a" (val) : "r" (pos));
	return val;
}

static inline void mmio_config_writeb(void __iomem *pos, u8 val)
{
	asm volatile("movb %%al,(%1)" : : "a" (val), "r" (pos) : "memory");
}

static inline void mmio_config_writew(void __iomem *pos, u16 val)
{
	asm volatile("movw %%ax,(%1)" : : "a" (val), "r" (pos) : "memory");
}

static inline void mmio_config_writel(void __iomem *pos, u32 val)
{
	asm volatile("movl %%eax,(%1)" : : "a" (val), "r" (pos) : "memory");
}

#ifdef CONFIG_PCI
# ifdef CONFIG_ACPI
#  define x86_default_pci_init		pci_acpi_init
# else
#  define x86_default_pci_init		pci_legacy_init
# endif
# define x86_default_pci_init_irq	pcibios_irq_init
# define x86_default_pci_fixup_irqs	pcibios_fixup_irqs
#else
# define x86_default_pci_init		NULL
# define x86_default_pci_init_irq	NULL
# define x86_default_pci_fixup_irqs	NULL
#endif
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Low-Level PCI Access for i386 machines.
	3	*
	4	* (c) 1999 Martin Mares <mj@ucw.cz>
	5	*/
	6
	7	#undef DEBUG
	8
	9	#ifdef DEBUG
	10	#define DBG(x...) printk(x)
	11	#else
	12	#define DBG(x...)
	13	#endif
	14
	15	#define PCI_PROBE_BIOS 0x0001
	16	#define PCI_PROBE_CONF1 0x0002
	17	#define PCI_PROBE_CONF2 0x0004
	18	#define PCI_PROBE_MMCONF 0x0008
79e453d4	19	#define PCI_PROBE_MASK 0x000f
0637a70a	20	#define PCI_PROBE_NOEARLY 0x0010
1da177e4	21
1da177e4 LT	22	#define PCI_NO_CHECKS 0x0400
	23	#define PCI_USE_PIRQ_MASK 0x0800
	24	#define PCI_ASSIGN_ROMS 0x1000
	25	#define PCI_BIOS_IRQ_SCAN 0x2000
	26	#define PCI_ASSIGN_ALL_BUSSES 0x4000
036fff4c	27	#define PCI_CAN_SKIP_ISA_ALIGN 0x8000
236e946b	28	#define PCI_USE__CRS 0x10000
5f0b2976	29	#define PCI_CHECK_ENABLE_AMD_MMCONF 0x20000
3a27dd1c	30	#define PCI_HAS_IO_ECS 0x40000
dc7c65db	31	#define PCI_NOASSIGN_ROMS 0x80000
7bc5e3f2	32	#define PCI_ROOT_NO_CRS 0x100000
1da177e4 LT	33
1da177e4 LT	34	extern unsigned int pci_probe;
120bb424	35	extern unsigned long pirq_table_addr;
1da177e4	36
6b4b78fe MD	37	enum pci_bf_sort_state {
	38	pci_bf_sort_default,
	39	pci_force_nobf,
	40	pci_force_bf,
	41	pci_dmi_bf,
	42	};
	43
1da177e4 LT	44	/* pci-i386.c */
	45
	46	extern unsigned int pcibios_max_latency;
	47
	48	void pcibios_resource_survey(void);
1da177e4 LT	49
	50	/* pci-pc.c */
	51
	52	extern int pcibios_last_bus;
	53	extern struct pci_bus *pci_root_bus;
	54	extern struct pci_ops pci_root_ops;
	55
	56	/* pci-irq.c */
	57
	58	struct irq_info {
	59	u8 bus, devfn; /* Bus, device and function */
	60	struct {
82487711 JSR	61	u8 link; /* IRQ line ID, chipset dependent,
82487711 JSR	62	0 = not routed */
1da177e4 LT	63	u16 bitmap; /* Available IRQs */
	64	} __attribute__((packed)) irq[4];
	65	u8 slot; /* Slot number, 0=onboard */
	66	u8 rfu;
	67	} __attribute__((packed));
	68
	69	struct irq_routing_table {
	70	u32 signature; /* PIRQ_SIGNATURE should be here */
	71	u16 version; /* PIRQ_VERSION */
	72	u16 size; /* Table size in bytes */
	73	u8 rtr_bus, rtr_devfn; /* Where the interrupt router lies */
82487711 JSR	74	u16 exclusive_irqs; /* IRQs devoted exclusively to
	75	PCI usage */
	76	u16 rtr_vendor, rtr_device; /* Vendor and device ID of
	77	interrupt router */
1da177e4 LT	78	u32 miniport_data; /* Crap */
1da177e4 LT	79	u8 rfu[11];
82487711	80	u8 checksum; /* Modulo 256 checksum must give 0 */
1da177e4 LT	81	struct irq_info slots[0];
	82	} __attribute__((packed));
	83
	84	extern unsigned int pcibios_irq_mask;
	85
1da177e4 LT	86	extern spinlock_t pci_config_lock;
	87
	88	extern int (pcibios_enable_irq)(struct pci_dev dev);
87bec66b	89	extern void (pcibios_disable_irq)(struct pci_dev dev);
928cf8c6	90
b6ce068a MW	91	struct pci_raw_ops {
	92	int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn,
	93	int reg, int len, u32 *val);
	94	int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn,
	95	int reg, int len, u32 val);
	96	};
	97
	98	extern struct pci_raw_ops *raw_pci_ops;
	99	extern struct pci_raw_ops *raw_pci_ext_ops;
	100
	101	extern struct pci_raw_ops pci_direct_conf1;
14d7ca5c	102	extern bool port_cf9_safe;
928cf8c6	103
8dd779b1	104	/* arch_initcall level */
5e544d61 AK	105	extern int pci_direct_probe(void);
5e544d61 AK	106	extern void pci_direct_init(int type);
92c05fc1	107	extern void pci_pcbios_init(void);
8dd779b1 RR	108	extern void __init dmi_check_pciprobe(void);
	109	extern void __init dmi_check_skip_isa_align(void);
	110
	111	/* some common used subsys_initcalls */
	112	extern int __init pci_acpi_init(void);
ab3b3793	113	extern void __init pcibios_irq_init(void);
8dd779b1	114	extern int __init pcibios_init(void);
b72d0db9	115	extern int pci_legacy_init(void);
9325a28c	116	extern void pcibios_fixup_irqs(void);
5e544d61	117
b7867394 OG	118	/* pci-mmconfig.c */
b7867394 OG	119
56ddf4d3 BH	120	/* "PCI MMCONFIG %04x [bus %02x-%02x]" */
	121	#define PCI_MMCFG_RESOURCE_NAME_LEN (22 + 4 + 2 + 2)
	122
d215a9c8	123	struct pci_mmcfg_region {
ff097ddd	124	struct list_head list;
56ddf4d3	125	struct resource res;
d215a9c8	126	u64 address;
3f0f5503	127	char __iomem *virt;
d7e6b66f BH	128	u16 segment;
	129	u8 start_bus;
	130	u8 end_bus;
56ddf4d3	131	char name[PCI_MMCFG_RESOURCE_NAME_LEN];
d215a9c8 BH	132	};
d215a9c8 BH	133
429d512e	134	extern int __init pci_mmcfg_arch_init(void);
0b64ad71	135	extern void __init pci_mmcfg_arch_free(void);
f6e1d8cc	136	extern struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus);
3320ad99	137
ff097ddd	138	extern struct list_head pci_mmcfg_list;
c4bf2f37	139
df5eb1d6 BH	140	#define PCI_MMCFG_BUS_OFFSET(bus) ((bus) << 20)
df5eb1d6 BH	141
3320ad99	142	/*
	143	* AMD Fam10h CPUs are buggy, and cannot access MMIO config space
	144	* on their northbrige except through the * %eax register. As such, you MUST
	145	* NOT use normal IOMEM accesses, you need to only use the magic mmio-config
	146	* accessor functions.
	147	* In fact just use pci_config_*, nothing else please.
	148	*/
	149	static inline unsigned char mmio_config_readb(void __iomem *pos)
	150	{
	151	u8 val;
	152	asm volatile("movb (%1),%%al" : "=a" (val) : "r" (pos));
	153	return val;
	154	}
	155
	156	static inline unsigned short mmio_config_readw(void __iomem *pos)
	157	{
	158	u16 val;
	159	asm volatile("movw (%1),%%ax" : "=a" (val) : "r" (pos));
	160	return val;
	161	}
	162
	163	static inline unsigned int mmio_config_readl(void __iomem *pos)
	164	{
	165	u32 val;
	166	asm volatile("movl (%1),%%eax" : "=a" (val) : "r" (pos));
	167	return val;
	168	}
	169
	170	static inline void mmio_config_writeb(void __iomem *pos, u8 val)
	171	{
82487711	172	asm volatile("movb %%al,(%1)" : : "a" (val), "r" (pos) : "memory");
3320ad99	173	}
	174
	175	static inline void mmio_config_writew(void __iomem *pos, u16 val)
	176	{
82487711	177	asm volatile("movw %%ax,(%1)" : : "a" (val), "r" (pos) : "memory");
3320ad99	178	}
	179
	180	static inline void mmio_config_writel(void __iomem *pos, u32 val)
	181	{
82487711	182	asm volatile("movl %%eax,(%1)" : : "a" (val), "r" (pos) : "memory");
3320ad99	183	}
b72d0db9 TG	184
	185	#ifdef CONFIG_PCI
	186	# ifdef CONFIG_ACPI
	187	# define x86_default_pci_init pci_acpi_init
	188	# else
	189	# define x86_default_pci_init pci_legacy_init
	190	# endif
ab3b3793	191	# define x86_default_pci_init_irq pcibios_irq_init
9325a28c	192	# define x86_default_pci_fixup_irqs pcibios_fixup_irqs
b72d0db9 TG	193	#else
b72d0db9 TG	194	# define x86_default_pci_init NULL
ab3b3793	195	# define x86_default_pci_init_irq NULL
9325a28c	196	# define x86_default_pci_fixup_irqs NULL
b72d0db9	197	#endif