[deliverable/linux.git] / arch / x86 / include / asm / perf_event.h

#ifndef _ASM_X86_PERF_EVENT_H
#define _ASM_X86_PERF_EVENT_H

/*
 * Performance event hw details:
 */

#define INTEL_PMC_MAX_GENERIC				       32
#define INTEL_PMC_MAX_FIXED					3
#define INTEL_PMC_IDX_FIXED				       32

#define X86_PMC_IDX_MAX					       64

#define MSR_ARCH_PERFMON_PERFCTR0			      0xc1
#define MSR_ARCH_PERFMON_PERFCTR1			      0xc2

#define MSR_ARCH_PERFMON_EVENTSEL0			     0x186
#define MSR_ARCH_PERFMON_EVENTSEL1			     0x187

#define ARCH_PERFMON_EVENTSEL_EVENT			0x000000FFULL
#define ARCH_PERFMON_EVENTSEL_UMASK			0x0000FF00ULL
#define ARCH_PERFMON_EVENTSEL_USR			(1ULL << 16)
#define ARCH_PERFMON_EVENTSEL_OS			(1ULL << 17)
#define ARCH_PERFMON_EVENTSEL_EDGE			(1ULL << 18)
#define ARCH_PERFMON_EVENTSEL_PIN_CONTROL		(1ULL << 19)
#define ARCH_PERFMON_EVENTSEL_INT			(1ULL << 20)
#define ARCH_PERFMON_EVENTSEL_ANY			(1ULL << 21)
#define ARCH_PERFMON_EVENTSEL_ENABLE			(1ULL << 22)
#define ARCH_PERFMON_EVENTSEL_INV			(1ULL << 23)
#define ARCH_PERFMON_EVENTSEL_CMASK			0xFF000000ULL

#define AMD64_EVENTSEL_INT_CORE_ENABLE			(1ULL << 36)
#define AMD64_EVENTSEL_GUESTONLY			(1ULL << 40)
#define AMD64_EVENTSEL_HOSTONLY				(1ULL << 41)

#define AMD64_EVENTSEL_INT_CORE_SEL_SHIFT		37
#define AMD64_EVENTSEL_INT_CORE_SEL_MASK		\
	(0xFULL << AMD64_EVENTSEL_INT_CORE_SEL_SHIFT)

#define AMD64_EVENTSEL_EVENT	\
	(ARCH_PERFMON_EVENTSEL_EVENT | (0x0FULL << 32))
#define INTEL_ARCH_EVENT_MASK	\
	(ARCH_PERFMON_EVENTSEL_UMASK | ARCH_PERFMON_EVENTSEL_EVENT)

#define X86_RAW_EVENT_MASK		\
	(ARCH_PERFMON_EVENTSEL_EVENT |	\
	 ARCH_PERFMON_EVENTSEL_UMASK |	\
	 ARCH_PERFMON_EVENTSEL_EDGE  |	\
	 ARCH_PERFMON_EVENTSEL_INV   |	\
	 ARCH_PERFMON_EVENTSEL_CMASK)
#define AMD64_RAW_EVENT_MASK		\
	(X86_RAW_EVENT_MASK          |  \
	 AMD64_EVENTSEL_EVENT)
#define AMD64_RAW_EVENT_MASK_NB		\
	(AMD64_EVENTSEL_EVENT        |  \
	 ARCH_PERFMON_EVENTSEL_UMASK)
#define AMD64_NUM_COUNTERS				4
#define AMD64_NUM_COUNTERS_CORE				6
#define AMD64_NUM_COUNTERS_NB				4

#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL		0x3c
#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK		(0x00 << 8)
#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX		0
#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \
		(1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX))

#define ARCH_PERFMON_BRANCH_MISSES_RETIRED		6
#define ARCH_PERFMON_EVENTS_COUNT			7

/*
 * Intel "Architectural Performance Monitoring" CPUID
 * detection/enumeration details:
 */
union cpuid10_eax {
	struct {
		unsigned int version_id:8;
		unsigned int num_counters:8;
		unsigned int bit_width:8;
		unsigned int mask_length:8;
	} split;
	unsigned int full;
};

union cpuid10_ebx {
	struct {
		unsigned int no_unhalted_core_cycles:1;
		unsigned int no_instructions_retired:1;
		unsigned int no_unhalted_reference_cycles:1;
		unsigned int no_llc_reference:1;
		unsigned int no_llc_misses:1;
		unsigned int no_branch_instruction_retired:1;
		unsigned int no_branch_misses_retired:1;
	} split;
	unsigned int full;
};

union cpuid10_edx {
	struct {
		unsigned int num_counters_fixed:5;
		unsigned int bit_width_fixed:8;
		unsigned int reserved:19;
	} split;
	unsigned int full;
};

struct x86_pmu_capability {
	int		version;
	int		num_counters_gp;
	int		num_counters_fixed;
	int		bit_width_gp;
	int		bit_width_fixed;
	unsigned int	events_mask;
	int		events_mask_len;
};

/*
 * Fixed-purpose performance events:
 */

/*
 * All 3 fixed-mode PMCs are configured via this single MSR:
 */
#define MSR_ARCH_PERFMON_FIXED_CTR_CTRL	0x38d

/*
 * The counts are available in three separate MSRs:
 */

/* Instr_Retired.Any: */
#define MSR_ARCH_PERFMON_FIXED_CTR0	0x309
#define INTEL_PMC_IDX_FIXED_INSTRUCTIONS	(INTEL_PMC_IDX_FIXED + 0)

/* CPU_CLK_Unhalted.Core: */
#define MSR_ARCH_PERFMON_FIXED_CTR1	0x30a
#define INTEL_PMC_IDX_FIXED_CPU_CYCLES	(INTEL_PMC_IDX_FIXED + 1)

/* CPU_CLK_Unhalted.Ref: */
#define MSR_ARCH_PERFMON_FIXED_CTR2	0x30b
#define INTEL_PMC_IDX_FIXED_REF_CYCLES	(INTEL_PMC_IDX_FIXED + 2)
#define INTEL_PMC_MSK_FIXED_REF_CYCLES	(1ULL << INTEL_PMC_IDX_FIXED_REF_CYCLES)

/*
 * We model BTS tracing as another fixed-mode PMC.
 *
 * We choose a value in the middle of the fixed event range, since lower
 * values are used by actual fixed events and higher values are used
 * to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr.
 */
#define INTEL_PMC_IDX_FIXED_BTS				(INTEL_PMC_IDX_FIXED + 16)

/*
 * IBS cpuid feature detection
 */

#define IBS_CPUID_FEATURES		0x8000001b

/*
 * Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but
 * bit 0 is used to indicate the existence of IBS.
 */
#define IBS_CAPS_AVAIL			(1U<<0)
#define IBS_CAPS_FETCHSAM		(1U<<1)
#define IBS_CAPS_OPSAM			(1U<<2)
#define IBS_CAPS_RDWROPCNT		(1U<<3)
#define IBS_CAPS_OPCNT			(1U<<4)
#define IBS_CAPS_BRNTRGT		(1U<<5)
#define IBS_CAPS_OPCNTEXT		(1U<<6)
#define IBS_CAPS_RIPINVALIDCHK		(1U<<7)

#define IBS_CAPS_DEFAULT		(IBS_CAPS_AVAIL		\
					 | IBS_CAPS_FETCHSAM	\
					 | IBS_CAPS_OPSAM)

/*
 * IBS APIC setup
 */
#define IBSCTL				0x1cc
#define IBSCTL_LVT_OFFSET_VALID		(1ULL<<8)
#define IBSCTL_LVT_OFFSET_MASK		0x0F

/* ibs fetch bits/masks */
#define IBS_FETCH_RAND_EN	(1ULL<<57)
#define IBS_FETCH_VAL		(1ULL<<49)
#define IBS_FETCH_ENABLE	(1ULL<<48)
#define IBS_FETCH_CNT		0xFFFF0000ULL
#define IBS_FETCH_MAX_CNT	0x0000FFFFULL

/* ibs op bits/masks */
/* lower 4 bits of the current count are ignored: */
#define IBS_OP_CUR_CNT		(0xFFFF0ULL<<32)
#define IBS_OP_CNT_CTL		(1ULL<<19)
#define IBS_OP_VAL		(1ULL<<18)
#define IBS_OP_ENABLE		(1ULL<<17)
#define IBS_OP_MAX_CNT		0x0000FFFFULL
#define IBS_OP_MAX_CNT_EXT	0x007FFFFFULL	/* not a register bit mask */
#define IBS_RIP_INVALID		(1ULL<<38)

#ifdef CONFIG_X86_LOCAL_APIC
extern u32 get_ibs_caps(void);
#else
static inline u32 get_ibs_caps(void) { return 0; }
#endif

#ifdef CONFIG_PERF_EVENTS
extern void perf_events_lapic_init(void);

/*
 * Abuse bits {3,5} of the cpu eflags register. These flags are otherwise
 * unused and ABI specified to be 0, so nobody should care what we do with
 * them.
 *
 * EXACT - the IP points to the exact instruction that triggered the
 *         event (HW bugs exempt).
 * VM    - original X86_VM_MASK; see set_linear_ip().
 */
#define PERF_EFLAGS_EXACT	(1UL << 3)
#define PERF_EFLAGS_VM		(1UL << 5)

struct pt_regs;
extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
extern unsigned long perf_misc_flags(struct pt_regs *regs);
#define perf_misc_flags(regs)	perf_misc_flags(regs)

#include <asm/stacktrace.h>

/*
 * We abuse bit 3 from flags to pass exact information, see perf_misc_flags
 * and the comment with PERF_EFLAGS_EXACT.
 */
#define perf_arch_fetch_caller_regs(regs, __ip)		{	\
	(regs)->ip = (__ip);					\
	(regs)->bp = caller_frame_pointer();			\
	(regs)->cs = __KERNEL_CS;				\
	regs->flags = 0;					\
	asm volatile(						\
		_ASM_MOV "%%"_ASM_SP ", %0\n"			\
		: "=m" ((regs)->sp)				\
		:: "memory"					\
	);							\
}

struct perf_guest_switch_msr {
	unsigned msr;
	u64 host, guest;
};

extern struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr);
extern void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap);
extern void perf_check_microcode(void);
#else
static inline struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
{
	*nr = 0;
	return NULL;
}

static inline void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
{
	memset(cap, 0, sizeof(*cap));
}

static inline void perf_events_lapic_init(void)	{ }
static inline void perf_check_microcode(void) { }
#endif

#if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD)
 extern void amd_pmu_enable_virt(void);
 extern void amd_pmu_disable_virt(void);
#else
 static inline void amd_pmu_enable_virt(void) { }
 static inline void amd_pmu_disable_virt(void) { }
#endif

#define arch_perf_out_copy_user copy_from_user_nmi

#endif /* _ASM_X86_PERF_EVENT_H */
Commit	Line	Data
cdd6c482 IM	1	#ifndef _ASM_X86_PERF_EVENT_H
cdd6c482 IM	2	#define _ASM_X86_PERF_EVENT_H
003a46cf	3
eb2b8618	4	/*
cdd6c482	5	* Performance event hw details:
eb2b8618 IM	6	*/
eb2b8618 IM	7
15c7ad51 RR	8	#define INTEL_PMC_MAX_GENERIC 32
	9	#define INTEL_PMC_MAX_FIXED 3
	10	#define INTEL_PMC_IDX_FIXED 32
eb2b8618	11
862a1a5f IM	12	#define X86_PMC_IDX_MAX 64
862a1a5f IM	13
241771ef IM	14	#define MSR_ARCH_PERFMON_PERFCTR0 0xc1
241771ef IM	15	#define MSR_ARCH_PERFMON_PERFCTR1 0xc2
003a46cf	16
241771ef IM	17	#define MSR_ARCH_PERFMON_EVENTSEL0 0x186
241771ef IM	18	#define MSR_ARCH_PERFMON_EVENTSEL1 0x187
003a46cf	19
a098f448 RR	20	#define ARCH_PERFMON_EVENTSEL_EVENT 0x000000FFULL
	21	#define ARCH_PERFMON_EVENTSEL_UMASK 0x0000FF00ULL
	22	#define ARCH_PERFMON_EVENTSEL_USR (1ULL << 16)
	23	#define ARCH_PERFMON_EVENTSEL_OS (1ULL << 17)
	24	#define ARCH_PERFMON_EVENTSEL_EDGE (1ULL << 18)
a7b9d2cc	25	#define ARCH_PERFMON_EVENTSEL_PIN_CONTROL (1ULL << 19)
a098f448 RR	26	#define ARCH_PERFMON_EVENTSEL_INT (1ULL << 20)
	27	#define ARCH_PERFMON_EVENTSEL_ANY (1ULL << 21)
	28	#define ARCH_PERFMON_EVENTSEL_ENABLE (1ULL << 22)
	29	#define ARCH_PERFMON_EVENTSEL_INV (1ULL << 23)
	30	#define ARCH_PERFMON_EVENTSEL_CMASK 0xFF000000ULL
	31
e259514e	32	#define AMD64_EVENTSEL_INT_CORE_ENABLE (1ULL << 36)
9f19010a JS	33	#define AMD64_EVENTSEL_GUESTONLY (1ULL << 40)
9f19010a JS	34	#define AMD64_EVENTSEL_HOSTONLY (1ULL << 41)
011af857	35
e259514e JS	36	#define AMD64_EVENTSEL_INT_CORE_SEL_SHIFT 37
	37	#define AMD64_EVENTSEL_INT_CORE_SEL_MASK \
	38	(0xFULL << AMD64_EVENTSEL_INT_CORE_SEL_SHIFT)
	39
a098f448 RR	40	#define AMD64_EVENTSEL_EVENT \
	41	(ARCH_PERFMON_EVENTSEL_EVENT \| (0x0FULL << 32))
	42	#define INTEL_ARCH_EVENT_MASK \
	43	(ARCH_PERFMON_EVENTSEL_UMASK \| ARCH_PERFMON_EVENTSEL_EVENT)
	44
	45	#define X86_RAW_EVENT_MASK \
	46	(ARCH_PERFMON_EVENTSEL_EVENT \| \
	47	ARCH_PERFMON_EVENTSEL_UMASK \| \
	48	ARCH_PERFMON_EVENTSEL_EDGE \| \
	49	ARCH_PERFMON_EVENTSEL_INV \| \
	50	ARCH_PERFMON_EVENTSEL_CMASK)
	51	#define AMD64_RAW_EVENT_MASK \
	52	(X86_RAW_EVENT_MASK \| \
	53	AMD64_EVENTSEL_EVENT)
e259514e JS	54	#define AMD64_RAW_EVENT_MASK_NB \
	55	(AMD64_EVENTSEL_EVENT \| \
	56	ARCH_PERFMON_EVENTSEL_UMASK)
ee5789db	57	#define AMD64_NUM_COUNTERS 4
b1dc3c48	58	#define AMD64_NUM_COUNTERS_CORE 6
e259514e	59	#define AMD64_NUM_COUNTERS_NB 4
04a705df	60
ee5789db	61	#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL 0x3c
241771ef	62	#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK (0x00 << 8)
ee5789db	63	#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX 0
003a46cf	64	#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \
241771ef IM	65	(1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX))
241771ef IM	66
ee5789db	67	#define ARCH_PERFMON_BRANCH_MISSES_RETIRED 6
ffb871bc	68	#define ARCH_PERFMON_EVENTS_COUNT 7
003a46cf	69
eb2b8618 IM	70	/*
	71	* Intel "Architectural Performance Monitoring" CPUID
	72	* detection/enumeration details:
	73	*/
003a46cf TG	74	union cpuid10_eax {
	75	struct {
	76	unsigned int version_id:8;
948b1bb8	77	unsigned int num_counters:8;
003a46cf TG	78	unsigned int bit_width:8;
	79	unsigned int mask_length:8;
	80	} split;
	81	unsigned int full;
	82	};
	83
ffb871bc GN	84	union cpuid10_ebx {
	85	struct {
	86	unsigned int no_unhalted_core_cycles:1;
	87	unsigned int no_instructions_retired:1;
	88	unsigned int no_unhalted_reference_cycles:1;
	89	unsigned int no_llc_reference:1;
	90	unsigned int no_llc_misses:1;
	91	unsigned int no_branch_instruction_retired:1;
	92	unsigned int no_branch_misses_retired:1;
	93	} split;
	94	unsigned int full;
	95	};
	96
703e937c IM	97	union cpuid10_edx {
703e937c IM	98	struct {
e768aee8 LS	99	unsigned int num_counters_fixed:5;
	100	unsigned int bit_width_fixed:8;
	101	unsigned int reserved:19;
703e937c IM	102	} split;
	103	unsigned int full;
	104	};
	105
b3d9468a GN	106	struct x86_pmu_capability {
	107	int version;
	108	int num_counters_gp;
	109	int num_counters_fixed;
	110	int bit_width_gp;
	111	int bit_width_fixed;
	112	unsigned int events_mask;
	113	int events_mask_len;
	114	};
703e937c IM	115
703e937c IM	116	/*
cdd6c482	117	* Fixed-purpose performance events:
703e937c IM	118	*/
703e937c IM	119
862a1a5f IM	120	/*
	121	* All 3 fixed-mode PMCs are configured via this single MSR:
	122	*/
cd09c0c4	123	#define MSR_ARCH_PERFMON_FIXED_CTR_CTRL 0x38d
862a1a5f IM	124
	125	/*
	126	* The counts are available in three separate MSRs:
	127	*/
	128
703e937c	129	/* Instr_Retired.Any: */
cd09c0c4	130	#define MSR_ARCH_PERFMON_FIXED_CTR0 0x309
15c7ad51	131	#define INTEL_PMC_IDX_FIXED_INSTRUCTIONS (INTEL_PMC_IDX_FIXED + 0)
703e937c IM	132
703e937c IM	133	/* CPU_CLK_Unhalted.Core: */
cd09c0c4	134	#define MSR_ARCH_PERFMON_FIXED_CTR1 0x30a
15c7ad51	135	#define INTEL_PMC_IDX_FIXED_CPU_CYCLES (INTEL_PMC_IDX_FIXED + 1)
703e937c IM	136
703e937c IM	137	/* CPU_CLK_Unhalted.Ref: */
cd09c0c4	138	#define MSR_ARCH_PERFMON_FIXED_CTR2 0x30b
15c7ad51 RR	139	#define INTEL_PMC_IDX_FIXED_REF_CYCLES (INTEL_PMC_IDX_FIXED + 2)
15c7ad51 RR	140	#define INTEL_PMC_MSK_FIXED_REF_CYCLES (1ULL << INTEL_PMC_IDX_FIXED_REF_CYCLES)
703e937c	141
30dd568c MM	142	/*
	143	* We model BTS tracing as another fixed-mode PMC.
	144	*
cdd6c482 IM	145	* We choose a value in the middle of the fixed event range, since lower
cdd6c482 IM	146	* values are used by actual fixed events and higher values are used
30dd568c MM	147	* to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr.
30dd568c MM	148	*/
15c7ad51	149	#define INTEL_PMC_IDX_FIXED_BTS (INTEL_PMC_IDX_FIXED + 16)
30dd568c	150
ee5789db RR	151	/*
	152	* IBS cpuid feature detection
	153	*/
	154
	155	#define IBS_CPUID_FEATURES 0x8000001b
	156
	157	/*
	158	* Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but
	159	* bit 0 is used to indicate the existence of IBS.
	160	*/
	161	#define IBS_CAPS_AVAIL (1U<<0)
	162	#define IBS_CAPS_FETCHSAM (1U<<1)
	163	#define IBS_CAPS_OPSAM (1U<<2)
	164	#define IBS_CAPS_RDWROPCNT (1U<<3)
	165	#define IBS_CAPS_OPCNT (1U<<4)
	166	#define IBS_CAPS_BRNTRGT (1U<<5)
	167	#define IBS_CAPS_OPCNTEXT (1U<<6)
d47e8238	168	#define IBS_CAPS_RIPINVALIDCHK (1U<<7)
ee5789db RR	169
	170	#define IBS_CAPS_DEFAULT (IBS_CAPS_AVAIL \
	171	\| IBS_CAPS_FETCHSAM \
	172	\| IBS_CAPS_OPSAM)
	173
	174	/*
	175	* IBS APIC setup
	176	*/
	177	#define IBSCTL 0x1cc
	178	#define IBSCTL_LVT_OFFSET_VALID (1ULL<<8)
	179	#define IBSCTL_LVT_OFFSET_MASK 0x0F
	180
d47e8238	181	/* ibs fetch bits/masks */
b47fad3b RR	182	#define IBS_FETCH_RAND_EN (1ULL<<57)
	183	#define IBS_FETCH_VAL (1ULL<<49)
	184	#define IBS_FETCH_ENABLE (1ULL<<48)
	185	#define IBS_FETCH_CNT 0xFFFF0000ULL
	186	#define IBS_FETCH_MAX_CNT 0x0000FFFFULL
1d6040f1	187
d47e8238	188	/* ibs op bits/masks */
db98c5fa RR	189	/* lower 4 bits of the current count are ignored: */
db98c5fa RR	190	#define IBS_OP_CUR_CNT (0xFFFF0ULL<<32)
b47fad3b RR	191	#define IBS_OP_CNT_CTL (1ULL<<19)
	192	#define IBS_OP_VAL (1ULL<<18)
	193	#define IBS_OP_ENABLE (1ULL<<17)
	194	#define IBS_OP_MAX_CNT 0x0000FFFFULL
	195	#define IBS_OP_MAX_CNT_EXT 0x007FFFFFULL /* not a register bit mask */
d47e8238	196	#define IBS_RIP_INVALID (1ULL<<38)
30dd568c	197
978da300	198	#ifdef CONFIG_X86_LOCAL_APIC
b7169166	199	extern u32 get_ibs_caps(void);
978da300 RR	200	#else
	201	static inline u32 get_ibs_caps(void) { return 0; }
	202	#endif
b7169166	203
cdd6c482	204	#ifdef CONFIG_PERF_EVENTS
cdd6c482	205	extern void perf_events_lapic_init(void);
194002b2	206
ef21f683	207	/*
d07bdfd3 PZ	208	* Abuse bits {3,5} of the cpu eflags register. These flags are otherwise
	209	* unused and ABI specified to be 0, so nobody should care what we do with
	210	* them.
	211	*
	212	* EXACT - the IP points to the exact instruction that triggered the
	213	* event (HW bugs exempt).
	214	* VM - original X86_VM_MASK; see set_linear_ip().
ef21f683 PZ	215	*/
ef21f683 PZ	216	#define PERF_EFLAGS_EXACT (1UL << 3)
d07bdfd3	217	#define PERF_EFLAGS_VM (1UL << 5)
ef21f683	218
39447b38 ZY	219	struct pt_regs;
	220	extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
	221	extern unsigned long perf_misc_flags(struct pt_regs *regs);
	222	#define perf_misc_flags(regs) perf_misc_flags(regs)
ef21f683	223
b0f82b81 FW	224	#include <asm/stacktrace.h>
	225
	226	/*
	227	* We abuse bit 3 from flags to pass exact information, see perf_misc_flags
	228	* and the comment with PERF_EFLAGS_EXACT.
	229	*/
	230	#define perf_arch_fetch_caller_regs(regs, __ip) { \
	231	(regs)->ip = (__ip); \
	232	(regs)->bp = caller_frame_pointer(); \
	233	(regs)->cs = __KERNEL_CS; \
	234	regs->flags = 0; \
9e46294d FW	235	asm volatile( \
	236	_ASM_MOV "%%"_ASM_SP ", %0\n" \
	237	: "=m" ((regs)->sp) \
	238	:: "memory" \
	239	); \
b0f82b81 FW	240	}
b0f82b81 FW	241
144d31e6 GN	242	struct perf_guest_switch_msr {
	243	unsigned msr;
	244	u64 host, guest;
	245	};
	246
	247	extern struct perf_guest_switch_msr perf_guest_get_msrs(int nr);
b3d9468a	248	extern void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap);
c93dc84c	249	extern void perf_check_microcode(void);
241771ef	250	#else
35d56ca9	251	static inline struct perf_guest_switch_msr perf_guest_get_msrs(int nr)
144d31e6 GN	252	{
	253	*nr = 0;
	254	return NULL;
	255	}
	256
b3d9468a GN	257	static inline void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
	258	{
	259	memset(cap, 0, sizeof(*cap));
	260	}
	261
cdd6c482	262	static inline void perf_events_lapic_init(void) { }
c93dc84c	263	static inline void perf_check_microcode(void) { }
241771ef IM	264	#endif
241771ef IM	265
1018faa6 JR	266	#if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD)
	267	extern void amd_pmu_enable_virt(void);
	268	extern void amd_pmu_disable_virt(void);
	269	#else
	270	static inline void amd_pmu_enable_virt(void) { }
	271	static inline void amd_pmu_disable_virt(void) { }
	272	#endif
	273
91d7753a FW	274	#define arch_perf_out_copy_user copy_from_user_nmi
91d7753a FW	275
cdd6c482	276	#endif /* _ASM_X86_PERF_EVENT_H */