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1965aae3 PA |
1 | #ifndef _ASM_X86_PGTABLE_32_H |
2 | #define _ASM_X86_PGTABLE_32_H | |
1da177e4 | 3 | |
f402a65f | 4 | #include <asm/pgtable_32_types.h> |
1da177e4 LT |
5 | |
6 | /* | |
7 | * The Linux memory management assumes a three-level page table setup. On | |
8 | * the i386, we use that, but "fold" the mid level into the top-level page | |
9 | * table, so that we physically have the same two-level page table as the | |
10 | * i386 mmu expects. | |
11 | * | |
12 | * This file contains the functions and defines necessary to modify and use | |
13 | * the i386 page table tree. | |
14 | */ | |
15 | #ifndef __ASSEMBLY__ | |
16 | #include <asm/processor.h> | |
17 | #include <asm/fixmap.h> | |
18 | #include <linux/threads.h> | |
da181a8b | 19 | #include <asm/paravirt.h> |
1da177e4 | 20 | |
1977f032 | 21 | #include <linux/bitops.h> |
1da177e4 LT |
22 | #include <linux/slab.h> |
23 | #include <linux/list.h> | |
24 | #include <linux/spinlock.h> | |
25 | ||
8c65b4a6 TS |
26 | struct mm_struct; |
27 | struct vm_area_struct; | |
28 | ||
1da177e4 | 29 | extern pgd_t swapper_pg_dir[1024]; |
1da177e4 | 30 | |
985a34bd TG |
31 | static inline void pgtable_cache_init(void) { } |
32 | static inline void check_pgt_cache(void) { } | |
1da177e4 LT |
33 | void paging_init(void); |
34 | ||
01eb7858 | 35 | extern void set_pmd_pfn(unsigned long, unsigned long, pgprot_t); |
f1d1a842 | 36 | |
e621bd18 | 37 | |
1da177e4 LT |
38 | /* |
39 | * Define this if things work differently on an i386 and an i486: | |
40 | * it will (on an i486) warn about kernel memory accesses that are | |
e49332bd | 41 | * done without a 'access_ok(VERIFY_WRITE,..)' |
1da177e4 | 42 | */ |
e49332bd | 43 | #undef TEST_ACCESS_OK |
1da177e4 | 44 | |
1da177e4 LT |
45 | #ifdef CONFIG_X86_PAE |
46 | # include <asm/pgtable-3level.h> | |
47 | #else | |
48 | # include <asm/pgtable-2level.h> | |
49 | #endif | |
50 | ||
1da177e4 | 51 | #if defined(CONFIG_HIGHPTE) |
0990b1c6 PZ |
52 | #define __KM_PTE \ |
53 | (in_nmi() ? KM_NMI_PTE : \ | |
54 | in_irq() ? KM_IRQ_PTE : \ | |
55 | KM_PTE0) | |
cf840147 | 56 | #define pte_offset_map(dir, address) \ |
dad52fc0 | 57 | ((pte_t *)kmap_atomic(pmd_page(*(dir)), __KM_PTE) + \ |
cf840147 JP |
58 | pte_index((address))) |
59 | #define pte_offset_map_nested(dir, address) \ | |
dad52fc0 | 60 | ((pte_t *)kmap_atomic(pmd_page(*(dir)), KM_PTE1) + \ |
cf840147 | 61 | pte_index((address))) |
3ff0141a | 62 | #define pte_unmap(pte) kunmap_atomic((pte), __KM_PTE) |
cf840147 | 63 | #define pte_unmap_nested(pte) kunmap_atomic((pte), KM_PTE1) |
1da177e4 | 64 | #else |
cf840147 JP |
65 | #define pte_offset_map(dir, address) \ |
66 | ((pte_t *)page_address(pmd_page(*(dir))) + pte_index((address))) | |
67 | #define pte_offset_map_nested(dir, address) pte_offset_map((dir), (address)) | |
1da177e4 LT |
68 | #define pte_unmap(pte) do { } while (0) |
69 | #define pte_unmap_nested(pte) do { } while (0) | |
70 | #endif | |
71 | ||
23002d88 | 72 | /* Clear a kernel PTE and flush it from the TLB */ |
cf840147 JP |
73 | #define kpte_clear_flush(ptep, vaddr) \ |
74 | do { \ | |
75 | pte_clear(&init_mm, (vaddr), (ptep)); \ | |
76 | __flush_tlb_one((vaddr)); \ | |
23002d88 ZA |
77 | } while (0) |
78 | ||
1da177e4 LT |
79 | /* |
80 | * The i386 doesn't have any external MMU info: the kernel page | |
81 | * tables contain all the necessary information. | |
1da177e4 | 82 | */ |
cf840147 | 83 | #define update_mmu_cache(vma, address, pte) do { } while (0) |
b239fb25 | 84 | |
1da177e4 LT |
85 | #endif /* !__ASSEMBLY__ */ |
86 | ||
4757d7d8 TG |
87 | /* |
88 | * kern_addr_valid() is (1) for FLATMEM and (0) for | |
89 | * SPARSEMEM and DISCONTIGMEM | |
90 | */ | |
05b79bdc | 91 | #ifdef CONFIG_FLATMEM |
1da177e4 | 92 | #define kern_addr_valid(addr) (1) |
4757d7d8 TG |
93 | #else |
94 | #define kern_addr_valid(kaddr) (0) | |
95 | #endif | |
1da177e4 | 96 | |
1965aae3 | 97 | #endif /* _ASM_X86_PGTABLE_32_H */ |