Commit | Line | Data |
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1965aae3 PA |
1 | #ifndef _ASM_X86_PROCESSOR_H |
2 | #define _ASM_X86_PROCESSOR_H | |
c758ecf6 | 3 | |
053de044 GOC |
4 | #include <asm/processor-flags.h> |
5 | ||
683e0253 GOC |
6 | /* Forward declaration, a strange C thing */ |
7 | struct task_struct; | |
8 | struct mm_struct; | |
9 | ||
2f66dcc9 GOC |
10 | #include <asm/vm86.h> |
11 | #include <asm/math_emu.h> | |
12 | #include <asm/segment.h> | |
2f66dcc9 GOC |
13 | #include <asm/types.h> |
14 | #include <asm/sigcontext.h> | |
15 | #include <asm/current.h> | |
16 | #include <asm/cpufeature.h> | |
c72dcf83 | 17 | #include <asm/system.h> |
2f66dcc9 | 18 | #include <asm/page.h> |
5300db88 | 19 | #include <asm/percpu.h> |
2f66dcc9 GOC |
20 | #include <asm/msr.h> |
21 | #include <asm/desc_defs.h> | |
bd61643e | 22 | #include <asm/nops.h> |
93fa7636 | 23 | #include <asm/ds.h> |
4d46a89e | 24 | |
2f66dcc9 | 25 | #include <linux/personality.h> |
5300db88 GOC |
26 | #include <linux/cpumask.h> |
27 | #include <linux/cache.h> | |
2f66dcc9 GOC |
28 | #include <linux/threads.h> |
29 | #include <linux/init.h> | |
c72dcf83 | 30 | |
0ccb8acc GOC |
31 | /* |
32 | * Default implementation of macro that returns current | |
33 | * instruction pointer ("program counter"). | |
34 | */ | |
35 | static inline void *current_text_addr(void) | |
36 | { | |
37 | void *pc; | |
4d46a89e IM |
38 | |
39 | asm volatile("mov $1f, %0; 1:":"=r" (pc)); | |
40 | ||
0ccb8acc GOC |
41 | return pc; |
42 | } | |
43 | ||
dbcb4660 | 44 | #ifdef CONFIG_X86_VSMP |
4d46a89e IM |
45 | # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT) |
46 | # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT) | |
dbcb4660 | 47 | #else |
4d46a89e IM |
48 | # define ARCH_MIN_TASKALIGN 16 |
49 | # define ARCH_MIN_MMSTRUCT_ALIGN 0 | |
dbcb4660 GOC |
50 | #endif |
51 | ||
5300db88 GOC |
52 | /* |
53 | * CPU type and hardware bug flags. Kept separately for each CPU. | |
54 | * Members of this structure are referenced in head.S, so think twice | |
55 | * before touching them. [mj] | |
56 | */ | |
57 | ||
58 | struct cpuinfo_x86 { | |
4d46a89e IM |
59 | __u8 x86; /* CPU family */ |
60 | __u8 x86_vendor; /* CPU vendor */ | |
61 | __u8 x86_model; | |
62 | __u8 x86_mask; | |
5300db88 | 63 | #ifdef CONFIG_X86_32 |
4d46a89e IM |
64 | char wp_works_ok; /* It doesn't on 386's */ |
65 | ||
66 | /* Problems on some 486Dx4's and old 386's: */ | |
67 | char hlt_works_ok; | |
68 | char hard_math; | |
69 | char rfu; | |
70 | char fdiv_bug; | |
71 | char f00f_bug; | |
72 | char coma_bug; | |
73 | char pad0; | |
5300db88 | 74 | #else |
4d46a89e IM |
75 | /* Number of 4K pages in DTLB/ITLB combined(in pages): */ |
76 | int x86_tlbsize; | |
77 | __u8 x86_virt_bits; | |
78 | __u8 x86_phys_bits; | |
11fdd252 | 79 | #endif |
4d46a89e IM |
80 | /* CPUID returned core id bits: */ |
81 | __u8 x86_coreid_bits; | |
82 | /* Max extended CPUID function supported: */ | |
83 | __u32 extended_cpuid_level; | |
4d46a89e IM |
84 | /* Maximum supported CPUID level, -1=no CPUID: */ |
85 | int cpuid_level; | |
86 | __u32 x86_capability[NCAPINTS]; | |
87 | char x86_vendor_id[16]; | |
88 | char x86_model_id[64]; | |
89 | /* in KB - valid for CPUS which support this call: */ | |
90 | int x86_cache_size; | |
91 | int x86_cache_alignment; /* In bytes */ | |
92 | int x86_power; | |
93 | unsigned long loops_per_jiffy; | |
5300db88 | 94 | #ifdef CONFIG_SMP |
4d46a89e IM |
95 | /* cpus sharing the last level cache: */ |
96 | cpumask_t llc_shared_map; | |
5300db88 | 97 | #endif |
4d46a89e IM |
98 | /* cpuid returned max cores value: */ |
99 | u16 x86_max_cores; | |
100 | u16 apicid; | |
01aaea1a | 101 | u16 initial_apicid; |
4d46a89e | 102 | u16 x86_clflush_size; |
5300db88 | 103 | #ifdef CONFIG_SMP |
4d46a89e IM |
104 | /* number of cores as seen by the OS: */ |
105 | u16 booted_cores; | |
106 | /* Physical processor id: */ | |
107 | u16 phys_proc_id; | |
108 | /* Core id: */ | |
109 | u16 cpu_core_id; | |
110 | /* Index into per_cpu list: */ | |
111 | u16 cpu_index; | |
5300db88 | 112 | #endif |
88b094fb | 113 | unsigned int x86_hyper_vendor; |
5300db88 GOC |
114 | } __attribute__((__aligned__(SMP_CACHE_BYTES))); |
115 | ||
4d46a89e IM |
116 | #define X86_VENDOR_INTEL 0 |
117 | #define X86_VENDOR_CYRIX 1 | |
118 | #define X86_VENDOR_AMD 2 | |
119 | #define X86_VENDOR_UMC 3 | |
4d46a89e IM |
120 | #define X86_VENDOR_CENTAUR 5 |
121 | #define X86_VENDOR_TRANSMETA 7 | |
122 | #define X86_VENDOR_NSC 8 | |
123 | #define X86_VENDOR_NUM 9 | |
124 | ||
125 | #define X86_VENDOR_UNKNOWN 0xff | |
5300db88 | 126 | |
88b094fb AK |
127 | #define X86_HYPER_VENDOR_NONE 0 |
128 | #define X86_HYPER_VENDOR_VMWARE 1 | |
129 | ||
1a53905a GOC |
130 | /* |
131 | * capabilities of CPUs | |
132 | */ | |
4d46a89e IM |
133 | extern struct cpuinfo_x86 boot_cpu_data; |
134 | extern struct cpuinfo_x86 new_cpu_data; | |
135 | ||
136 | extern struct tss_struct doublefault_tss; | |
137 | extern __u32 cleared_cpu_caps[NCAPINTS]; | |
5300db88 GOC |
138 | |
139 | #ifdef CONFIG_SMP | |
140 | DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info); | |
141 | #define cpu_data(cpu) per_cpu(cpu_info, cpu) | |
94a1e869 | 142 | #define current_cpu_data __get_cpu_var(cpu_info) |
5300db88 GOC |
143 | #else |
144 | #define cpu_data(cpu) boot_cpu_data | |
145 | #define current_cpu_data boot_cpu_data | |
146 | #endif | |
147 | ||
1c6c727d JS |
148 | extern const struct seq_operations cpuinfo_op; |
149 | ||
3d3f487c GC |
150 | static inline int hlt_works(int cpu) |
151 | { | |
152 | #ifdef CONFIG_X86_32 | |
153 | return cpu_data(cpu).hlt_works_ok; | |
154 | #else | |
155 | return 1; | |
156 | #endif | |
157 | } | |
158 | ||
4d46a89e IM |
159 | #define cache_line_size() (boot_cpu_data.x86_cache_alignment) |
160 | ||
161 | extern void cpu_detect(struct cpuinfo_x86 *c); | |
1a53905a | 162 | |
8fd329a1 JS |
163 | extern struct pt_regs *idle_regs(struct pt_regs *); |
164 | ||
f580366f | 165 | extern void early_cpu_init(void); |
1a53905a GOC |
166 | extern void identify_boot_cpu(void); |
167 | extern void identify_secondary_cpu(struct cpuinfo_x86 *); | |
5300db88 GOC |
168 | extern void print_cpu_info(struct cpuinfo_x86 *); |
169 | extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c); | |
170 | extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c); | |
171 | extern unsigned short num_cache_leaves; | |
172 | ||
bbb65d2d | 173 | extern void detect_extended_topology(struct cpuinfo_x86 *c); |
1a53905a | 174 | extern void detect_ht(struct cpuinfo_x86 *c); |
1a53905a | 175 | |
c758ecf6 | 176 | static inline void native_cpuid(unsigned int *eax, unsigned int *ebx, |
4d46a89e | 177 | unsigned int *ecx, unsigned int *edx) |
c758ecf6 GOC |
178 | { |
179 | /* ecx is often an input as well as an output. */ | |
cca2e6f8 JP |
180 | asm("cpuid" |
181 | : "=a" (*eax), | |
182 | "=b" (*ebx), | |
183 | "=c" (*ecx), | |
184 | "=d" (*edx) | |
185 | : "0" (*eax), "2" (*ecx)); | |
c758ecf6 GOC |
186 | } |
187 | ||
c72dcf83 GOC |
188 | static inline void load_cr3(pgd_t *pgdir) |
189 | { | |
190 | write_cr3(__pa(pgdir)); | |
191 | } | |
c758ecf6 | 192 | |
ca241c75 GOC |
193 | #ifdef CONFIG_X86_32 |
194 | /* This is the TSS defined by the hardware. */ | |
195 | struct x86_hw_tss { | |
4d46a89e IM |
196 | unsigned short back_link, __blh; |
197 | unsigned long sp0; | |
198 | unsigned short ss0, __ss0h; | |
199 | unsigned long sp1; | |
200 | /* ss1 caches MSR_IA32_SYSENTER_CS: */ | |
201 | unsigned short ss1, __ss1h; | |
202 | unsigned long sp2; | |
203 | unsigned short ss2, __ss2h; | |
204 | unsigned long __cr3; | |
205 | unsigned long ip; | |
206 | unsigned long flags; | |
207 | unsigned long ax; | |
208 | unsigned long cx; | |
209 | unsigned long dx; | |
210 | unsigned long bx; | |
211 | unsigned long sp; | |
212 | unsigned long bp; | |
213 | unsigned long si; | |
214 | unsigned long di; | |
215 | unsigned short es, __esh; | |
216 | unsigned short cs, __csh; | |
217 | unsigned short ss, __ssh; | |
218 | unsigned short ds, __dsh; | |
219 | unsigned short fs, __fsh; | |
220 | unsigned short gs, __gsh; | |
221 | unsigned short ldt, __ldth; | |
222 | unsigned short trace; | |
223 | unsigned short io_bitmap_base; | |
224 | ||
ca241c75 GOC |
225 | } __attribute__((packed)); |
226 | #else | |
227 | struct x86_hw_tss { | |
4d46a89e IM |
228 | u32 reserved1; |
229 | u64 sp0; | |
230 | u64 sp1; | |
231 | u64 sp2; | |
232 | u64 reserved2; | |
233 | u64 ist[7]; | |
234 | u32 reserved3; | |
235 | u32 reserved4; | |
236 | u16 reserved5; | |
237 | u16 io_bitmap_base; | |
238 | ||
ca241c75 GOC |
239 | } __attribute__((packed)) ____cacheline_aligned; |
240 | #endif | |
241 | ||
242 | /* | |
4d46a89e | 243 | * IO-bitmap sizes: |
ca241c75 | 244 | */ |
4d46a89e IM |
245 | #define IO_BITMAP_BITS 65536 |
246 | #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8) | |
247 | #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long)) | |
248 | #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap) | |
249 | #define INVALID_IO_BITMAP_OFFSET 0x8000 | |
250 | #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000 | |
ca241c75 GOC |
251 | |
252 | struct tss_struct { | |
4d46a89e IM |
253 | /* |
254 | * The hardware state: | |
255 | */ | |
256 | struct x86_hw_tss x86_tss; | |
ca241c75 GOC |
257 | |
258 | /* | |
259 | * The extra 1 is there because the CPU will access an | |
260 | * additional byte beyond the end of the IO permission | |
261 | * bitmap. The extra byte must be all 1 bits, and must | |
262 | * be within the limit. | |
263 | */ | |
4d46a89e | 264 | unsigned long io_bitmap[IO_BITMAP_LONGS + 1]; |
ca241c75 GOC |
265 | /* |
266 | * Cache the current maximum and the last task that used the bitmap: | |
267 | */ | |
4d46a89e IM |
268 | unsigned long io_bitmap_max; |
269 | struct thread_struct *io_bitmap_owner; | |
270 | ||
ca241c75 | 271 | /* |
4d46a89e | 272 | * .. and then another 0x100 bytes for the emergency kernel stack: |
ca241c75 | 273 | */ |
4d46a89e IM |
274 | unsigned long stack[64]; |
275 | ||
84e65b0a | 276 | } ____cacheline_aligned; |
ca241c75 GOC |
277 | |
278 | DECLARE_PER_CPU(struct tss_struct, init_tss); | |
279 | ||
4d46a89e IM |
280 | /* |
281 | * Save the original ist values for checking stack pointers during debugging | |
282 | */ | |
1a53905a | 283 | struct orig_ist { |
4d46a89e | 284 | unsigned long ist[7]; |
1a53905a GOC |
285 | }; |
286 | ||
99f8ecdf | 287 | #define MXCSR_DEFAULT 0x1f80 |
46265df0 | 288 | |
99f8ecdf | 289 | struct i387_fsave_struct { |
ca9cda2f IM |
290 | u32 cwd; /* FPU Control Word */ |
291 | u32 swd; /* FPU Status Word */ | |
292 | u32 twd; /* FPU Tag Word */ | |
293 | u32 fip; /* FPU IP Offset */ | |
294 | u32 fcs; /* FPU IP Selector */ | |
295 | u32 foo; /* FPU Operand Pointer Offset */ | |
296 | u32 fos; /* FPU Operand Pointer Selector */ | |
297 | ||
298 | /* 8*10 bytes for each FP-reg = 80 bytes: */ | |
4d46a89e | 299 | u32 st_space[20]; |
ca9cda2f IM |
300 | |
301 | /* Software status information [not touched by FSAVE ]: */ | |
4d46a89e | 302 | u32 status; |
46265df0 GOC |
303 | }; |
304 | ||
46265df0 | 305 | struct i387_fxsave_struct { |
ca9cda2f IM |
306 | u16 cwd; /* Control Word */ |
307 | u16 swd; /* Status Word */ | |
308 | u16 twd; /* Tag Word */ | |
309 | u16 fop; /* Last Instruction Opcode */ | |
99f8ecdf RM |
310 | union { |
311 | struct { | |
ca9cda2f IM |
312 | u64 rip; /* Instruction Pointer */ |
313 | u64 rdp; /* Data Pointer */ | |
99f8ecdf RM |
314 | }; |
315 | struct { | |
ca9cda2f IM |
316 | u32 fip; /* FPU IP Offset */ |
317 | u32 fcs; /* FPU IP Selector */ | |
318 | u32 foo; /* FPU Operand Offset */ | |
319 | u32 fos; /* FPU Operand Selector */ | |
99f8ecdf RM |
320 | }; |
321 | }; | |
ca9cda2f IM |
322 | u32 mxcsr; /* MXCSR Register State */ |
323 | u32 mxcsr_mask; /* MXCSR Mask */ | |
324 | ||
325 | /* 8*16 bytes for each FP-reg = 128 bytes: */ | |
4d46a89e | 326 | u32 st_space[32]; |
ca9cda2f IM |
327 | |
328 | /* 16*16 bytes for each XMM-reg = 256 bytes: */ | |
4d46a89e | 329 | u32 xmm_space[64]; |
ca9cda2f | 330 | |
bdd8caba SS |
331 | u32 padding[12]; |
332 | ||
333 | union { | |
334 | u32 padding1[12]; | |
335 | u32 sw_reserved[12]; | |
336 | }; | |
4d46a89e | 337 | |
46265df0 GOC |
338 | } __attribute__((aligned(16))); |
339 | ||
99f8ecdf | 340 | struct i387_soft_struct { |
4d46a89e IM |
341 | u32 cwd; |
342 | u32 swd; | |
343 | u32 twd; | |
344 | u32 fip; | |
345 | u32 fcs; | |
346 | u32 foo; | |
347 | u32 fos; | |
348 | /* 8*10 bytes for each FP-reg = 80 bytes: */ | |
349 | u32 st_space[20]; | |
350 | u8 ftop; | |
351 | u8 changed; | |
352 | u8 lookahead; | |
353 | u8 no_update; | |
354 | u8 rm; | |
355 | u8 alimit; | |
356 | struct info *info; | |
357 | u32 entry_eip; | |
99f8ecdf RM |
358 | }; |
359 | ||
dc1e35c6 SS |
360 | struct xsave_hdr_struct { |
361 | u64 xstate_bv; | |
362 | u64 reserved1[2]; | |
363 | u64 reserved2[5]; | |
364 | } __attribute__((packed)); | |
365 | ||
366 | struct xsave_struct { | |
367 | struct i387_fxsave_struct i387; | |
368 | struct xsave_hdr_struct xsave_hdr; | |
369 | /* new processor state extensions will go here */ | |
370 | } __attribute__ ((packed, aligned (64))); | |
371 | ||
61c4628b | 372 | union thread_xstate { |
99f8ecdf | 373 | struct i387_fsave_struct fsave; |
46265df0 | 374 | struct i387_fxsave_struct fxsave; |
4d46a89e | 375 | struct i387_soft_struct soft; |
b359e8a4 | 376 | struct xsave_struct xsave; |
46265df0 GOC |
377 | }; |
378 | ||
fe676203 | 379 | #ifdef CONFIG_X86_64 |
2f66dcc9 | 380 | DECLARE_PER_CPU(struct orig_ist, orig_ist); |
26f80bd6 | 381 | |
947e76cd BG |
382 | union irq_stack_union { |
383 | char irq_stack[IRQ_STACK_SIZE]; | |
384 | /* | |
385 | * GCC hardcodes the stack canary as %gs:40. Since the | |
386 | * irq_stack is the object at %gs:0, we reserve the bottom | |
387 | * 48 bytes of the irq stack for the canary. | |
388 | */ | |
389 | struct { | |
390 | char gs_base[40]; | |
391 | unsigned long stack_canary; | |
392 | }; | |
393 | }; | |
394 | ||
395 | DECLARE_PER_CPU(union irq_stack_union, irq_stack_union); | |
26f80bd6 | 396 | DECLARE_PER_CPU(char *, irq_stack_ptr); |
947e76cd BG |
397 | |
398 | static inline void load_gs_base(int cpu) | |
399 | { | |
947e76cd | 400 | wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); |
947e76cd | 401 | } |
96a388de | 402 | #endif |
c758ecf6 | 403 | |
683e0253 | 404 | extern void print_cpu_info(struct cpuinfo_x86 *); |
61c4628b | 405 | extern unsigned int xstate_size; |
aa283f49 SS |
406 | extern void free_thread_xstate(struct task_struct *); |
407 | extern struct kmem_cache *task_xstate_cachep; | |
683e0253 GOC |
408 | extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c); |
409 | extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c); | |
410 | extern unsigned short num_cache_leaves; | |
411 | ||
cb38d377 | 412 | struct thread_struct { |
4d46a89e IM |
413 | /* Cached TLS descriptors: */ |
414 | struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES]; | |
415 | unsigned long sp0; | |
416 | unsigned long sp; | |
cb38d377 | 417 | #ifdef CONFIG_X86_32 |
4d46a89e | 418 | unsigned long sysenter_cs; |
cb38d377 | 419 | #else |
4d46a89e IM |
420 | unsigned long usersp; /* Copy from PDA */ |
421 | unsigned short es; | |
422 | unsigned short ds; | |
423 | unsigned short fsindex; | |
424 | unsigned short gsindex; | |
cb38d377 | 425 | #endif |
4d46a89e IM |
426 | unsigned long ip; |
427 | unsigned long fs; | |
428 | unsigned long gs; | |
429 | /* Hardware debugging registers: */ | |
430 | unsigned long debugreg0; | |
431 | unsigned long debugreg1; | |
432 | unsigned long debugreg2; | |
433 | unsigned long debugreg3; | |
434 | unsigned long debugreg6; | |
435 | unsigned long debugreg7; | |
436 | /* Fault info: */ | |
437 | unsigned long cr2; | |
438 | unsigned long trap_no; | |
439 | unsigned long error_code; | |
61c4628b SS |
440 | /* floating point and extended processor state */ |
441 | union thread_xstate *xstate; | |
cb38d377 | 442 | #ifdef CONFIG_X86_32 |
4d46a89e | 443 | /* Virtual 86 mode info */ |
cb38d377 GOC |
444 | struct vm86_struct __user *vm86_info; |
445 | unsigned long screen_bitmap; | |
4d46a89e IM |
446 | unsigned long v86flags; |
447 | unsigned long v86mask; | |
448 | unsigned long saved_sp0; | |
449 | unsigned int saved_fs; | |
450 | unsigned int saved_gs; | |
cb38d377 | 451 | #endif |
4d46a89e IM |
452 | /* IO permissions: */ |
453 | unsigned long *io_bitmap_ptr; | |
454 | unsigned long iopl; | |
455 | /* Max allowed port in the bitmap, in bytes: */ | |
456 | unsigned io_bitmap_max; | |
cb38d377 GOC |
457 | /* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set. */ |
458 | unsigned long debugctlmsr; | |
93fa7636 MM |
459 | #ifdef CONFIG_X86_DS |
460 | /* Debug Store context; see include/asm-x86/ds.h; goes into MSR_IA32_DS_AREA */ | |
461 | struct ds_context *ds_ctx; | |
462 | #endif /* CONFIG_X86_DS */ | |
463 | #ifdef CONFIG_X86_PTRACE_BTS | |
464 | /* the signal to send on a bts buffer overflow */ | |
465 | unsigned int bts_ovfl_signal; | |
466 | #endif /* CONFIG_X86_PTRACE_BTS */ | |
cb38d377 GOC |
467 | }; |
468 | ||
1b46cbe0 GOC |
469 | static inline unsigned long native_get_debugreg(int regno) |
470 | { | |
4d46a89e | 471 | unsigned long val = 0; /* Damn you, gcc! */ |
1b46cbe0 GOC |
472 | |
473 | switch (regno) { | |
474 | case 0: | |
cca2e6f8 JP |
475 | asm("mov %%db0, %0" :"=r" (val)); |
476 | break; | |
1b46cbe0 | 477 | case 1: |
cca2e6f8 JP |
478 | asm("mov %%db1, %0" :"=r" (val)); |
479 | break; | |
1b46cbe0 | 480 | case 2: |
cca2e6f8 JP |
481 | asm("mov %%db2, %0" :"=r" (val)); |
482 | break; | |
1b46cbe0 | 483 | case 3: |
cca2e6f8 JP |
484 | asm("mov %%db3, %0" :"=r" (val)); |
485 | break; | |
1b46cbe0 | 486 | case 6: |
cca2e6f8 JP |
487 | asm("mov %%db6, %0" :"=r" (val)); |
488 | break; | |
1b46cbe0 | 489 | case 7: |
cca2e6f8 JP |
490 | asm("mov %%db7, %0" :"=r" (val)); |
491 | break; | |
1b46cbe0 GOC |
492 | default: |
493 | BUG(); | |
494 | } | |
495 | return val; | |
496 | } | |
497 | ||
498 | static inline void native_set_debugreg(int regno, unsigned long value) | |
499 | { | |
500 | switch (regno) { | |
501 | case 0: | |
4d46a89e | 502 | asm("mov %0, %%db0" ::"r" (value)); |
1b46cbe0 GOC |
503 | break; |
504 | case 1: | |
4d46a89e | 505 | asm("mov %0, %%db1" ::"r" (value)); |
1b46cbe0 GOC |
506 | break; |
507 | case 2: | |
4d46a89e | 508 | asm("mov %0, %%db2" ::"r" (value)); |
1b46cbe0 GOC |
509 | break; |
510 | case 3: | |
4d46a89e | 511 | asm("mov %0, %%db3" ::"r" (value)); |
1b46cbe0 GOC |
512 | break; |
513 | case 6: | |
4d46a89e | 514 | asm("mov %0, %%db6" ::"r" (value)); |
1b46cbe0 GOC |
515 | break; |
516 | case 7: | |
4d46a89e | 517 | asm("mov %0, %%db7" ::"r" (value)); |
1b46cbe0 GOC |
518 | break; |
519 | default: | |
520 | BUG(); | |
521 | } | |
522 | } | |
523 | ||
62d7d7ed GOC |
524 | /* |
525 | * Set IOPL bits in EFLAGS from given mask | |
526 | */ | |
527 | static inline void native_set_iopl_mask(unsigned mask) | |
528 | { | |
529 | #ifdef CONFIG_X86_32 | |
530 | unsigned int reg; | |
4d46a89e | 531 | |
cca2e6f8 JP |
532 | asm volatile ("pushfl;" |
533 | "popl %0;" | |
534 | "andl %1, %0;" | |
535 | "orl %2, %0;" | |
536 | "pushl %0;" | |
537 | "popfl" | |
538 | : "=&r" (reg) | |
539 | : "i" (~X86_EFLAGS_IOPL), "r" (mask)); | |
62d7d7ed GOC |
540 | #endif |
541 | } | |
542 | ||
4d46a89e IM |
543 | static inline void |
544 | native_load_sp0(struct tss_struct *tss, struct thread_struct *thread) | |
7818a1e0 GOC |
545 | { |
546 | tss->x86_tss.sp0 = thread->sp0; | |
547 | #ifdef CONFIG_X86_32 | |
4d46a89e | 548 | /* Only happens when SEP is enabled, no need to test "SEP"arately: */ |
7818a1e0 GOC |
549 | if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) { |
550 | tss->x86_tss.ss1 = thread->sysenter_cs; | |
551 | wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0); | |
552 | } | |
553 | #endif | |
554 | } | |
1b46cbe0 | 555 | |
e801f864 GOC |
556 | static inline void native_swapgs(void) |
557 | { | |
558 | #ifdef CONFIG_X86_64 | |
559 | asm volatile("swapgs" ::: "memory"); | |
560 | #endif | |
561 | } | |
562 | ||
7818a1e0 GOC |
563 | #ifdef CONFIG_PARAVIRT |
564 | #include <asm/paravirt.h> | |
565 | #else | |
4d46a89e IM |
566 | #define __cpuid native_cpuid |
567 | #define paravirt_enabled() 0 | |
1b46cbe0 GOC |
568 | |
569 | /* | |
570 | * These special macros can be used to get or set a debugging register | |
571 | */ | |
572 | #define get_debugreg(var, register) \ | |
573 | (var) = native_get_debugreg(register) | |
574 | #define set_debugreg(value, register) \ | |
575 | native_set_debugreg(register, value) | |
576 | ||
cca2e6f8 JP |
577 | static inline void load_sp0(struct tss_struct *tss, |
578 | struct thread_struct *thread) | |
7818a1e0 GOC |
579 | { |
580 | native_load_sp0(tss, thread); | |
581 | } | |
582 | ||
62d7d7ed | 583 | #define set_iopl_mask native_set_iopl_mask |
1b46cbe0 GOC |
584 | #endif /* CONFIG_PARAVIRT */ |
585 | ||
586 | /* | |
587 | * Save the cr4 feature set we're using (ie | |
588 | * Pentium 4MB enable and PPro Global page | |
589 | * enable), so that any CPU's that boot up | |
590 | * after us can get the correct flags. | |
591 | */ | |
4d46a89e | 592 | extern unsigned long mmu_cr4_features; |
1b46cbe0 GOC |
593 | |
594 | static inline void set_in_cr4(unsigned long mask) | |
595 | { | |
596 | unsigned cr4; | |
4d46a89e | 597 | |
1b46cbe0 GOC |
598 | mmu_cr4_features |= mask; |
599 | cr4 = read_cr4(); | |
600 | cr4 |= mask; | |
601 | write_cr4(cr4); | |
602 | } | |
603 | ||
604 | static inline void clear_in_cr4(unsigned long mask) | |
605 | { | |
606 | unsigned cr4; | |
4d46a89e | 607 | |
1b46cbe0 GOC |
608 | mmu_cr4_features &= ~mask; |
609 | cr4 = read_cr4(); | |
610 | cr4 &= ~mask; | |
611 | write_cr4(cr4); | |
612 | } | |
613 | ||
fc87e906 | 614 | typedef struct { |
4d46a89e | 615 | unsigned long seg; |
fc87e906 GOC |
616 | } mm_segment_t; |
617 | ||
618 | ||
683e0253 GOC |
619 | /* |
620 | * create a kernel thread without removing it from tasklists | |
621 | */ | |
622 | extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); | |
623 | ||
624 | /* Free all resources held by a thread. */ | |
625 | extern void release_thread(struct task_struct *); | |
626 | ||
4d46a89e | 627 | /* Prepare to copy thread state - unlazy all lazy state */ |
683e0253 | 628 | extern void prepare_to_copy(struct task_struct *tsk); |
1b46cbe0 | 629 | |
683e0253 | 630 | unsigned long get_wchan(struct task_struct *p); |
c758ecf6 GOC |
631 | |
632 | /* | |
633 | * Generic CPUID function | |
634 | * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx | |
635 | * resulting in stale register contents being returned. | |
636 | */ | |
637 | static inline void cpuid(unsigned int op, | |
638 | unsigned int *eax, unsigned int *ebx, | |
639 | unsigned int *ecx, unsigned int *edx) | |
640 | { | |
641 | *eax = op; | |
642 | *ecx = 0; | |
643 | __cpuid(eax, ebx, ecx, edx); | |
644 | } | |
645 | ||
646 | /* Some CPUID calls want 'count' to be placed in ecx */ | |
647 | static inline void cpuid_count(unsigned int op, int count, | |
648 | unsigned int *eax, unsigned int *ebx, | |
649 | unsigned int *ecx, unsigned int *edx) | |
650 | { | |
651 | *eax = op; | |
652 | *ecx = count; | |
653 | __cpuid(eax, ebx, ecx, edx); | |
654 | } | |
655 | ||
656 | /* | |
657 | * CPUID functions returning a single datum | |
658 | */ | |
659 | static inline unsigned int cpuid_eax(unsigned int op) | |
660 | { | |
661 | unsigned int eax, ebx, ecx, edx; | |
662 | ||
663 | cpuid(op, &eax, &ebx, &ecx, &edx); | |
4d46a89e | 664 | |
c758ecf6 GOC |
665 | return eax; |
666 | } | |
4d46a89e | 667 | |
c758ecf6 GOC |
668 | static inline unsigned int cpuid_ebx(unsigned int op) |
669 | { | |
670 | unsigned int eax, ebx, ecx, edx; | |
671 | ||
672 | cpuid(op, &eax, &ebx, &ecx, &edx); | |
4d46a89e | 673 | |
c758ecf6 GOC |
674 | return ebx; |
675 | } | |
4d46a89e | 676 | |
c758ecf6 GOC |
677 | static inline unsigned int cpuid_ecx(unsigned int op) |
678 | { | |
679 | unsigned int eax, ebx, ecx, edx; | |
680 | ||
681 | cpuid(op, &eax, &ebx, &ecx, &edx); | |
4d46a89e | 682 | |
c758ecf6 GOC |
683 | return ecx; |
684 | } | |
4d46a89e | 685 | |
c758ecf6 GOC |
686 | static inline unsigned int cpuid_edx(unsigned int op) |
687 | { | |
688 | unsigned int eax, ebx, ecx, edx; | |
689 | ||
690 | cpuid(op, &eax, &ebx, &ecx, &edx); | |
4d46a89e | 691 | |
c758ecf6 GOC |
692 | return edx; |
693 | } | |
694 | ||
683e0253 GOC |
695 | /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */ |
696 | static inline void rep_nop(void) | |
697 | { | |
cca2e6f8 | 698 | asm volatile("rep; nop" ::: "memory"); |
683e0253 GOC |
699 | } |
700 | ||
4d46a89e IM |
701 | static inline void cpu_relax(void) |
702 | { | |
703 | rep_nop(); | |
704 | } | |
705 | ||
706 | /* Stop speculative execution: */ | |
683e0253 GOC |
707 | static inline void sync_core(void) |
708 | { | |
709 | int tmp; | |
4d46a89e | 710 | |
683e0253 | 711 | asm volatile("cpuid" : "=a" (tmp) : "0" (1) |
cca2e6f8 | 712 | : "ebx", "ecx", "edx", "memory"); |
683e0253 GOC |
713 | } |
714 | ||
cca2e6f8 JP |
715 | static inline void __monitor(const void *eax, unsigned long ecx, |
716 | unsigned long edx) | |
683e0253 | 717 | { |
4d46a89e | 718 | /* "monitor %eax, %ecx, %edx;" */ |
cca2e6f8 JP |
719 | asm volatile(".byte 0x0f, 0x01, 0xc8;" |
720 | :: "a" (eax), "c" (ecx), "d"(edx)); | |
683e0253 GOC |
721 | } |
722 | ||
723 | static inline void __mwait(unsigned long eax, unsigned long ecx) | |
724 | { | |
4d46a89e | 725 | /* "mwait %eax, %ecx;" */ |
cca2e6f8 JP |
726 | asm volatile(".byte 0x0f, 0x01, 0xc9;" |
727 | :: "a" (eax), "c" (ecx)); | |
683e0253 GOC |
728 | } |
729 | ||
730 | static inline void __sti_mwait(unsigned long eax, unsigned long ecx) | |
731 | { | |
7f424a8b | 732 | trace_hardirqs_on(); |
4d46a89e | 733 | /* "mwait %eax, %ecx;" */ |
cca2e6f8 JP |
734 | asm volatile("sti; .byte 0x0f, 0x01, 0xc9;" |
735 | :: "a" (eax), "c" (ecx)); | |
683e0253 GOC |
736 | } |
737 | ||
738 | extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx); | |
739 | ||
683e0253 GOC |
740 | extern void select_idle_routine(const struct cpuinfo_x86 *c); |
741 | ||
4d46a89e | 742 | extern unsigned long boot_option_idle_override; |
c1e3b377 | 743 | extern unsigned long idle_halt; |
da5e09a1 | 744 | extern unsigned long idle_nomwait; |
683e0253 | 745 | |
394a1505 ML |
746 | /* |
747 | * on systems with caches, caches must be flashed as the absolute | |
748 | * last instruction before going into a suspended halt. Otherwise, | |
749 | * dirty data can linger in the cache and become stale on resume, | |
750 | * leading to strange errors. | |
751 | * | |
752 | * perform a variety of operations to guarantee that the compiler | |
753 | * will not reorder instructions. wbinvd itself is serializing | |
754 | * so the processor will not reorder. | |
755 | * | |
756 | * Systems without cache can just go into halt. | |
757 | */ | |
758 | static inline void wbinvd_halt(void) | |
759 | { | |
760 | mb(); | |
761 | /* check for clflush to determine if wbinvd is legal */ | |
762 | if (cpu_has_clflush) | |
763 | asm volatile("cli; wbinvd; 1: hlt; jmp 1b" : : : "memory"); | |
764 | else | |
765 | while (1) | |
766 | halt(); | |
767 | } | |
768 | ||
1a53905a GOC |
769 | extern void enable_sep_cpu(void); |
770 | extern int sysenter_setup(void); | |
771 | ||
772 | /* Defined in head.S */ | |
4d46a89e | 773 | extern struct desc_ptr early_gdt_descr; |
1a53905a GOC |
774 | |
775 | extern void cpu_set_gdt(int); | |
776 | extern void switch_to_new_gdt(void); | |
777 | extern void cpu_init(void); | |
1a53905a | 778 | |
c2724775 MM |
779 | static inline unsigned long get_debugctlmsr(void) |
780 | { | |
781 | unsigned long debugctlmsr = 0; | |
782 | ||
783 | #ifndef CONFIG_X86_DEBUGCTLMSR | |
784 | if (boot_cpu_data.x86 < 6) | |
785 | return 0; | |
786 | #endif | |
787 | rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); | |
788 | ||
789 | return debugctlmsr; | |
790 | } | |
791 | ||
5b0e5084 JB |
792 | static inline void update_debugctlmsr(unsigned long debugctlmsr) |
793 | { | |
794 | #ifndef CONFIG_X86_DEBUGCTLMSR | |
795 | if (boot_cpu_data.x86 < 6) | |
796 | return; | |
797 | #endif | |
798 | wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); | |
799 | } | |
800 | ||
4d46a89e IM |
801 | /* |
802 | * from system description table in BIOS. Mostly for MCA use, but | |
803 | * others may find it useful: | |
804 | */ | |
805 | extern unsigned int machine_id; | |
806 | extern unsigned int machine_submodel_id; | |
807 | extern unsigned int BIOS_revision; | |
1a53905a | 808 | |
4d46a89e IM |
809 | /* Boot loader type from the setup header: */ |
810 | extern int bootloader_type; | |
1a53905a | 811 | |
4d46a89e | 812 | extern char ignore_fpu_irq; |
683e0253 GOC |
813 | |
814 | #define HAVE_ARCH_PICK_MMAP_LAYOUT 1 | |
815 | #define ARCH_HAS_PREFETCHW | |
816 | #define ARCH_HAS_SPINLOCK_PREFETCH | |
817 | ||
ae2e15eb | 818 | #ifdef CONFIG_X86_32 |
4d46a89e IM |
819 | # define BASE_PREFETCH ASM_NOP4 |
820 | # define ARCH_HAS_PREFETCH | |
ae2e15eb | 821 | #else |
4d46a89e | 822 | # define BASE_PREFETCH "prefetcht0 (%1)" |
ae2e15eb GOC |
823 | #endif |
824 | ||
4d46a89e IM |
825 | /* |
826 | * Prefetch instructions for Pentium III (+) and AMD Athlon (+) | |
827 | * | |
828 | * It's not worth to care about 3dnow prefetches for the K6 | |
829 | * because they are microcoded there and very slow. | |
830 | */ | |
ae2e15eb GOC |
831 | static inline void prefetch(const void *x) |
832 | { | |
833 | alternative_input(BASE_PREFETCH, | |
834 | "prefetchnta (%1)", | |
835 | X86_FEATURE_XMM, | |
836 | "r" (x)); | |
837 | } | |
838 | ||
4d46a89e IM |
839 | /* |
840 | * 3dnow prefetch to get an exclusive cache line. | |
841 | * Useful for spinlocks to avoid one state transition in the | |
842 | * cache coherency protocol: | |
843 | */ | |
ae2e15eb GOC |
844 | static inline void prefetchw(const void *x) |
845 | { | |
846 | alternative_input(BASE_PREFETCH, | |
847 | "prefetchw (%1)", | |
848 | X86_FEATURE_3DNOW, | |
849 | "r" (x)); | |
850 | } | |
851 | ||
4d46a89e IM |
852 | static inline void spin_lock_prefetch(const void *x) |
853 | { | |
854 | prefetchw(x); | |
855 | } | |
856 | ||
2f66dcc9 GOC |
857 | #ifdef CONFIG_X86_32 |
858 | /* | |
859 | * User space process size: 3GB (default). | |
860 | */ | |
4d46a89e IM |
861 | #define TASK_SIZE PAGE_OFFSET |
862 | #define STACK_TOP TASK_SIZE | |
863 | #define STACK_TOP_MAX STACK_TOP | |
864 | ||
865 | #define INIT_THREAD { \ | |
866 | .sp0 = sizeof(init_stack) + (long)&init_stack, \ | |
867 | .vm86_info = NULL, \ | |
868 | .sysenter_cs = __KERNEL_CS, \ | |
869 | .io_bitmap_ptr = NULL, \ | |
870 | .fs = __KERNEL_PERCPU, \ | |
2f66dcc9 GOC |
871 | } |
872 | ||
873 | /* | |
874 | * Note that the .io_bitmap member must be extra-big. This is because | |
875 | * the CPU will access an additional byte beyond the end of the IO | |
876 | * permission bitmap. The extra byte must be all 1 bits, and must | |
877 | * be within the limit. | |
878 | */ | |
4d46a89e IM |
879 | #define INIT_TSS { \ |
880 | .x86_tss = { \ | |
2f66dcc9 | 881 | .sp0 = sizeof(init_stack) + (long)&init_stack, \ |
4d46a89e IM |
882 | .ss0 = __KERNEL_DS, \ |
883 | .ss1 = __KERNEL_CS, \ | |
884 | .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \ | |
885 | }, \ | |
886 | .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \ | |
2f66dcc9 GOC |
887 | } |
888 | ||
2f66dcc9 GOC |
889 | extern unsigned long thread_saved_pc(struct task_struct *tsk); |
890 | ||
891 | #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long)) | |
892 | #define KSTK_TOP(info) \ | |
893 | ({ \ | |
894 | unsigned long *__ptr = (unsigned long *)(info); \ | |
895 | (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \ | |
896 | }) | |
897 | ||
898 | /* | |
899 | * The below -8 is to reserve 8 bytes on top of the ring0 stack. | |
900 | * This is necessary to guarantee that the entire "struct pt_regs" | |
901 | * is accessable even if the CPU haven't stored the SS/ESP registers | |
902 | * on the stack (interrupt gate does not save these registers | |
903 | * when switching to the same priv ring). | |
904 | * Therefore beware: accessing the ss/esp fields of the | |
905 | * "struct pt_regs" is possible, but they may contain the | |
906 | * completely wrong values. | |
907 | */ | |
908 | #define task_pt_regs(task) \ | |
909 | ({ \ | |
910 | struct pt_regs *__regs__; \ | |
911 | __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \ | |
912 | __regs__ - 1; \ | |
913 | }) | |
914 | ||
4d46a89e | 915 | #define KSTK_ESP(task) (task_pt_regs(task)->sp) |
2f66dcc9 GOC |
916 | |
917 | #else | |
918 | /* | |
919 | * User space process size. 47bits minus one guard page. | |
920 | */ | |
a5ae1c37 | 921 | #define TASK_SIZE64 ((1UL << 47) - PAGE_SIZE) |
2f66dcc9 GOC |
922 | |
923 | /* This decides where the kernel will search for a free chunk of vm | |
924 | * space during mmap's. | |
925 | */ | |
4d46a89e IM |
926 | #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \ |
927 | 0xc0000000 : 0xFFFFe000) | |
2f66dcc9 | 928 | |
4d46a89e IM |
929 | #define TASK_SIZE (test_thread_flag(TIF_IA32) ? \ |
930 | IA32_PAGE_OFFSET : TASK_SIZE64) | |
931 | #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? \ | |
932 | IA32_PAGE_OFFSET : TASK_SIZE64) | |
2f66dcc9 | 933 | |
922a70d3 DH |
934 | #define STACK_TOP TASK_SIZE |
935 | #define STACK_TOP_MAX TASK_SIZE64 | |
936 | ||
2f66dcc9 GOC |
937 | #define INIT_THREAD { \ |
938 | .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \ | |
939 | } | |
940 | ||
941 | #define INIT_TSS { \ | |
942 | .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \ | |
943 | } | |
944 | ||
2f66dcc9 GOC |
945 | /* |
946 | * Return saved PC of a blocked thread. | |
947 | * What is this good for? it will be always the scheduler or ret_from_fork. | |
948 | */ | |
4d46a89e | 949 | #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8)) |
2f66dcc9 | 950 | |
4d46a89e IM |
951 | #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1) |
952 | #define KSTK_ESP(tsk) -1 /* sorry. doesn't work for syscall. */ | |
2f66dcc9 GOC |
953 | #endif /* CONFIG_X86_64 */ |
954 | ||
513ad84b IM |
955 | extern void start_thread(struct pt_regs *regs, unsigned long new_ip, |
956 | unsigned long new_sp); | |
957 | ||
4d46a89e IM |
958 | /* |
959 | * This decides where the kernel will search for a free chunk of vm | |
683e0253 GOC |
960 | * space during mmap's. |
961 | */ | |
962 | #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3)) | |
963 | ||
4d46a89e | 964 | #define KSTK_EIP(task) (task_pt_regs(task)->ip) |
683e0253 | 965 | |
529e25f6 EB |
966 | /* Get/set a process' ability to use the timestamp counter instruction */ |
967 | #define GET_TSC_CTL(adr) get_tsc_mode((adr)) | |
968 | #define SET_TSC_CTL(val) set_tsc_mode((val)) | |
969 | ||
970 | extern int get_tsc_mode(unsigned long adr); | |
971 | extern int set_tsc_mode(unsigned int val); | |
972 | ||
1965aae3 | 973 | #endif /* _ASM_X86_PROCESSOR_H */ |