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Merge branch 'oprofile-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / arch / x86 / include / asm / processor.h
CommitLineData
1965aae3
PA		 1#ifndef _ASM_X86_PROCESSOR_H
2#define _ASM_X86_PROCESSOR_H
c758ecf6 3
053de044
GOC		 4#include <asm/processor-flags.h>
5
683e0253
GOC		 6/* Forward declaration, a strange C thing */
7struct task_struct;
8struct mm_struct;
9
2f66dcc9
GOC		 10#include <asm/vm86.h>
11#include <asm/math_emu.h>
12#include <asm/segment.h>
2f66dcc9
GOC		 13#include <asm/types.h>
14#include <asm/sigcontext.h>
15#include <asm/current.h>
16#include <asm/cpufeature.h>
c72dcf83 17#include <asm/system.h>
2f66dcc9 18#include <asm/page.h>
54321d94 19#include <asm/pgtable_types.h>
5300db88 20#include <asm/percpu.h>
2f66dcc9
GOC		 21#include <asm/msr.h>
22#include <asm/desc_defs.h>
bd61643e 23#include <asm/nops.h>
93fa7636 24#include <asm/ds.h>
4d46a89e 25
2f66dcc9 26#include <linux/personality.h>
5300db88
GOC		 27#include <linux/cpumask.h>
28#include <linux/cache.h>
2f66dcc9
GOC		 29#include <linux/threads.h>
30#include <linux/init.h>
c72dcf83 31
0ccb8acc
GOC		 32/*
33 * Default implementation of macro that returns current
34 * instruction pointer ("program counter").
35 */
36static inline void *current_text_addr(void)
37{
38 void *pc;
4d46a89e
IM		 39
40 asm volatile("mov $1f, %0; 1:":"=r" (pc));
41
0ccb8acc
GOC		 42 return pc;
43}
44
dbcb4660 45#ifdef CONFIG_X86_VSMP
4d46a89e
IM		 46# define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
47# define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
dbcb4660 48#else
4d46a89e
IM		 49# define ARCH_MIN_TASKALIGN 16
50# define ARCH_MIN_MMSTRUCT_ALIGN 0
dbcb4660
GOC		 51#endif
52
5300db88
GOC		 53/*
54 * CPU type and hardware bug flags. Kept separately for each CPU.
55 * Members of this structure are referenced in head.S, so think twice
56 * before touching them. [mj]
57 */
58
59struct cpuinfo_x86 {
4d46a89e
IM		 60 __u8 x86; /* CPU family */
61 __u8 x86_vendor; /* CPU vendor */
62 __u8 x86_model;
63 __u8 x86_mask;
5300db88 64#ifdef CONFIG_X86_32
4d46a89e
IM		 65 char wp_works_ok; /* It doesn't on 386's */
66
67 /* Problems on some 486Dx4's and old 386's: */
68 char hlt_works_ok;
69 char hard_math;
70 char rfu;
71 char fdiv_bug;
72 char f00f_bug;
73 char coma_bug;
74 char pad0;
5300db88 75#else
4d46a89e 76 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
b1882e68 77 int x86_tlbsize;
13c6c532 78#endif
4d46a89e
IM		 79 __u8 x86_virt_bits;
80 __u8 x86_phys_bits;
81 /* CPUID returned core id bits: */
82 __u8 x86_coreid_bits;
83 /* Max extended CPUID function supported: */
84 __u32 extended_cpuid_level;
4d46a89e
IM		 85 /* Maximum supported CPUID level, -1=no CPUID: */
86 int cpuid_level;
87 __u32 x86_capability[NCAPINTS];
88 char x86_vendor_id[16];
89 char x86_model_id[64];
90 /* in KB - valid for CPUS which support this call: */
91 int x86_cache_size;
92 int x86_cache_alignment; /* In bytes */
93 int x86_power;
94 unsigned long loops_per_jiffy;
5300db88 95#ifdef CONFIG_SMP
4d46a89e 96 /* cpus sharing the last level cache: */
155dd720 97 cpumask_var_t llc_shared_map;
5300db88 98#endif
4d46a89e
IM		 99 /* cpuid returned max cores value: */
100 u16 x86_max_cores;
101 u16 apicid;
01aaea1a 102 u16 initial_apicid;
4d46a89e 103 u16 x86_clflush_size;
5300db88 104#ifdef CONFIG_SMP
4d46a89e
IM		 105 /* number of cores as seen by the OS: */
106 u16 booted_cores;
107 /* Physical processor id: */
108 u16 phys_proc_id;
109 /* Core id: */
110 u16 cpu_core_id;
111 /* Index into per_cpu list: */
112 u16 cpu_index;
5300db88 113#endif
88b094fb 114 unsigned int x86_hyper_vendor;
5300db88
GOC		 115} __attribute__((__aligned__(SMP_CACHE_BYTES)));
116
4d46a89e
IM		 117#define X86_VENDOR_INTEL 0
118#define X86_VENDOR_CYRIX 1
119#define X86_VENDOR_AMD 2
120#define X86_VENDOR_UMC 3
4d46a89e
IM		 121#define X86_VENDOR_CENTAUR 5
122#define X86_VENDOR_TRANSMETA 7
123#define X86_VENDOR_NSC 8
124#define X86_VENDOR_NUM 9
125
126#define X86_VENDOR_UNKNOWN 0xff
5300db88 127
88b094fb
AK		 128#define X86_HYPER_VENDOR_NONE 0
129#define X86_HYPER_VENDOR_VMWARE 1
130
1a53905a
GOC		 131/*
132 * capabilities of CPUs
133 */
4d46a89e
IM		 134extern struct cpuinfo_x86 boot_cpu_data;
135extern struct cpuinfo_x86 new_cpu_data;
136
137extern struct tss_struct doublefault_tss;
3e0c3737
YL		 138extern __u32 cpu_caps_cleared[NCAPINTS];
139extern __u32 cpu_caps_set[NCAPINTS];
5300db88
GOC		 140
141#ifdef CONFIG_SMP
9b8de747 142DECLARE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
5300db88 143#define cpu_data(cpu) per_cpu(cpu_info, cpu)
94a1e869 144#define current_cpu_data __get_cpu_var(cpu_info)
5300db88
GOC		 145#else
146#define cpu_data(cpu) boot_cpu_data
147#define current_cpu_data boot_cpu_data
148#endif
149
1c6c727d
JS		 150extern const struct seq_operations cpuinfo_op;
151
3d3f487c
GC		 152static inline int hlt_works(int cpu)
153{
154#ifdef CONFIG_X86_32
155 return cpu_data(cpu).hlt_works_ok;
156#else
157 return 1;
158#endif
159}
160
4d46a89e
IM		 161#define cache_line_size() (boot_cpu_data.x86_cache_alignment)
162
163extern void cpu_detect(struct cpuinfo_x86 *c);
1a53905a 164
8fd329a1
JS		 165extern struct pt_regs *idle_regs(struct pt_regs *);
166
f580366f 167extern void early_cpu_init(void);
1a53905a
GOC		 168extern void identify_boot_cpu(void);
169extern void identify_secondary_cpu(struct cpuinfo_x86 *);
5300db88
GOC		 170extern void print_cpu_info(struct cpuinfo_x86 *);
171extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
172extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
173extern unsigned short num_cache_leaves;
174
bbb65d2d 175extern void detect_extended_topology(struct cpuinfo_x86 *c);
1a53905a 176extern void detect_ht(struct cpuinfo_x86 *c);
1a53905a 177
c758ecf6 178static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
4d46a89e 179 unsigned int *ecx, unsigned int *edx)
c758ecf6
GOC		 180{
181 /* ecx is often an input as well as an output. */
cca2e6f8
JP		 182 asm("cpuid"
183 : "=a" (*eax),
184 "=b" (*ebx),
185 "=c" (*ecx),
186 "=d" (*edx)
187 : "0" (*eax), "2" (*ecx));
c758ecf6
GOC		 188}
189
c72dcf83
GOC		 190static inline void load_cr3(pgd_t *pgdir)
191{
192 write_cr3(__pa(pgdir));
193}
c758ecf6 194
ca241c75
GOC		 195#ifdef CONFIG_X86_32
196/* This is the TSS defined by the hardware. */
197struct x86_hw_tss {
4d46a89e
IM		 198 unsigned short back_link, __blh;
199 unsigned long sp0;
200 unsigned short ss0, __ss0h;
201 unsigned long sp1;
202 /* ss1 caches MSR_IA32_SYSENTER_CS: */
203 unsigned short ss1, __ss1h;
204 unsigned long sp2;
205 unsigned short ss2, __ss2h;
206 unsigned long __cr3;
207 unsigned long ip;
208 unsigned long flags;
209 unsigned long ax;
210 unsigned long cx;
211 unsigned long dx;
212 unsigned long bx;
213 unsigned long sp;
214 unsigned long bp;
215 unsigned long si;
216 unsigned long di;
217 unsigned short es, __esh;
218 unsigned short cs, __csh;
219 unsigned short ss, __ssh;
220 unsigned short ds, __dsh;
221 unsigned short fs, __fsh;
222 unsigned short gs, __gsh;
223 unsigned short ldt, __ldth;
224 unsigned short trace;
225 unsigned short io_bitmap_base;
226
ca241c75
GOC		 227} __attribute__((packed));
228#else
229struct x86_hw_tss {
4d46a89e
IM		 230 u32 reserved1;
231 u64 sp0;
232 u64 sp1;
233 u64 sp2;
234 u64 reserved2;
235 u64 ist[7];
236 u32 reserved3;
237 u32 reserved4;
238 u16 reserved5;
239 u16 io_bitmap_base;
240
ca241c75
GOC		 241} __attribute__((packed)) ____cacheline_aligned;
242#endif
243
244/*
4d46a89e 245 * IO-bitmap sizes:
ca241c75 246 */
4d46a89e
IM		 247#define IO_BITMAP_BITS 65536
248#define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
249#define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
250#define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
251#define INVALID_IO_BITMAP_OFFSET 0x8000
ca241c75
GOC		 252
253struct tss_struct {
4d46a89e
IM		 254 /*
255 * The hardware state:
256 */
257 struct x86_hw_tss x86_tss;
ca241c75
GOC		 258
259 /*
260 * The extra 1 is there because the CPU will access an
261 * additional byte beyond the end of the IO permission
262 * bitmap. The extra byte must be all 1 bits, and must
263 * be within the limit.
264 */
4d46a89e 265 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
4d46a89e 266
ca241c75 267 /*
4d46a89e 268 * .. and then another 0x100 bytes for the emergency kernel stack:
ca241c75 269 */
4d46a89e
IM		 270 unsigned long stack[64];
271
84e65b0a 272} ____cacheline_aligned;
ca241c75 273
9b8de747 274DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss);
ca241c75 275
4d46a89e
IM		 276/*
277 * Save the original ist values for checking stack pointers during debugging
278 */
1a53905a 279struct orig_ist {
4d46a89e 280 unsigned long ist[7];
1a53905a
GOC		 281};
282
99f8ecdf 283#define MXCSR_DEFAULT 0x1f80
46265df0 284
99f8ecdf 285struct i387_fsave_struct {
ca9cda2f
IM		 286 u32 cwd; /* FPU Control Word */
287 u32 swd; /* FPU Status Word */
288 u32 twd; /* FPU Tag Word */
289 u32 fip; /* FPU IP Offset */
290 u32 fcs; /* FPU IP Selector */
291 u32 foo; /* FPU Operand Pointer Offset */
292 u32 fos; /* FPU Operand Pointer Selector */
293
294 /* 8*10 bytes for each FP-reg = 80 bytes: */
4d46a89e 295 u32 st_space[20];
ca9cda2f
IM		 296
297 /* Software status information [not touched by FSAVE ]: */
4d46a89e 298 u32 status;
46265df0
GOC		 299};
300
46265df0 301struct i387_fxsave_struct {
ca9cda2f
IM		 302 u16 cwd; /* Control Word */
303 u16 swd; /* Status Word */
304 u16 twd; /* Tag Word */
305 u16 fop; /* Last Instruction Opcode */
99f8ecdf
RM		 306 union {
307 struct {
ca9cda2f
IM		 308 u64 rip; /* Instruction Pointer */
309 u64 rdp; /* Data Pointer */
99f8ecdf
RM		 310 };
311 struct {
ca9cda2f
IM		 312 u32 fip; /* FPU IP Offset */
313 u32 fcs; /* FPU IP Selector */
314 u32 foo; /* FPU Operand Offset */
315 u32 fos; /* FPU Operand Selector */
99f8ecdf
RM		 316 };
317 };
ca9cda2f
IM		 318 u32 mxcsr; /* MXCSR Register State */
319 u32 mxcsr_mask; /* MXCSR Mask */
320
321 /* 8*16 bytes for each FP-reg = 128 bytes: */
4d46a89e 322 u32 st_space[32];
ca9cda2f
IM		 323
324 /* 16*16 bytes for each XMM-reg = 256 bytes: */
4d46a89e 325 u32 xmm_space[64];
ca9cda2f 326
bdd8caba
SS		 327 u32 padding[12];
328
329 union {
330 u32 padding1[12];
331 u32 sw_reserved[12];
332 };
4d46a89e 333
46265df0
GOC		 334} __attribute__((aligned(16)));
335
99f8ecdf 336struct i387_soft_struct {
4d46a89e
IM		 337 u32 cwd;
338 u32 swd;
339 u32 twd;
340 u32 fip;
341 u32 fcs;
342 u32 foo;
343 u32 fos;
344 /* 8*10 bytes for each FP-reg = 80 bytes: */
345 u32 st_space[20];
346 u8 ftop;
347 u8 changed;
348 u8 lookahead;
349 u8 no_update;
350 u8 rm;
351 u8 alimit;
ae6af41f 352 struct math_emu_info *info;
4d46a89e 353 u32 entry_eip;
99f8ecdf
RM		 354};
355
a30469e7
SS		 356struct ymmh_struct {
357 /* 16 * 16 bytes for each YMMH-reg = 256 bytes */
358 u32 ymmh_space[64];
359};
360
dc1e35c6
SS		 361struct xsave_hdr_struct {
362 u64 xstate_bv;
363 u64 reserved1[2];
364 u64 reserved2[5];
365} __attribute__((packed));
366
367struct xsave_struct {
368 struct i387_fxsave_struct i387;
369 struct xsave_hdr_struct xsave_hdr;
a30469e7 370 struct ymmh_struct ymmh;
dc1e35c6
SS		 371 /* new processor state extensions will go here */
372} __attribute__ ((packed, aligned (64)));
373
61c4628b 374union thread_xstate {
99f8ecdf 375 struct i387_fsave_struct fsave;
46265df0 376 struct i387_fxsave_struct fxsave;
4d46a89e 377 struct i387_soft_struct soft;
b359e8a4 378 struct xsave_struct xsave;
46265df0
GOC		 379};
380
fe676203 381#ifdef CONFIG_X86_64
2f66dcc9 382DECLARE_PER_CPU(struct orig_ist, orig_ist);
26f80bd6 383
947e76cd
BG		 384union irq_stack_union {
385 char irq_stack[IRQ_STACK_SIZE];
386 /*
387 * GCC hardcodes the stack canary as %gs:40. Since the
388 * irq_stack is the object at %gs:0, we reserve the bottom
389 * 48 bytes of the irq stack for the canary.
390 */
391 struct {
392 char gs_base[40];
393 unsigned long stack_canary;
394 };
395};
396
9b8de747 397DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union);
2add8e23
BG		 398DECLARE_INIT_PER_CPU(irq_stack_union);
399
26f80bd6 400DECLARE_PER_CPU(char *, irq_stack_ptr);
9766cdbc
JSR		 401DECLARE_PER_CPU(unsigned int, irq_count);
402extern unsigned long kernel_eflags;
403extern asmlinkage void ignore_sysret(void);
60a5317f
TH		 404#else /* X86_64 */
405#ifdef CONFIG_CC_STACKPROTECTOR
406DECLARE_PER_CPU(unsigned long, stack_canary);
96a388de 407#endif
60a5317f 408#endif /* X86_64 */
c758ecf6 409
61c4628b 410extern unsigned int xstate_size;
aa283f49
SS		 411extern void free_thread_xstate(struct task_struct *);
412extern struct kmem_cache *task_xstate_cachep;
683e0253 413
cb38d377 414struct thread_struct {
4d46a89e
IM		 415 /* Cached TLS descriptors: */
416 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
417 unsigned long sp0;
418 unsigned long sp;
cb38d377 419#ifdef CONFIG_X86_32
4d46a89e 420 unsigned long sysenter_cs;
cb38d377 421#else
4d46a89e
IM		 422 unsigned long usersp; /* Copy from PDA */
423 unsigned short es;
424 unsigned short ds;
425 unsigned short fsindex;
426 unsigned short gsindex;
cb38d377 427#endif
0c23590f 428#ifdef CONFIG_X86_32
4d46a89e 429 unsigned long ip;
0c23590f 430#endif
d756f4ad 431#ifdef CONFIG_X86_64
4d46a89e 432 unsigned long fs;
d756f4ad 433#endif
4d46a89e
IM		 434 unsigned long gs;
435 /* Hardware debugging registers: */
436 unsigned long debugreg0;
437 unsigned long debugreg1;
438 unsigned long debugreg2;
439 unsigned long debugreg3;
440 unsigned long debugreg6;
441 unsigned long debugreg7;
442 /* Fault info: */
443 unsigned long cr2;
444 unsigned long trap_no;
445 unsigned long error_code;
61c4628b
SS		 446 /* floating point and extended processor state */
447 union thread_xstate *xstate;
cb38d377 448#ifdef CONFIG_X86_32
4d46a89e 449 /* Virtual 86 mode info */
cb38d377
GOC		 450 struct vm86_struct __user *vm86_info;
451 unsigned long screen_bitmap;
4d46a89e
IM		 452 unsigned long v86flags;
453 unsigned long v86mask;
454 unsigned long saved_sp0;
455 unsigned int saved_fs;
456 unsigned int saved_gs;
cb38d377 457#endif
4d46a89e
IM		 458 /* IO permissions: */
459 unsigned long *io_bitmap_ptr;
460 unsigned long iopl;
461 /* Max allowed port in the bitmap, in bytes: */
462 unsigned io_bitmap_max;
cb38d377
GOC		 463/* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set. */
464 unsigned long debugctlmsr;
93fa7636
MM		 465#ifdef CONFIG_X86_DS
466/* Debug Store context; see include/asm-x86/ds.h; goes into MSR_IA32_DS_AREA */
467 struct ds_context *ds_ctx;
468#endif /* CONFIG_X86_DS */
469#ifdef CONFIG_X86_PTRACE_BTS
470/* the signal to send on a bts buffer overflow */
471 unsigned int bts_ovfl_signal;
472#endif /* CONFIG_X86_PTRACE_BTS */
cb38d377
GOC		 473};
474
1b46cbe0
GOC		 475static inline unsigned long native_get_debugreg(int regno)
476{
4d46a89e 477 unsigned long val = 0; /* Damn you, gcc! */
1b46cbe0
GOC		 478
479 switch (regno) {
480 case 0:
cca2e6f8
JP		 481 asm("mov %%db0, %0" :"=r" (val));
482 break;
1b46cbe0 483 case 1:
cca2e6f8
JP		 484 asm("mov %%db1, %0" :"=r" (val));
485 break;
1b46cbe0 486 case 2:
cca2e6f8
JP		 487 asm("mov %%db2, %0" :"=r" (val));
488 break;
1b46cbe0 489 case 3:
cca2e6f8
JP		 490 asm("mov %%db3, %0" :"=r" (val));
491 break;
1b46cbe0 492 case 6:
cca2e6f8
JP		 493 asm("mov %%db6, %0" :"=r" (val));
494 break;
1b46cbe0 495 case 7:
cca2e6f8
JP		 496 asm("mov %%db7, %0" :"=r" (val));
497 break;
1b46cbe0
GOC		 498 default:
499 BUG();
500 }
501 return val;
502}
503
504static inline void native_set_debugreg(int regno, unsigned long value)
505{
506 switch (regno) {
507 case 0:
4d46a89e 508 asm("mov %0, %%db0" ::"r" (value));
1b46cbe0
GOC		 509 break;
510 case 1:
4d46a89e 511 asm("mov %0, %%db1" ::"r" (value));
1b46cbe0
GOC		 512 break;
513 case 2:
4d46a89e 514 asm("mov %0, %%db2" ::"r" (value));
1b46cbe0
GOC		 515 break;
516 case 3:
4d46a89e 517 asm("mov %0, %%db3" ::"r" (value));
1b46cbe0
GOC		 518 break;
519 case 6:
4d46a89e 520 asm("mov %0, %%db6" ::"r" (value));
1b46cbe0
GOC		 521 break;
522 case 7:
4d46a89e 523 asm("mov %0, %%db7" ::"r" (value));
1b46cbe0
GOC		 524 break;
525 default:
526 BUG();
527 }
528}
529
62d7d7ed
GOC		 530/*
531 * Set IOPL bits in EFLAGS from given mask
532 */
533static inline void native_set_iopl_mask(unsigned mask)
534{
535#ifdef CONFIG_X86_32
536 unsigned int reg;
4d46a89e 537
cca2e6f8
JP		 538 asm volatile ("pushfl;"
539 "popl %0;"
540 "andl %1, %0;"
541 "orl %2, %0;"
542 "pushl %0;"
543 "popfl"
544 : "=&r" (reg)
545 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
62d7d7ed
GOC		 546#endif
547}
548
4d46a89e
IM		 549static inline void
550native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
7818a1e0
GOC		 551{
552 tss->x86_tss.sp0 = thread->sp0;
553#ifdef CONFIG_X86_32
4d46a89e 554 /* Only happens when SEP is enabled, no need to test "SEP"arately: */
7818a1e0
GOC		 555 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
556 tss->x86_tss.ss1 = thread->sysenter_cs;
557 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
558 }
559#endif
560}
1b46cbe0 561
e801f864
GOC		 562static inline void native_swapgs(void)
563{
564#ifdef CONFIG_X86_64
565 asm volatile("swapgs" ::: "memory");
566#endif
567}
568
7818a1e0
GOC		 569#ifdef CONFIG_PARAVIRT
570#include <asm/paravirt.h>
571#else
4d46a89e
IM		 572#define __cpuid native_cpuid
573#define paravirt_enabled() 0
1b46cbe0
GOC		 574
575/*
576 * These special macros can be used to get or set a debugging register
577 */
578#define get_debugreg(var, register) \
579 (var) = native_get_debugreg(register)
580#define set_debugreg(value, register) \
581 native_set_debugreg(register, value)
582
cca2e6f8
JP		 583static inline void load_sp0(struct tss_struct *tss,
584 struct thread_struct *thread)
7818a1e0
GOC		 585{
586 native_load_sp0(tss, thread);
587}
588
62d7d7ed 589#define set_iopl_mask native_set_iopl_mask
1b46cbe0
GOC		 590#endif /* CONFIG_PARAVIRT */
591
592/*
593 * Save the cr4 feature set we're using (ie
594 * Pentium 4MB enable and PPro Global page
595 * enable), so that any CPU's that boot up
596 * after us can get the correct flags.
597 */
4d46a89e 598extern unsigned long mmu_cr4_features;
1b46cbe0
GOC		 599
600static inline void set_in_cr4(unsigned long mask)
601{
602 unsigned cr4;
4d46a89e 603
1b46cbe0
GOC		 604 mmu_cr4_features |= mask;
605 cr4 = read_cr4();
606 cr4 |= mask;
607 write_cr4(cr4);
608}
609
610static inline void clear_in_cr4(unsigned long mask)
611{
612 unsigned cr4;
4d46a89e 613
1b46cbe0
GOC		 614 mmu_cr4_features &= ~mask;
615 cr4 = read_cr4();
616 cr4 &= ~mask;
617 write_cr4(cr4);
618}
619
fc87e906 620typedef struct {
4d46a89e 621 unsigned long seg;
fc87e906
GOC		 622} mm_segment_t;
623
624
683e0253
GOC		 625/*
626 * create a kernel thread without removing it from tasklists
627 */
628extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
629
630/* Free all resources held by a thread. */
631extern void release_thread(struct task_struct *);
632
4d46a89e 633/* Prepare to copy thread state - unlazy all lazy state */
683e0253 634extern void prepare_to_copy(struct task_struct *tsk);
1b46cbe0 635
683e0253 636unsigned long get_wchan(struct task_struct *p);
c758ecf6
GOC		 637
638/*
639 * Generic CPUID function
640 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
641 * resulting in stale register contents being returned.
642 */
643static inline void cpuid(unsigned int op,
644 unsigned int *eax, unsigned int *ebx,
645 unsigned int *ecx, unsigned int *edx)
646{
647 *eax = op;
648 *ecx = 0;
649 __cpuid(eax, ebx, ecx, edx);
650}
651
652/* Some CPUID calls want 'count' to be placed in ecx */
653static inline void cpuid_count(unsigned int op, int count,
654 unsigned int *eax, unsigned int *ebx,
655 unsigned int *ecx, unsigned int *edx)
656{
657 *eax = op;
658 *ecx = count;
659 __cpuid(eax, ebx, ecx, edx);
660}
661
662/*
663 * CPUID functions returning a single datum
664 */
665static inline unsigned int cpuid_eax(unsigned int op)
666{
667 unsigned int eax, ebx, ecx, edx;
668
669 cpuid(op, &eax, &ebx, &ecx, &edx);
4d46a89e 670
c758ecf6
GOC		 671 return eax;
672}
4d46a89e 673
c758ecf6
GOC		 674static inline unsigned int cpuid_ebx(unsigned int op)
675{
676 unsigned int eax, ebx, ecx, edx;
677
678 cpuid(op, &eax, &ebx, &ecx, &edx);
4d46a89e 679
c758ecf6
GOC		 680 return ebx;
681}
4d46a89e 682
c758ecf6
GOC		 683static inline unsigned int cpuid_ecx(unsigned int op)
684{
685 unsigned int eax, ebx, ecx, edx;
686
687 cpuid(op, &eax, &ebx, &ecx, &edx);
4d46a89e 688
c758ecf6
GOC		 689 return ecx;
690}
4d46a89e 691
c758ecf6
GOC		 692static inline unsigned int cpuid_edx(unsigned int op)
693{
694 unsigned int eax, ebx, ecx, edx;
695
696 cpuid(op, &eax, &ebx, &ecx, &edx);
4d46a89e 697
c758ecf6
GOC		 698 return edx;
699}
700
683e0253
GOC		 701/* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
702static inline void rep_nop(void)
703{
cca2e6f8 704 asm volatile("rep; nop" ::: "memory");
683e0253
GOC		 705}
706
4d46a89e
IM		 707static inline void cpu_relax(void)
708{
709 rep_nop();
710}
711
712/* Stop speculative execution: */
683e0253
GOC		 713static inline void sync_core(void)
714{
715 int tmp;
4d46a89e 716
683e0253 717 asm volatile("cpuid" : "=a" (tmp) : "0" (1)
cca2e6f8 718 : "ebx", "ecx", "edx", "memory");
683e0253
GOC		 719}
720
cca2e6f8
JP		 721static inline void __monitor(const void *eax, unsigned long ecx,
722 unsigned long edx)
683e0253 723{
4d46a89e 724 /* "monitor %eax, %ecx, %edx;" */
cca2e6f8
JP		 725 asm volatile(".byte 0x0f, 0x01, 0xc8;"
726 :: "a" (eax), "c" (ecx), "d"(edx));
683e0253
GOC		 727}
728
729static inline void __mwait(unsigned long eax, unsigned long ecx)
730{
4d46a89e 731 /* "mwait %eax, %ecx;" */
cca2e6f8
JP		 732 asm volatile(".byte 0x0f, 0x01, 0xc9;"
733 :: "a" (eax), "c" (ecx));
683e0253
GOC		 734}
735
736static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
737{
7f424a8b 738 trace_hardirqs_on();
4d46a89e 739 /* "mwait %eax, %ecx;" */
cca2e6f8
JP		 740 asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
741 :: "a" (eax), "c" (ecx));
683e0253
GOC		 742}
743
744extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
745
683e0253 746extern void select_idle_routine(const struct cpuinfo_x86 *c);
30e1e6d1 747extern void init_c1e_mask(void);
683e0253 748
4d46a89e 749extern unsigned long boot_option_idle_override;
c1e3b377 750extern unsigned long idle_halt;
da5e09a1 751extern unsigned long idle_nomwait;
683e0253 752
394a1505
ML		 753/*
754 * on systems with caches, caches must be flashed as the absolute
755 * last instruction before going into a suspended halt. Otherwise,
756 * dirty data can linger in the cache and become stale on resume,
757 * leading to strange errors.
758 *
759 * perform a variety of operations to guarantee that the compiler
760 * will not reorder instructions. wbinvd itself is serializing
761 * so the processor will not reorder.
762 *
763 * Systems without cache can just go into halt.
764 */
765static inline void wbinvd_halt(void)
766{
767 mb();
768 /* check for clflush to determine if wbinvd is legal */
769 if (cpu_has_clflush)
770 asm volatile("cli; wbinvd; 1: hlt; jmp 1b" : : : "memory");
771 else
772 while (1)
773 halt();
774}
775
1a53905a
GOC		 776extern void enable_sep_cpu(void);
777extern int sysenter_setup(void);
778
779/* Defined in head.S */
4d46a89e 780extern struct desc_ptr early_gdt_descr;
1a53905a
GOC		 781
782extern void cpu_set_gdt(int);
552be871 783extern void switch_to_new_gdt(int);
11e3a840 784extern void load_percpu_segment(int);
1a53905a 785extern void cpu_init(void);
1a53905a 786
c2724775
MM		 787static inline unsigned long get_debugctlmsr(void)
788{
789 unsigned long debugctlmsr = 0;
790
791#ifndef CONFIG_X86_DEBUGCTLMSR
792 if (boot_cpu_data.x86 < 6)
793 return 0;
794#endif
795 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
796
797 return debugctlmsr;
798}
799
5b0e5084
JB		 800static inline void update_debugctlmsr(unsigned long debugctlmsr)
801{
802#ifndef CONFIG_X86_DEBUGCTLMSR
803 if (boot_cpu_data.x86 < 6)
804 return;
805#endif
806 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
807}
808
4d46a89e
IM		 809/*
810 * from system description table in BIOS. Mostly for MCA use, but
811 * others may find it useful:
812 */
813extern unsigned int machine_id;
814extern unsigned int machine_submodel_id;
815extern unsigned int BIOS_revision;
1a53905a 816
4d46a89e
IM		 817/* Boot loader type from the setup header: */
818extern int bootloader_type;
5031296c 819extern int bootloader_version;
1a53905a 820
4d46a89e 821extern char ignore_fpu_irq;
683e0253
GOC		 822
823#define HAVE_ARCH_PICK_MMAP_LAYOUT 1
824#define ARCH_HAS_PREFETCHW
825#define ARCH_HAS_SPINLOCK_PREFETCH
826
ae2e15eb 827#ifdef CONFIG_X86_32
4d46a89e
IM		 828# define BASE_PREFETCH ASM_NOP4
829# define ARCH_HAS_PREFETCH
ae2e15eb 830#else
4d46a89e 831# define BASE_PREFETCH "prefetcht0 (%1)"
ae2e15eb
GOC		 832#endif
833
4d46a89e
IM		 834/*
835 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
836 *
837 * It's not worth to care about 3dnow prefetches for the K6
838 * because they are microcoded there and very slow.
839 */
ae2e15eb
GOC		 840static inline void prefetch(const void *x)
841{
842 alternative_input(BASE_PREFETCH,
843 "prefetchnta (%1)",
844 X86_FEATURE_XMM,
845 "r" (x));
846}
847
4d46a89e
IM		 848/*
849 * 3dnow prefetch to get an exclusive cache line.
850 * Useful for spinlocks to avoid one state transition in the
851 * cache coherency protocol:
852 */
ae2e15eb
GOC		 853static inline void prefetchw(const void *x)
854{
855 alternative_input(BASE_PREFETCH,
856 "prefetchw (%1)",
857 X86_FEATURE_3DNOW,
858 "r" (x));
859}
860
4d46a89e
IM		 861static inline void spin_lock_prefetch(const void *x)
862{
863 prefetchw(x);
864}
865
2f66dcc9
GOC		 866#ifdef CONFIG_X86_32
867/*
868 * User space process size: 3GB (default).
869 */
4d46a89e 870#define TASK_SIZE PAGE_OFFSET
d9517346 871#define TASK_SIZE_MAX TASK_SIZE
4d46a89e
IM		 872#define STACK_TOP TASK_SIZE
873#define STACK_TOP_MAX STACK_TOP
874
875#define INIT_THREAD { \
876 .sp0 = sizeof(init_stack) + (long)&init_stack, \
877 .vm86_info = NULL, \
878 .sysenter_cs = __KERNEL_CS, \
879 .io_bitmap_ptr = NULL, \
2f66dcc9
GOC		 880}
881
882/*
883 * Note that the .io_bitmap member must be extra-big. This is because
884 * the CPU will access an additional byte beyond the end of the IO
885 * permission bitmap. The extra byte must be all 1 bits, and must
886 * be within the limit.
887 */
4d46a89e
IM		 888#define INIT_TSS { \
889 .x86_tss = { \
2f66dcc9 890 .sp0 = sizeof(init_stack) + (long)&init_stack, \
4d46a89e
IM		 891 .ss0 = __KERNEL_DS, \
892 .ss1 = __KERNEL_CS, \
893 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
894 }, \
895 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \
2f66dcc9
GOC		 896}
897
2f66dcc9
GOC		 898extern unsigned long thread_saved_pc(struct task_struct *tsk);
899
900#define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
901#define KSTK_TOP(info) \
902({ \
903 unsigned long *__ptr = (unsigned long *)(info); \
904 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
905})
906
907/*
908 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
909 * This is necessary to guarantee that the entire "struct pt_regs"
910 * is accessable even if the CPU haven't stored the SS/ESP registers
911 * on the stack (interrupt gate does not save these registers
912 * when switching to the same priv ring).
913 * Therefore beware: accessing the ss/esp fields of the
914 * "struct pt_regs" is possible, but they may contain the
915 * completely wrong values.
916 */
917#define task_pt_regs(task) \
918({ \
919 struct pt_regs *__regs__; \
920 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
921 __regs__ - 1; \
922})
923
4d46a89e 924#define KSTK_ESP(task) (task_pt_regs(task)->sp)
2f66dcc9
GOC		 925
926#else
927/*
928 * User space process size. 47bits minus one guard page.
929 */
d9517346 930#define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE)
2f66dcc9
GOC		 931
932/* This decides where the kernel will search for a free chunk of vm
933 * space during mmap's.
934 */
4d46a89e
IM		 935#define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
936 0xc0000000 : 0xFFFFe000)
2f66dcc9 937
4d46a89e 938#define TASK_SIZE (test_thread_flag(TIF_IA32) ? \
d9517346 939 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
4d46a89e 940#define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? \
d9517346 941 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
2f66dcc9 942
922a70d3 943#define STACK_TOP TASK_SIZE
d9517346 944#define STACK_TOP_MAX TASK_SIZE_MAX
922a70d3 945
2f66dcc9
GOC		 946#define INIT_THREAD { \
947 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
948}
949
950#define INIT_TSS { \
951 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
952}
953
2f66dcc9
GOC		 954/*
955 * Return saved PC of a blocked thread.
956 * What is this good for? it will be always the scheduler or ret_from_fork.
957 */
4d46a89e 958#define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
2f66dcc9 959
4d46a89e
IM		 960#define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
961#define KSTK_ESP(tsk) -1 /* sorry. doesn't work for syscall. */
2f66dcc9
GOC		 962#endif /* CONFIG_X86_64 */
963
513ad84b
IM		 964extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
965 unsigned long new_sp);
966
4d46a89e
IM		 967/*
968 * This decides where the kernel will search for a free chunk of vm
683e0253
GOC		 969 * space during mmap's.
970 */
971#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
972
4d46a89e 973#define KSTK_EIP(task) (task_pt_regs(task)->ip)
683e0253 974
529e25f6
EB		 975/* Get/set a process' ability to use the timestamp counter instruction */
976#define GET_TSC_CTL(adr) get_tsc_mode((adr))
977#define SET_TSC_CTL(val) set_tsc_mode((val))
978
979extern int get_tsc_mode(unsigned long adr);
980extern int set_tsc_mode(unsigned int val);
981
1965aae3 982#endif /* _ASM_X86_PROCESSOR_H */
Linux kernel - Deliverables
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