[deliverable/linux.git] / arch / x86 / include / asm / svm.h

#ifndef __SVM_H
#define __SVM_H

enum {
	INTERCEPT_INTR,
	INTERCEPT_NMI,
	INTERCEPT_SMI,
	INTERCEPT_INIT,
	INTERCEPT_VINTR,
	INTERCEPT_SELECTIVE_CR0,
	INTERCEPT_STORE_IDTR,
	INTERCEPT_STORE_GDTR,
	INTERCEPT_STORE_LDTR,
	INTERCEPT_STORE_TR,
	INTERCEPT_LOAD_IDTR,
	INTERCEPT_LOAD_GDTR,
	INTERCEPT_LOAD_LDTR,
	INTERCEPT_LOAD_TR,
	INTERCEPT_RDTSC,
	INTERCEPT_RDPMC,
	INTERCEPT_PUSHF,
	INTERCEPT_POPF,
	INTERCEPT_CPUID,
	INTERCEPT_RSM,
	INTERCEPT_IRET,
	INTERCEPT_INTn,
	INTERCEPT_INVD,
	INTERCEPT_PAUSE,
	INTERCEPT_HLT,
	INTERCEPT_INVLPG,
	INTERCEPT_INVLPGA,
	INTERCEPT_IOIO_PROT,
	INTERCEPT_MSR_PROT,
	INTERCEPT_TASK_SWITCH,
	INTERCEPT_FERR_FREEZE,
	INTERCEPT_SHUTDOWN,
	INTERCEPT_VMRUN,
	INTERCEPT_VMMCALL,
	INTERCEPT_VMLOAD,
	INTERCEPT_VMSAVE,
	INTERCEPT_STGI,
	INTERCEPT_CLGI,
	INTERCEPT_SKINIT,
	INTERCEPT_RDTSCP,
	INTERCEPT_ICEBP,
	INTERCEPT_WBINVD,
	INTERCEPT_MONITOR,
	INTERCEPT_MWAIT,
	INTERCEPT_MWAIT_COND,
	INTERCEPT_XSETBV,
};


struct __attribute__ ((__packed__)) vmcb_control_area {
	u32 intercept_cr;
	u32 intercept_dr;
	u32 intercept_exceptions;
	u64 intercept;
	u8 reserved_1[42];
	u16 pause_filter_count;
	u64 iopm_base_pa;
	u64 msrpm_base_pa;
	u64 tsc_offset;
	u32 asid;
	u8 tlb_ctl;
	u8 reserved_2[3];
	u32 int_ctl;
	u32 int_vector;
	u32 int_state;
	u8 reserved_3[4];
	u32 exit_code;
	u32 exit_code_hi;
	u64 exit_info_1;
	u64 exit_info_2;
	u32 exit_int_info;
	u32 exit_int_info_err;
	u64 nested_ctl;
	u8 reserved_4[16];
	u32 event_inj;
	u32 event_inj_err;
	u64 nested_cr3;
	u64 lbr_ctl;
	u32 clean;
	u32 reserved_5;
	u64 next_rip;
	u8 insn_len;
	u8 insn_bytes[15];
	u8 reserved_6[800];
};


#define TLB_CONTROL_DO_NOTHING 0
#define TLB_CONTROL_FLUSH_ALL_ASID 1
#define TLB_CONTROL_FLUSH_ASID 3
#define TLB_CONTROL_FLUSH_ASID_LOCAL 7

#define V_TPR_MASK 0x0f

#define V_IRQ_SHIFT 8
#define V_IRQ_MASK (1 << V_IRQ_SHIFT)

#define V_INTR_PRIO_SHIFT 16
#define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)

#define V_IGN_TPR_SHIFT 20
#define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT)

#define V_INTR_MASKING_SHIFT 24
#define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT)

#define SVM_INTERRUPT_SHADOW_MASK 1

#define SVM_IOIO_STR_SHIFT 2
#define SVM_IOIO_REP_SHIFT 3
#define SVM_IOIO_SIZE_SHIFT 4
#define SVM_IOIO_ASIZE_SHIFT 7

#define SVM_IOIO_TYPE_MASK 1
#define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT)
#define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT)
#define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT)
#define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT)

#define SVM_VM_CR_VALID_MASK	0x001fULL
#define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
#define SVM_VM_CR_SVM_DIS_MASK  0x0010ULL

struct __attribute__ ((__packed__)) vmcb_seg {
	u16 selector;
	u16 attrib;
	u32 limit;
	u64 base;
};

struct __attribute__ ((__packed__)) vmcb_save_area {
	struct vmcb_seg es;
	struct vmcb_seg cs;
	struct vmcb_seg ss;
	struct vmcb_seg ds;
	struct vmcb_seg fs;
	struct vmcb_seg gs;
	struct vmcb_seg gdtr;
	struct vmcb_seg ldtr;
	struct vmcb_seg idtr;
	struct vmcb_seg tr;
	u8 reserved_1[43];
	u8 cpl;
	u8 reserved_2[4];
	u64 efer;
	u8 reserved_3[112];
	u64 cr4;
	u64 cr3;
	u64 cr0;
	u64 dr7;
	u64 dr6;
	u64 rflags;
	u64 rip;
	u8 reserved_4[88];
	u64 rsp;
	u8 reserved_5[24];
	u64 rax;
	u64 star;
	u64 lstar;
	u64 cstar;
	u64 sfmask;
	u64 kernel_gs_base;
	u64 sysenter_cs;
	u64 sysenter_esp;
	u64 sysenter_eip;
	u64 cr2;
	u8 reserved_6[32];
	u64 g_pat;
	u64 dbgctl;
	u64 br_from;
	u64 br_to;
	u64 last_excp_from;
	u64 last_excp_to;
};

struct __attribute__ ((__packed__)) vmcb {
	struct vmcb_control_area control;
	struct vmcb_save_area save;
};

#define SVM_CPUID_FEATURE_SHIFT 2
#define SVM_CPUID_FUNC 0x8000000a

#define SVM_VM_CR_SVM_DISABLE 4

#define SVM_SELECTOR_S_SHIFT 4
#define SVM_SELECTOR_DPL_SHIFT 5
#define SVM_SELECTOR_P_SHIFT 7
#define SVM_SELECTOR_AVL_SHIFT 8
#define SVM_SELECTOR_L_SHIFT 9
#define SVM_SELECTOR_DB_SHIFT 10
#define SVM_SELECTOR_G_SHIFT 11

#define SVM_SELECTOR_TYPE_MASK (0xf)
#define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT)
#define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT)
#define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT)
#define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT)
#define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT)
#define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT)
#define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT)

#define SVM_SELECTOR_WRITE_MASK (1 << 1)
#define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK
#define SVM_SELECTOR_CODE_MASK (1 << 3)

#define INTERCEPT_CR0_READ	0
#define INTERCEPT_CR3_READ	3
#define INTERCEPT_CR4_READ	4
#define INTERCEPT_CR8_READ	8
#define INTERCEPT_CR0_WRITE	(16 + 0)
#define INTERCEPT_CR3_WRITE	(16 + 3)
#define INTERCEPT_CR4_WRITE	(16 + 4)
#define INTERCEPT_CR8_WRITE	(16 + 8)

#define INTERCEPT_DR0_READ	0
#define INTERCEPT_DR1_READ	1
#define INTERCEPT_DR2_READ	2
#define INTERCEPT_DR3_READ	3
#define INTERCEPT_DR4_READ	4
#define INTERCEPT_DR5_READ	5
#define INTERCEPT_DR6_READ	6
#define INTERCEPT_DR7_READ	7
#define INTERCEPT_DR0_WRITE	(16 + 0)
#define INTERCEPT_DR1_WRITE	(16 + 1)
#define INTERCEPT_DR2_WRITE	(16 + 2)
#define INTERCEPT_DR3_WRITE	(16 + 3)
#define INTERCEPT_DR4_WRITE	(16 + 4)
#define INTERCEPT_DR5_WRITE	(16 + 5)
#define INTERCEPT_DR6_WRITE	(16 + 6)
#define INTERCEPT_DR7_WRITE	(16 + 7)

#define SVM_EVTINJ_VEC_MASK 0xff

#define SVM_EVTINJ_TYPE_SHIFT 8
#define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT)

#define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
#define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT)
#define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT)
#define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT)

#define SVM_EVTINJ_VALID (1 << 31)
#define SVM_EVTINJ_VALID_ERR (1 << 11)

#define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
#define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK

#define	SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
#define	SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
#define	SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
#define	SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT

#define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID
#define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR

#define SVM_EXITINFOSHIFT_TS_REASON_IRET 36
#define SVM_EXITINFOSHIFT_TS_REASON_JMP 38
#define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44

#define SVM_EXITINFO_REG_MASK 0x0F

#define	SVM_EXIT_READ_CR0 	0x000
#define	SVM_EXIT_READ_CR3 	0x003
#define	SVM_EXIT_READ_CR4 	0x004
#define	SVM_EXIT_READ_CR8 	0x008
#define	SVM_EXIT_WRITE_CR0 	0x010
#define	SVM_EXIT_WRITE_CR3 	0x013
#define	SVM_EXIT_WRITE_CR4 	0x014
#define	SVM_EXIT_WRITE_CR8 	0x018
#define	SVM_EXIT_READ_DR0 	0x020
#define	SVM_EXIT_READ_DR1 	0x021
#define	SVM_EXIT_READ_DR2 	0x022
#define	SVM_EXIT_READ_DR3 	0x023
#define	SVM_EXIT_READ_DR4 	0x024
#define	SVM_EXIT_READ_DR5 	0x025
#define	SVM_EXIT_READ_DR6 	0x026
#define	SVM_EXIT_READ_DR7 	0x027
#define	SVM_EXIT_WRITE_DR0 	0x030
#define	SVM_EXIT_WRITE_DR1 	0x031
#define	SVM_EXIT_WRITE_DR2 	0x032
#define	SVM_EXIT_WRITE_DR3 	0x033
#define	SVM_EXIT_WRITE_DR4 	0x034
#define	SVM_EXIT_WRITE_DR5 	0x035
#define	SVM_EXIT_WRITE_DR6 	0x036
#define	SVM_EXIT_WRITE_DR7 	0x037
#define SVM_EXIT_EXCP_BASE      0x040
#define SVM_EXIT_INTR		0x060
#define SVM_EXIT_NMI		0x061
#define SVM_EXIT_SMI		0x062
#define SVM_EXIT_INIT		0x063
#define SVM_EXIT_VINTR		0x064
#define SVM_EXIT_CR0_SEL_WRITE	0x065
#define SVM_EXIT_IDTR_READ	0x066
#define SVM_EXIT_GDTR_READ	0x067
#define SVM_EXIT_LDTR_READ	0x068
#define SVM_EXIT_TR_READ	0x069
#define SVM_EXIT_IDTR_WRITE	0x06a
#define SVM_EXIT_GDTR_WRITE	0x06b
#define SVM_EXIT_LDTR_WRITE	0x06c
#define SVM_EXIT_TR_WRITE	0x06d
#define SVM_EXIT_RDTSC		0x06e
#define SVM_EXIT_RDPMC		0x06f
#define SVM_EXIT_PUSHF		0x070
#define SVM_EXIT_POPF		0x071
#define SVM_EXIT_CPUID		0x072
#define SVM_EXIT_RSM		0x073
#define SVM_EXIT_IRET		0x074
#define SVM_EXIT_SWINT		0x075
#define SVM_EXIT_INVD		0x076
#define SVM_EXIT_PAUSE		0x077
#define SVM_EXIT_HLT		0x078
#define SVM_EXIT_INVLPG		0x079
#define SVM_EXIT_INVLPGA	0x07a
#define SVM_EXIT_IOIO		0x07b
#define SVM_EXIT_MSR		0x07c
#define SVM_EXIT_TASK_SWITCH	0x07d
#define SVM_EXIT_FERR_FREEZE	0x07e
#define SVM_EXIT_SHUTDOWN	0x07f
#define SVM_EXIT_VMRUN		0x080
#define SVM_EXIT_VMMCALL	0x081
#define SVM_EXIT_VMLOAD		0x082
#define SVM_EXIT_VMSAVE		0x083
#define SVM_EXIT_STGI		0x084
#define SVM_EXIT_CLGI		0x085
#define SVM_EXIT_SKINIT		0x086
#define SVM_EXIT_RDTSCP		0x087
#define SVM_EXIT_ICEBP		0x088
#define SVM_EXIT_WBINVD		0x089
#define SVM_EXIT_MONITOR	0x08a
#define SVM_EXIT_MWAIT		0x08b
#define SVM_EXIT_MWAIT_COND	0x08c
#define SVM_EXIT_XSETBV		0x08d
#define SVM_EXIT_NPF  		0x400

#define SVM_EXIT_ERR		-1

#define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP)

#define SVM_VMLOAD ".byte 0x0f, 0x01, 0xda"
#define SVM_VMRUN  ".byte 0x0f, 0x01, 0xd8"
#define SVM_VMSAVE ".byte 0x0f, 0x01, 0xdb"
#define SVM_CLGI   ".byte 0x0f, 0x01, 0xdd"
#define SVM_STGI   ".byte 0x0f, 0x01, 0xdc"
#define SVM_INVLPGA ".byte 0x0f, 0x01, 0xdf"

#endif
Commit	Line	Data
6aa8b732 AK	1	#ifndef __SVM_H
	2	#define __SVM_H
	3
	4	enum {
	5	INTERCEPT_INTR,
	6	INTERCEPT_NMI,
	7	INTERCEPT_SMI,
	8	INTERCEPT_INIT,
	9	INTERCEPT_VINTR,
	10	INTERCEPT_SELECTIVE_CR0,
	11	INTERCEPT_STORE_IDTR,
	12	INTERCEPT_STORE_GDTR,
	13	INTERCEPT_STORE_LDTR,
	14	INTERCEPT_STORE_TR,
	15	INTERCEPT_LOAD_IDTR,
	16	INTERCEPT_LOAD_GDTR,
	17	INTERCEPT_LOAD_LDTR,
	18	INTERCEPT_LOAD_TR,
	19	INTERCEPT_RDTSC,
	20	INTERCEPT_RDPMC,
	21	INTERCEPT_PUSHF,
	22	INTERCEPT_POPF,
	23	INTERCEPT_CPUID,
	24	INTERCEPT_RSM,
	25	INTERCEPT_IRET,
	26	INTERCEPT_INTn,
	27	INTERCEPT_INVD,
	28	INTERCEPT_PAUSE,
	29	INTERCEPT_HLT,
	30	INTERCEPT_INVLPG,
	31	INTERCEPT_INVLPGA,
	32	INTERCEPT_IOIO_PROT,
	33	INTERCEPT_MSR_PROT,
	34	INTERCEPT_TASK_SWITCH,
	35	INTERCEPT_FERR_FREEZE,
	36	INTERCEPT_SHUTDOWN,
	37	INTERCEPT_VMRUN,
	38	INTERCEPT_VMMCALL,
	39	INTERCEPT_VMLOAD,
	40	INTERCEPT_VMSAVE,
	41	INTERCEPT_STGI,
	42	INTERCEPT_CLGI,
	43	INTERCEPT_SKINIT,
	44	INTERCEPT_RDTSCP,
	45	INTERCEPT_ICEBP,
	46	INTERCEPT_WBINVD,
916ce236 JR	47	INTERCEPT_MONITOR,
	48	INTERCEPT_MWAIT,
	49	INTERCEPT_MWAIT_COND,
81dd35d4	50	INTERCEPT_XSETBV,
6aa8b732 AK	51	};
	52
	53
	54	struct __attribute__ ((__packed__)) vmcb_control_area {
4ee546b4	55	u32 intercept_cr;
3aed041a	56	u32 intercept_dr;
6aa8b732 AK	57	u32 intercept_exceptions;
6aa8b732 AK	58	u64 intercept;
565d0998 ML	59	u8 reserved_1[42];
565d0998 ML	60	u16 pause_filter_count;
6aa8b732 AK	61	u64 iopm_base_pa;
	62	u64 msrpm_base_pa;
	63	u64 tsc_offset;
	64	u32 asid;
	65	u8 tlb_ctl;
	66	u8 reserved_2[3];
	67	u32 int_ctl;
	68	u32 int_vector;
	69	u32 int_state;
	70	u8 reserved_3[4];
	71	u32 exit_code;
	72	u32 exit_code_hi;
	73	u64 exit_info_1;
	74	u64 exit_info_2;
	75	u32 exit_int_info;
	76	u32 exit_int_info_err;
	77	u64 nested_ctl;
	78	u8 reserved_4[16];
	79	u32 event_inj;
	80	u32 event_inj_err;
	81	u64 nested_cr3;
	82	u64 lbr_ctl;
8d28fec4 RJ	83	u32 clean;
8d28fec4 RJ	84	u32 reserved_5;
6bc31bdc	85	u64 next_rip;
dc25e89e AP	86	u8 insn_len;
	87	u8 insn_bytes[15];
	88	u8 reserved_6[800];
6aa8b732 AK	89	};
	90
	91
	92	#define TLB_CONTROL_DO_NOTHING 0
	93	#define TLB_CONTROL_FLUSH_ALL_ASID 1
38e5e92f JR	94	#define TLB_CONTROL_FLUSH_ASID 3
38e5e92f JR	95	#define TLB_CONTROL_FLUSH_ASID_LOCAL 7
6aa8b732 AK	96
	97	#define V_TPR_MASK 0x0f
	98
	99	#define V_IRQ_SHIFT 8
	100	#define V_IRQ_MASK (1 << V_IRQ_SHIFT)
	101
	102	#define V_INTR_PRIO_SHIFT 16
	103	#define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
	104
	105	#define V_IGN_TPR_SHIFT 20
	106	#define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT)
	107
	108	#define V_INTR_MASKING_SHIFT 24
	109	#define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT)
	110
	111	#define SVM_INTERRUPT_SHADOW_MASK 1
	112
	113	#define SVM_IOIO_STR_SHIFT 2
	114	#define SVM_IOIO_REP_SHIFT 3
	115	#define SVM_IOIO_SIZE_SHIFT 4
	116	#define SVM_IOIO_ASIZE_SHIFT 7
	117
	118	#define SVM_IOIO_TYPE_MASK 1
	119	#define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT)
	120	#define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT)
	121	#define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT)
	122	#define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT)
	123
4a810181 JR	124	#define SVM_VM_CR_VALID_MASK 0x001fULL
	125	#define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
	126	#define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL
	127
6aa8b732 AK	128	struct __attribute__ ((__packed__)) vmcb_seg {
	129	u16 selector;
	130	u16 attrib;
	131	u32 limit;
	132	u64 base;
	133	};
	134
	135	struct __attribute__ ((__packed__)) vmcb_save_area {
	136	struct vmcb_seg es;
	137	struct vmcb_seg cs;
	138	struct vmcb_seg ss;
	139	struct vmcb_seg ds;
	140	struct vmcb_seg fs;
	141	struct vmcb_seg gs;
	142	struct vmcb_seg gdtr;
	143	struct vmcb_seg ldtr;
	144	struct vmcb_seg idtr;
	145	struct vmcb_seg tr;
	146	u8 reserved_1[43];
	147	u8 cpl;
	148	u8 reserved_2[4];
	149	u64 efer;
	150	u8 reserved_3[112];
	151	u64 cr4;
	152	u64 cr3;
	153	u64 cr0;
	154	u64 dr7;
	155	u64 dr6;
	156	u64 rflags;
	157	u64 rip;
	158	u8 reserved_4[88];
	159	u64 rsp;
	160	u8 reserved_5[24];
	161	u64 rax;
	162	u64 star;
	163	u64 lstar;
	164	u64 cstar;
	165	u64 sfmask;
	166	u64 kernel_gs_base;
	167	u64 sysenter_cs;
	168	u64 sysenter_esp;
	169	u64 sysenter_eip;
	170	u64 cr2;
	171	u8 reserved_6[32];
	172	u64 g_pat;
	173	u64 dbgctl;
	174	u64 br_from;
	175	u64 br_to;
	176	u64 last_excp_from;
	177	u64 last_excp_to;
	178	};
	179
	180	struct __attribute__ ((__packed__)) vmcb {
	181	struct vmcb_control_area control;
	182	struct vmcb_save_area save;
	183	};
	184
	185	#define SVM_CPUID_FEATURE_SHIFT 2
	186	#define SVM_CPUID_FUNC 0x8000000a
	187
6031a61c JR	188	#define SVM_VM_CR_SVM_DISABLE 4
6031a61c JR	189
6aa8b732 AK	190	#define SVM_SELECTOR_S_SHIFT 4
	191	#define SVM_SELECTOR_DPL_SHIFT 5
	192	#define SVM_SELECTOR_P_SHIFT 7
	193	#define SVM_SELECTOR_AVL_SHIFT 8
	194	#define SVM_SELECTOR_L_SHIFT 9
	195	#define SVM_SELECTOR_DB_SHIFT 10
	196	#define SVM_SELECTOR_G_SHIFT 11
	197
	198	#define SVM_SELECTOR_TYPE_MASK (0xf)
	199	#define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT)
	200	#define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT)
	201	#define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT)
	202	#define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT)
	203	#define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT)
	204	#define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT)
	205	#define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT)
	206
	207	#define SVM_SELECTOR_WRITE_MASK (1 << 1)
	208	#define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK
	209	#define SVM_SELECTOR_CODE_MASK (1 << 3)
	210
4ee546b4 RJ	211	#define INTERCEPT_CR0_READ 0
	212	#define INTERCEPT_CR3_READ 3
	213	#define INTERCEPT_CR4_READ 4
	214	#define INTERCEPT_CR8_READ 8
	215	#define INTERCEPT_CR0_WRITE (16 + 0)
	216	#define INTERCEPT_CR3_WRITE (16 + 3)
	217	#define INTERCEPT_CR4_WRITE (16 + 4)
	218	#define INTERCEPT_CR8_WRITE (16 + 8)
6aa8b732	219
3aed041a JR	220	#define INTERCEPT_DR0_READ 0
	221	#define INTERCEPT_DR1_READ 1
	222	#define INTERCEPT_DR2_READ 2
	223	#define INTERCEPT_DR3_READ 3
	224	#define INTERCEPT_DR4_READ 4
	225	#define INTERCEPT_DR5_READ 5
	226	#define INTERCEPT_DR6_READ 6
	227	#define INTERCEPT_DR7_READ 7
	228	#define INTERCEPT_DR0_WRITE (16 + 0)
	229	#define INTERCEPT_DR1_WRITE (16 + 1)
	230	#define INTERCEPT_DR2_WRITE (16 + 2)
	231	#define INTERCEPT_DR3_WRITE (16 + 3)
	232	#define INTERCEPT_DR4_WRITE (16 + 4)
	233	#define INTERCEPT_DR5_WRITE (16 + 5)
	234	#define INTERCEPT_DR6_WRITE (16 + 6)
	235	#define INTERCEPT_DR7_WRITE (16 + 7)
6aa8b732 AK	236
	237	#define SVM_EVTINJ_VEC_MASK 0xff
	238
	239	#define SVM_EVTINJ_TYPE_SHIFT 8
	240	#define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT)
	241
	242	#define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
	243	#define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT)
	244	#define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT)
	245	#define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT)
	246
	247	#define SVM_EVTINJ_VALID (1 << 31)
	248	#define SVM_EVTINJ_VALID_ERR (1 << 11)
	249
	250	#define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
64a7ec06	251	#define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK
6aa8b732 AK	252
	253	#define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
	254	#define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
	255	#define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
	256	#define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT
	257
	258	#define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID
	259	#define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR
	260
37817f29 IE	261	#define SVM_EXITINFOSHIFT_TS_REASON_IRET 36
37817f29 IE	262	#define SVM_EXITINFOSHIFT_TS_REASON_JMP 38
e269fb21	263	#define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44
37817f29	264
7ff76d58 AP	265	#define SVM_EXITINFO_REG_MASK 0x0F
7ff76d58 AP	266
6aa8b732 AK	267	#define SVM_EXIT_READ_CR0 0x000
	268	#define SVM_EXIT_READ_CR3 0x003
	269	#define SVM_EXIT_READ_CR4 0x004
	270	#define SVM_EXIT_READ_CR8 0x008
	271	#define SVM_EXIT_WRITE_CR0 0x010
	272	#define SVM_EXIT_WRITE_CR3 0x013
	273	#define SVM_EXIT_WRITE_CR4 0x014
	274	#define SVM_EXIT_WRITE_CR8 0x018
	275	#define SVM_EXIT_READ_DR0 0x020
	276	#define SVM_EXIT_READ_DR1 0x021
	277	#define SVM_EXIT_READ_DR2 0x022
	278	#define SVM_EXIT_READ_DR3 0x023
	279	#define SVM_EXIT_READ_DR4 0x024
	280	#define SVM_EXIT_READ_DR5 0x025
	281	#define SVM_EXIT_READ_DR6 0x026
	282	#define SVM_EXIT_READ_DR7 0x027
	283	#define SVM_EXIT_WRITE_DR0 0x030
	284	#define SVM_EXIT_WRITE_DR1 0x031
	285	#define SVM_EXIT_WRITE_DR2 0x032
	286	#define SVM_EXIT_WRITE_DR3 0x033
	287	#define SVM_EXIT_WRITE_DR4 0x034
	288	#define SVM_EXIT_WRITE_DR5 0x035
	289	#define SVM_EXIT_WRITE_DR6 0x036
	290	#define SVM_EXIT_WRITE_DR7 0x037
	291	#define SVM_EXIT_EXCP_BASE 0x040
	292	#define SVM_EXIT_INTR 0x060
	293	#define SVM_EXIT_NMI 0x061
	294	#define SVM_EXIT_SMI 0x062
	295	#define SVM_EXIT_INIT 0x063
	296	#define SVM_EXIT_VINTR 0x064
	297	#define SVM_EXIT_CR0_SEL_WRITE 0x065
	298	#define SVM_EXIT_IDTR_READ 0x066
	299	#define SVM_EXIT_GDTR_READ 0x067
	300	#define SVM_EXIT_LDTR_READ 0x068
	301	#define SVM_EXIT_TR_READ 0x069
	302	#define SVM_EXIT_IDTR_WRITE 0x06a
	303	#define SVM_EXIT_GDTR_WRITE 0x06b
	304	#define SVM_EXIT_LDTR_WRITE 0x06c
	305	#define SVM_EXIT_TR_WRITE 0x06d
	306	#define SVM_EXIT_RDTSC 0x06e
	307	#define SVM_EXIT_RDPMC 0x06f
	308	#define SVM_EXIT_PUSHF 0x070
	309	#define SVM_EXIT_POPF 0x071
	310	#define SVM_EXIT_CPUID 0x072
	311	#define SVM_EXIT_RSM 0x073
	312	#define SVM_EXIT_IRET 0x074
	313	#define SVM_EXIT_SWINT 0x075
	314	#define SVM_EXIT_INVD 0x076
	315	#define SVM_EXIT_PAUSE 0x077
	316	#define SVM_EXIT_HLT 0x078
	317	#define SVM_EXIT_INVLPG 0x079
	318	#define SVM_EXIT_INVLPGA 0x07a
	319	#define SVM_EXIT_IOIO 0x07b
	320	#define SVM_EXIT_MSR 0x07c
	321	#define SVM_EXIT_TASK_SWITCH 0x07d
	322	#define SVM_EXIT_FERR_FREEZE 0x07e
	323	#define SVM_EXIT_SHUTDOWN 0x07f
	324	#define SVM_EXIT_VMRUN 0x080
	325	#define SVM_EXIT_VMMCALL 0x081
	326	#define SVM_EXIT_VMLOAD 0x082
	327	#define SVM_EXIT_VMSAVE 0x083
	328	#define SVM_EXIT_STGI 0x084
	329	#define SVM_EXIT_CLGI 0x085
	330	#define SVM_EXIT_SKINIT 0x086
331	#define SVM_EXIT_RDTSCP 0x087
332	#define SVM_EXIT_ICEBP 0x088
333	#define SVM_EXIT_WBINVD 0x089
916ce236 JR	334	#define SVM_EXIT_MONITOR 0x08a
	335	#define SVM_EXIT_MWAIT 0x08b
	336	#define SVM_EXIT_MWAIT_COND 0x08c
81dd35d4	337	#define SVM_EXIT_XSETBV 0x08d
6aa8b732 AK	338	#define SVM_EXIT_NPF 0x400
	339
	340	#define SVM_EXIT_ERR -1
	341
dc77270f	342	#define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS \| X86_CR0_MP)
6aa8b732 AK	343
	344	#define SVM_VMLOAD ".byte 0x0f, 0x01, 0xda"
	345	#define SVM_VMRUN ".byte 0x0f, 0x01, 0xd8"
	346	#define SVM_VMSAVE ".byte 0x0f, 0x01, 0xdb"
	347	#define SVM_CLGI ".byte 0x0f, 0x01, 0xdd"
	348	#define SVM_STGI ".byte 0x0f, 0x01, 0xdc"
	349	#define SVM_INVLPGA ".byte 0x0f, 0x01, 0xdf"
	350
	351	#endif
	352