[deliverable/linux.git] / arch / x86 / include / asm / uv / uv_hub.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * SGI UV architectural definitions
 *
 * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
 */

#ifndef _ASM_X86_UV_UV_HUB_H
#define _ASM_X86_UV_UV_HUB_H

#ifdef CONFIG_X86_64
#include <linux/numa.h>
#include <linux/percpu.h>
#include <linux/timer.h>
#include <asm/types.h>
#include <asm/percpu.h>
#include <asm/uv/uv_mmrs.h>


/*
 * Addressing Terminology
 *
 *	M       - The low M bits of a physical address represent the offset
 *		  into the blade local memory. RAM memory on a blade is physically
 *		  contiguous (although various IO spaces may punch holes in
 *		  it)..
 *
 * 	N	- Number of bits in the node portion of a socket physical
 * 		  address.
 *
 * 	NASID   - network ID of a router, Mbrick or Cbrick. Nasid values of
 * 	 	  routers always have low bit of 1, C/MBricks have low bit
 * 		  equal to 0. Most addressing macros that target UV hub chips
 * 		  right shift the NASID by 1 to exclude the always-zero bit.
 * 		  NASIDs contain up to 15 bits.
 *
 *	GNODE   - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
 *		  of nasids.
 *
 * 	PNODE   - the low N bits of the GNODE. The PNODE is the most useful variant
 * 		  of the nasid for socket usage.
 *
 *
 *  NumaLink Global Physical Address Format:
 *  +--------------------------------+---------------------+
 *  |00..000|      GNODE             |      NodeOffset     |
 *  +--------------------------------+---------------------+
 *          |<-------53 - M bits --->|<--------M bits ----->
 *
 *	M - number of node offset bits (35 .. 40)
 *
 *
 *  Memory/UV-HUB Processor Socket Address Format:
 *  +----------------+---------------+---------------------+
 *  |00..000000000000|   PNODE       |      NodeOffset     |
 *  +----------------+---------------+---------------------+
 *                   <--- N bits --->|<--------M bits ----->
 *
 *	M - number of node offset bits (35 .. 40)
 *	N - number of PNODE bits (0 .. 10)
 *
 *		Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64).
 *		The actual values are configuration dependent and are set at
 *		boot time. M & N values are set by the hardware/BIOS at boot.
 *
 *
 * APICID format
 * 	NOTE!!!!!! This is the current format of the APICID. However, code
 * 	should assume that this will change in the future. Use functions
 * 	in this file for all APICID bit manipulations and conversion.
 *
 * 		1111110000000000
 * 		5432109876543210
 *		pppppppppplc0cch
 *		sssssssssss
 *
 *			p  = pnode bits
 *			l =  socket number on board
 *			c  = core
 *			h  = hyperthread
 *			s  = bits that are in the SOCKET_ID CSR
 *
 *	Note: Processor only supports 12 bits in the APICID register. The ACPI
 *	      tables hold all 16 bits. Software needs to be aware of this.
 *
 * 	      Unless otherwise specified, all references to APICID refer to
 * 	      the FULL value contained in ACPI tables, not the subset in the
 * 	      processor APICID register.
 */


/*
 * Maximum number of bricks in all partitions and in all coherency domains.
 * This is the total number of bricks accessible in the numalink fabric. It
 * includes all C & M bricks. Routers are NOT included.
 *
 * This value is also the value of the maximum number of non-router NASIDs
 * in the numalink fabric.
 *
 * NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused.
 */
#define UV_MAX_NUMALINK_BLADES	16384

/*
 * Maximum number of C/Mbricks within a software SSI (hardware may support
 * more).
 */
#define UV_MAX_SSI_BLADES	256

/*
 * The largest possible NASID of a C or M brick (+ 2)
 */
#define UV_MAX_NASID_VALUE	(UV_MAX_NUMALINK_NODES * 2)

struct uv_scir_s {
	struct timer_list timer;
	unsigned long	offset;
	unsigned long	last;
	unsigned long	idle_on;
	unsigned long	idle_off;
	unsigned char	state;
	unsigned char	enabled;
};

/*
 * The following defines attributes of the HUB chip. These attributes are
 * frequently referenced and are kept in the per-cpu data areas of each cpu.
 * They are kept together in a struct to minimize cache misses.
 */
struct uv_hub_info_s {
	unsigned long		global_mmr_base;
	unsigned long		gpa_mask;
	unsigned int		gnode_extra;
	unsigned long		gnode_upper;
	unsigned long		lowmem_remap_top;
	unsigned long		lowmem_remap_base;
	unsigned short		pnode;
	unsigned short		pnode_mask;
	unsigned short		coherency_domain_number;
	unsigned short		numa_blade_id;
	unsigned char		blade_processor_id;
	unsigned char		m_val;
	unsigned char		n_val;
	struct uv_scir_s	scir;
};

DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
#define uv_hub_info 		(&__get_cpu_var(__uv_hub_info))
#define uv_cpu_hub_info(cpu)	(&per_cpu(__uv_hub_info, cpu))

/*
 * Local & Global MMR space macros.
 * 	Note: macros are intended to be used ONLY by inline functions
 * 	in this file - not by other kernel code.
 * 		n -  NASID (full 15-bit global nasid)
 * 		g -  GNODE (full 15-bit global nasid, right shifted 1)
 * 		p -  PNODE (local part of nsids, right shifted 1)
 */
#define UV_NASID_TO_PNODE(n)		(((n) >> 1) & uv_hub_info->pnode_mask)
#define UV_PNODE_TO_GNODE(p)		((p) |uv_hub_info->gnode_extra)
#define UV_PNODE_TO_NASID(p)		(UV_PNODE_TO_GNODE(p) << 1)

#define UV_LOCAL_MMR_BASE		0xf4000000UL
#define UV_GLOBAL_MMR32_BASE		0xf8000000UL
#define UV_GLOBAL_MMR64_BASE		(uv_hub_info->global_mmr_base)
#define UV_LOCAL_MMR_SIZE		(64UL * 1024 * 1024)
#define UV_GLOBAL_MMR32_SIZE		(64UL * 1024 * 1024)

#define UV_GLOBAL_MMR32_PNODE_SHIFT	15
#define UV_GLOBAL_MMR64_PNODE_SHIFT	26

#define UV_GLOBAL_MMR32_PNODE_BITS(p)	((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT))

#define UV_GLOBAL_MMR64_PNODE_BITS(p)					\
	(((unsigned long)(p)) << UV_GLOBAL_MMR64_PNODE_SHIFT)

#define UV_APIC_PNODE_SHIFT	6

/* Local Bus from cpu's perspective */
#define LOCAL_BUS_BASE		0x1c00000
#define LOCAL_BUS_SIZE		(4 * 1024 * 1024)

/*
 * System Controller Interface Reg
 *
 * Note there are NO leds on a UV system.  This register is only
 * used by the system controller to monitor system-wide operation.
 * There are 64 regs per node.  With Nahelem cpus (2 cores per node,
 * 8 cpus per core, 2 threads per cpu) there are 32 cpu threads on
 * a node.
 *
 * The window is located at top of ACPI MMR space
 */
#define SCIR_WINDOW_COUNT	64
#define SCIR_LOCAL_MMR_BASE	(LOCAL_BUS_BASE + \
				 LOCAL_BUS_SIZE - \
				 SCIR_WINDOW_COUNT)

#define SCIR_CPU_HEARTBEAT	0x01	/* timer interrupt */
#define SCIR_CPU_ACTIVITY	0x02	/* not idle */
#define SCIR_CPU_HB_INTERVAL	(HZ)	/* once per second */

/* Loop through all installed blades */
#define for_each_possible_blade(bid)		\
	for ((bid) = 0; (bid) < uv_num_possible_blades(); (bid)++)

/*
 * Macros for converting between kernel virtual addresses, socket local physical
 * addresses, and UV global physical addresses.
 * 	Note: use the standard __pa() & __va() macros for converting
 * 	      between socket virtual and socket physical addresses.
 */

/* socket phys RAM --> UV global physical address */
static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr)
{
	if (paddr < uv_hub_info->lowmem_remap_top)
		paddr |= uv_hub_info->lowmem_remap_base;
	return paddr | uv_hub_info->gnode_upper;
}


/* socket virtual --> UV global physical address */
static inline unsigned long uv_gpa(void *v)
{
	return uv_soc_phys_ram_to_gpa(__pa(v));
}

/* pnode, offset --> socket virtual */
static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset)
{
	return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset);
}


/*
 * Extract a PNODE from an APICID (full apicid, not processor subset)
 */
static inline int uv_apicid_to_pnode(int apicid)
{
	return (apicid >> UV_APIC_PNODE_SHIFT);
}

/*
 * Access global MMRs using the low memory MMR32 space. This region supports
 * faster MMR access but not all MMRs are accessible in this space.
 */
static inline unsigned long *uv_global_mmr32_address(int pnode,
				unsigned long offset)
{
	return __va(UV_GLOBAL_MMR32_BASE |
		       UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset);
}

static inline void uv_write_global_mmr32(int pnode, unsigned long offset,
				 unsigned long val)
{
	*uv_global_mmr32_address(pnode, offset) = val;
}

static inline unsigned long uv_read_global_mmr32(int pnode,
						 unsigned long offset)
{
	return *uv_global_mmr32_address(pnode, offset);
}

/*
 * Access Global MMR space using the MMR space located at the top of physical
 * memory.
 */
static inline unsigned long *uv_global_mmr64_address(int pnode,
				unsigned long offset)
{
	return __va(UV_GLOBAL_MMR64_BASE |
		    UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset);
}

static inline void uv_write_global_mmr64(int pnode, unsigned long offset,
				unsigned long val)
{
	*uv_global_mmr64_address(pnode, offset) = val;
}

static inline unsigned long uv_read_global_mmr64(int pnode,
						 unsigned long offset)
{
	return *uv_global_mmr64_address(pnode, offset);
}

/*
 * Access hub local MMRs. Faster than using global space but only local MMRs
 * are accessible.
 */
static inline unsigned long *uv_local_mmr_address(unsigned long offset)
{
	return __va(UV_LOCAL_MMR_BASE | offset);
}

static inline unsigned long uv_read_local_mmr(unsigned long offset)
{
	return *uv_local_mmr_address(offset);
}

static inline void uv_write_local_mmr(unsigned long offset, unsigned long val)
{
	*uv_local_mmr_address(offset) = val;
}

static inline unsigned char uv_read_local_mmr8(unsigned long offset)
{
	return *((unsigned char *)uv_local_mmr_address(offset));
}

static inline void uv_write_local_mmr8(unsigned long offset, unsigned char val)
{
	*((unsigned char *)uv_local_mmr_address(offset)) = val;
}

/*
 * Structures and definitions for converting between cpu, node, pnode, and blade
 * numbers.
 */
struct uv_blade_info {
	unsigned short	nr_possible_cpus;
	unsigned short	nr_online_cpus;
	unsigned short	pnode;
	short		memory_nid;
};
extern struct uv_blade_info *uv_blade_info;
extern short *uv_node_to_blade;
extern short *uv_cpu_to_blade;
extern short uv_possible_blades;

/* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */
static inline int uv_blade_processor_id(void)
{
	return uv_hub_info->blade_processor_id;
}

/* Blade number of current cpu. Numnbered 0 .. <#blades -1> */
static inline int uv_numa_blade_id(void)
{
	return uv_hub_info->numa_blade_id;
}

/* Convert a cpu number to the the UV blade number */
static inline int uv_cpu_to_blade_id(int cpu)
{
	return uv_cpu_to_blade[cpu];
}

/* Convert linux node number to the UV blade number */
static inline int uv_node_to_blade_id(int nid)
{
	return uv_node_to_blade[nid];
}

/* Convert a blade id to the PNODE of the blade */
static inline int uv_blade_to_pnode(int bid)
{
	return uv_blade_info[bid].pnode;
}

/* Nid of memory node on blade. -1 if no blade-local memory */
static inline int uv_blade_to_memory_nid(int bid)
{
	return uv_blade_info[bid].memory_nid;
}

/* Determine the number of possible cpus on a blade */
static inline int uv_blade_nr_possible_cpus(int bid)
{
	return uv_blade_info[bid].nr_possible_cpus;
}

/* Determine the number of online cpus on a blade */
static inline int uv_blade_nr_online_cpus(int bid)
{
	return uv_blade_info[bid].nr_online_cpus;
}

/* Convert a cpu id to the PNODE of the blade containing the cpu */
static inline int uv_cpu_to_pnode(int cpu)
{
	return uv_blade_info[uv_cpu_to_blade_id(cpu)].pnode;
}

/* Convert a linux node number to the PNODE of the blade */
static inline int uv_node_to_pnode(int nid)
{
	return uv_blade_info[uv_node_to_blade_id(nid)].pnode;
}

/* Maximum possible number of blades */
static inline int uv_num_possible_blades(void)
{
	return uv_possible_blades;
}

/* Update SCIR state */
static inline void uv_set_scir_bits(unsigned char value)
{
	if (uv_hub_info->scir.state != value) {
		uv_hub_info->scir.state = value;
		uv_write_local_mmr8(uv_hub_info->scir.offset, value);
	}
}

static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value)
{
	if (uv_cpu_hub_info(cpu)->scir.state != value) {
		uv_cpu_hub_info(cpu)->scir.state = value;
		uv_write_local_mmr8(uv_cpu_hub_info(cpu)->scir.offset, value);
	}
}

static inline void uv_hub_send_ipi(int pnode, int apicid, int vector)
{
	unsigned long val;

	val = (1UL << UVH_IPI_INT_SEND_SHFT) |
			((apicid & 0x3f) << UVH_IPI_INT_APIC_ID_SHFT) |
			(vector << UVH_IPI_INT_VECTOR_SHFT);
	uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
}

#endif /* CONFIG_X86_64 */
#endif /* _ASM_X86_UV_UV_HUB_H */
Commit	Line	Data
952cf6d7 JS	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* SGI UV architectural definitions
	7	*
9f5314fb	8	* Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
952cf6d7 JS	9	*/
952cf6d7 JS	10
05e4d316 PA	11	#ifndef _ASM_X86_UV_UV_HUB_H
05e4d316 PA	12	#define _ASM_X86_UV_UV_HUB_H
952cf6d7	13
bc5d9940	14	#ifdef CONFIG_X86_64
952cf6d7 JS	15	#include <linux/numa.h>
952cf6d7 JS	16	#include <linux/percpu.h>
c08b6acc	17	#include <linux/timer.h>
952cf6d7 JS	18	#include <asm/types.h>
952cf6d7 JS	19	#include <asm/percpu.h>
66666e50	20	#include <asm/uv/uv_mmrs.h>
952cf6d7 JS	21
	22
	23	/*
	24	* Addressing Terminology
	25	*
9f5314fb JS	26	* M - The low M bits of a physical address represent the offset
	27	* into the blade local memory. RAM memory on a blade is physically
	28	* contiguous (although various IO spaces may punch holes in
	29	* it)..
952cf6d7	30	*
9f5314fb JS	31	* N - Number of bits in the node portion of a socket physical
	32	* address.
	33	*
	34	* NASID - network ID of a router, Mbrick or Cbrick. Nasid values of
	35	* routers always have low bit of 1, C/MBricks have low bit
	36	* equal to 0. Most addressing macros that target UV hub chips
	37	* right shift the NASID by 1 to exclude the always-zero bit.
	38	* NASIDs contain up to 15 bits.
	39	*
	40	* GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
	41	* of nasids.
	42	*
	43	* PNODE - the low N bits of the GNODE. The PNODE is the most useful variant
	44	* of the nasid for socket usage.
	45	*
	46	*
	47	* NumaLink Global Physical Address Format:
	48	* +--------------------------------+---------------------+
	49	* \|00..000\| GNODE \| NodeOffset \|
	50	* +--------------------------------+---------------------+
	51	* \|<-------53 - M bits --->\|<--------M bits ----->
	52	*
	53	* M - number of node offset bits (35 .. 40)
952cf6d7 JS	54	*
	55	*
	56	* Memory/UV-HUB Processor Socket Address Format:
9f5314fb JS	57	* +----------------+---------------+---------------------+
	58	* \|00..000000000000\| PNODE \| NodeOffset \|
	59	* +----------------+---------------+---------------------+
	60	* <--- N bits --->\|<--------M bits ----->
952cf6d7	61	*
9f5314fb JS	62	* M - number of node offset bits (35 .. 40)
9f5314fb JS	63	* N - number of PNODE bits (0 .. 10)
952cf6d7 JS	64	*
	65	* Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64).
	66	* The actual values are configuration dependent and are set at
9f5314fb JS	67	* boot time. M & N values are set by the hardware/BIOS at boot.
9f5314fb JS	68	*
952cf6d7 JS	69	*
	70	* APICID format
	71	* NOTE!!!!!! This is the current format of the APICID. However, code
	72	* should assume that this will change in the future. Use functions
	73	* in this file for all APICID bit manipulations and conversion.
	74	*
	75	* 1111110000000000
	76	* 5432109876543210
9f5314fb	77	* pppppppppplc0cch
952cf6d7 JS	78	* sssssssssss
952cf6d7 JS	79	*
9f5314fb	80	* p = pnode bits
952cf6d7 JS	81	* l = socket number on board
	82	* c = core
	83	* h = hyperthread
9f5314fb	84	* s = bits that are in the SOCKET_ID CSR
952cf6d7 JS	85	*
	86	* Note: Processor only supports 12 bits in the APICID register. The ACPI
	87	* tables hold all 16 bits. Software needs to be aware of this.
	88	*
	89	* Unless otherwise specified, all references to APICID refer to
	90	* the FULL value contained in ACPI tables, not the subset in the
	91	* processor APICID register.
	92	*/
	93
	94
	95	/*
	96	* Maximum number of bricks in all partitions and in all coherency domains.
	97	* This is the total number of bricks accessible in the numalink fabric. It
	98	* includes all C & M bricks. Routers are NOT included.
	99	*
	100	* This value is also the value of the maximum number of non-router NASIDs
	101	* in the numalink fabric.
	102	*
9f5314fb	103	* NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused.
952cf6d7 JS	104	*/
	105	#define UV_MAX_NUMALINK_BLADES 16384
	106
	107	/*
	108	* Maximum number of C/Mbricks within a software SSI (hardware may support
	109	* more).
	110	*/
	111	#define UV_MAX_SSI_BLADES 256
	112
	113	/*
	114	* The largest possible NASID of a C or M brick (+ 2)
	115	*/
	116	#define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_NODES * 2)
	117
7f1baa06 MT	118	struct uv_scir_s {
	119	struct timer_list timer;
	120	unsigned long offset;
	121	unsigned long last;
	122	unsigned long idle_on;
	123	unsigned long idle_off;
	124	unsigned char state;
	125	unsigned char enabled;
	126	};
	127
952cf6d7 JS	128	/*
	129	* The following defines attributes of the HUB chip. These attributes are
	130	* frequently referenced and are kept in the per-cpu data areas of each cpu.
	131	* They are kept together in a struct to minimize cache misses.
	132	*/
	133	struct uv_hub_info_s {
69a72a0e MT	134	unsigned long global_mmr_base;
69a72a0e MT	135	unsigned long gpa_mask;
c4ed3f04	136	unsigned int gnode_extra;
69a72a0e MT	137	unsigned long gnode_upper;
	138	unsigned long lowmem_remap_top;
	139	unsigned long lowmem_remap_base;
	140	unsigned short pnode;
	141	unsigned short pnode_mask;
	142	unsigned short coherency_domain_number;
	143	unsigned short numa_blade_id;
	144	unsigned char blade_processor_id;
	145	unsigned char m_val;
	146	unsigned char n_val;
	147	struct uv_scir_s scir;
952cf6d7	148	};
7f1baa06	149
952cf6d7 JS	150	DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
	151	#define uv_hub_info (&__get_cpu_var(__uv_hub_info))
	152	#define uv_cpu_hub_info(cpu) (&per_cpu(__uv_hub_info, cpu))
	153
	154	/*
	155	* Local & Global MMR space macros.
	156	* Note: macros are intended to be used ONLY by inline functions
	157	* in this file - not by other kernel code.
9f5314fb JS	158	* n - NASID (full 15-bit global nasid)
	159	* g - GNODE (full 15-bit global nasid, right shifted 1)
	160	* p - PNODE (local part of nsids, right shifted 1)
952cf6d7	161	*/
9f5314fb	162	#define UV_NASID_TO_PNODE(n) (((n) >> 1) & uv_hub_info->pnode_mask)
c4ed3f04 JS	163	#define UV_PNODE_TO_GNODE(p) ((p) \|uv_hub_info->gnode_extra)
c4ed3f04 JS	164	#define UV_PNODE_TO_NASID(p) (UV_PNODE_TO_GNODE(p) << 1)
952cf6d7 JS	165
	166	#define UV_LOCAL_MMR_BASE 0xf4000000UL
	167	#define UV_GLOBAL_MMR32_BASE 0xf8000000UL
	168	#define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base)
83f5d894 JS	169	#define UV_LOCAL_MMR_SIZE (64UL * 1024 * 1024)
83f5d894 JS	170	#define UV_GLOBAL_MMR32_SIZE (64UL * 1024 * 1024)
952cf6d7	171
9f5314fb JS	172	#define UV_GLOBAL_MMR32_PNODE_SHIFT 15
9f5314fb JS	173	#define UV_GLOBAL_MMR64_PNODE_SHIFT 26
952cf6d7	174
9f5314fb	175	#define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT))
952cf6d7	176
9f5314fb	177	#define UV_GLOBAL_MMR64_PNODE_BITS(p) \
67e83f30	178	(((unsigned long)(p)) << UV_GLOBAL_MMR64_PNODE_SHIFT)
9f5314fb JS	179
	180	#define UV_APIC_PNODE_SHIFT 6
	181
7f1baa06 MT	182	/* Local Bus from cpu's perspective */
	183	#define LOCAL_BUS_BASE 0x1c00000
	184	#define LOCAL_BUS_SIZE (4 * 1024 * 1024)
	185
	186	/*
	187	* System Controller Interface Reg
	188	*
	189	* Note there are NO leds on a UV system. This register is only
	190	* used by the system controller to monitor system-wide operation.
	191	* There are 64 regs per node. With Nahelem cpus (2 cores per node,
	192	* 8 cpus per core, 2 threads per cpu) there are 32 cpu threads on
	193	* a node.
	194	*
	195	* The window is located at top of ACPI MMR space
	196	*/
	197	#define SCIR_WINDOW_COUNT 64
	198	#define SCIR_LOCAL_MMR_BASE (LOCAL_BUS_BASE + \
	199	LOCAL_BUS_SIZE - \
	200	SCIR_WINDOW_COUNT)
	201
	202	#define SCIR_CPU_HEARTBEAT 0x01 /* timer interrupt */
	203	#define SCIR_CPU_ACTIVITY 0x02 /* not idle */
	204	#define SCIR_CPU_HB_INTERVAL (HZ) /* once per second */
	205
8661984f DS	206	/* Loop through all installed blades */
	207	#define for_each_possible_blade(bid) \
	208	for ((bid) = 0; (bid) < uv_num_possible_blades(); (bid)++)
	209
9f5314fb JS	210	/*
	211	* Macros for converting between kernel virtual addresses, socket local physical
	212	* addresses, and UV global physical addresses.
	213	* Note: use the standard __pa() & __va() macros for converting
	214	* between socket virtual and socket physical addresses.
	215	*/
	216
	217	/* socket phys RAM --> UV global physical address */
	218	static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr)
	219	{
	220	if (paddr < uv_hub_info->lowmem_remap_top)
189f67c4	221	paddr \|= uv_hub_info->lowmem_remap_base;
9f5314fb JS	222	return paddr \| uv_hub_info->gnode_upper;
	223	}
	224
	225
	226	/* socket virtual --> UV global physical address */
	227	static inline unsigned long uv_gpa(void *v)
	228	{
189f67c4	229	return uv_soc_phys_ram_to_gpa(__pa(v));
9f5314fb JS	230	}
	231
	232	/* pnode, offset --> socket virtual */
	233	static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset)
	234	{
	235	return __va(((unsigned long)pnode << uv_hub_info->m_val) \| offset);
	236	}
952cf6d7	237
952cf6d7 JS	238
952cf6d7 JS	239	/*
9f5314fb	240	* Extract a PNODE from an APICID (full apicid, not processor subset)
952cf6d7	241	*/
9f5314fb	242	static inline int uv_apicid_to_pnode(int apicid)
952cf6d7	243	{
9f5314fb	244	return (apicid >> UV_APIC_PNODE_SHIFT);
952cf6d7 JS	245	}
	246
	247	/*
	248	* Access global MMRs using the low memory MMR32 space. This region supports
	249	* faster MMR access but not all MMRs are accessible in this space.
	250	*/
9f5314fb	251	static inline unsigned long *uv_global_mmr32_address(int pnode,
952cf6d7 JS	252	unsigned long offset)
	253	{
	254	return __va(UV_GLOBAL_MMR32_BASE \|
9f5314fb	255	UV_GLOBAL_MMR32_PNODE_BITS(pnode) \| offset);
952cf6d7 JS	256	}
952cf6d7 JS	257
9f5314fb	258	static inline void uv_write_global_mmr32(int pnode, unsigned long offset,
952cf6d7 JS	259	unsigned long val)
952cf6d7 JS	260	{
9f5314fb	261	*uv_global_mmr32_address(pnode, offset) = val;
952cf6d7 JS	262	}
952cf6d7 JS	263
9f5314fb	264	static inline unsigned long uv_read_global_mmr32(int pnode,
952cf6d7 JS	265	unsigned long offset)
952cf6d7 JS	266	{
9f5314fb	267	return *uv_global_mmr32_address(pnode, offset);
952cf6d7 JS	268	}
	269
	270	/*
	271	* Access Global MMR space using the MMR space located at the top of physical
	272	* memory.
	273	*/
9f5314fb	274	static inline unsigned long *uv_global_mmr64_address(int pnode,
952cf6d7 JS	275	unsigned long offset)
	276	{
	277	return __va(UV_GLOBAL_MMR64_BASE \|
9f5314fb	278	UV_GLOBAL_MMR64_PNODE_BITS(pnode) \| offset);
952cf6d7 JS	279	}
952cf6d7 JS	280
9f5314fb	281	static inline void uv_write_global_mmr64(int pnode, unsigned long offset,
952cf6d7 JS	282	unsigned long val)
952cf6d7 JS	283	{
9f5314fb	284	*uv_global_mmr64_address(pnode, offset) = val;
952cf6d7 JS	285	}
952cf6d7 JS	286
9f5314fb	287	static inline unsigned long uv_read_global_mmr64(int pnode,
952cf6d7 JS	288	unsigned long offset)
952cf6d7 JS	289	{
9f5314fb	290	return *uv_global_mmr64_address(pnode, offset);
952cf6d7 JS	291	}
	292
	293	/*
9f5314fb	294	* Access hub local MMRs. Faster than using global space but only local MMRs
952cf6d7 JS	295	* are accessible.
	296	*/
	297	static inline unsigned long *uv_local_mmr_address(unsigned long offset)
	298	{
	299	return __va(UV_LOCAL_MMR_BASE \| offset);
	300	}
	301
	302	static inline unsigned long uv_read_local_mmr(unsigned long offset)
	303	{
	304	return *uv_local_mmr_address(offset);
	305	}
	306
	307	static inline void uv_write_local_mmr(unsigned long offset, unsigned long val)
	308	{
	309	*uv_local_mmr_address(offset) = val;
	310	}
	311
7f1baa06 MT	312	static inline unsigned char uv_read_local_mmr8(unsigned long offset)
	313	{
	314	return ((unsigned char )uv_local_mmr_address(offset));
	315	}
	316
	317	static inline void uv_write_local_mmr8(unsigned long offset, unsigned char val)
	318	{
	319	((unsigned char )uv_local_mmr_address(offset)) = val;
	320	}
	321
8400def8	322	/*
9f5314fb	323	* Structures and definitions for converting between cpu, node, pnode, and blade
8400def8 JS	324	* numbers.
	325	*/
	326	struct uv_blade_info {
9f5314fb	327	unsigned short nr_possible_cpus;
8400def8	328	unsigned short nr_online_cpus;
9f5314fb	329	unsigned short pnode;
6c7184b7	330	short memory_nid;
8400def8	331	};
9f5314fb	332	extern struct uv_blade_info *uv_blade_info;
8400def8 JS	333	extern short *uv_node_to_blade;
	334	extern short *uv_cpu_to_blade;
	335	extern short uv_possible_blades;
	336
	337	/* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */
	338	static inline int uv_blade_processor_id(void)
	339	{
	340	return uv_hub_info->blade_processor_id;
	341	}
	342
	343	/* Blade number of current cpu. Numnbered 0 .. <#blades -1> */
	344	static inline int uv_numa_blade_id(void)
	345	{
	346	return uv_hub_info->numa_blade_id;
	347	}
	348
	349	/* Convert a cpu number to the the UV blade number */
	350	static inline int uv_cpu_to_blade_id(int cpu)
	351	{
	352	return uv_cpu_to_blade[cpu];
	353	}
	354
	355	/* Convert linux node number to the UV blade number */
	356	static inline int uv_node_to_blade_id(int nid)
	357	{
	358	return uv_node_to_blade[nid];
	359	}
	360
9f5314fb JS	361	/* Convert a blade id to the PNODE of the blade */
9f5314fb JS	362	static inline int uv_blade_to_pnode(int bid)
8400def8	363	{
9f5314fb	364	return uv_blade_info[bid].pnode;
8400def8 JS	365	}
8400def8 JS	366
6c7184b7 JS	367	/* Nid of memory node on blade. -1 if no blade-local memory */
	368	static inline int uv_blade_to_memory_nid(int bid)
	369	{
	370	return uv_blade_info[bid].memory_nid;
	371	}
	372
8400def8 JS	373	/* Determine the number of possible cpus on a blade */
	374	static inline int uv_blade_nr_possible_cpus(int bid)
	375	{
9f5314fb	376	return uv_blade_info[bid].nr_possible_cpus;
8400def8 JS	377	}
	378
	379	/* Determine the number of online cpus on a blade */
	380	static inline int uv_blade_nr_online_cpus(int bid)
	381	{
	382	return uv_blade_info[bid].nr_online_cpus;
	383	}
	384
9f5314fb JS	385	/* Convert a cpu id to the PNODE of the blade containing the cpu */
9f5314fb JS	386	static inline int uv_cpu_to_pnode(int cpu)
8400def8	387	{
9f5314fb	388	return uv_blade_info[uv_cpu_to_blade_id(cpu)].pnode;
8400def8 JS	389	}
8400def8 JS	390
9f5314fb JS	391	/* Convert a linux node number to the PNODE of the blade */
9f5314fb JS	392	static inline int uv_node_to_pnode(int nid)
8400def8	393	{
9f5314fb	394	return uv_blade_info[uv_node_to_blade_id(nid)].pnode;
8400def8 JS	395	}
	396
	397	/* Maximum possible number of blades */
	398	static inline int uv_num_possible_blades(void)
	399	{
	400	return uv_possible_blades;
	401	}
	402
7f1baa06 MT	403	/* Update SCIR state */
	404	static inline void uv_set_scir_bits(unsigned char value)
	405	{
	406	if (uv_hub_info->scir.state != value) {
	407	uv_hub_info->scir.state = value;
	408	uv_write_local_mmr8(uv_hub_info->scir.offset, value);
	409	}
	410	}
66666e50	411
7f1baa06 MT	412	static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value)
	413	{
	414	if (uv_cpu_hub_info(cpu)->scir.state != value) {
	415	uv_cpu_hub_info(cpu)->scir.state = value;
	416	uv_write_local_mmr8(uv_cpu_hub_info(cpu)->scir.offset, value);
	417	}
	418	}
952cf6d7	419
66666e50 JS	420	static inline void uv_hub_send_ipi(int pnode, int apicid, int vector)
	421	{
	422	unsigned long val;
	423
	424	val = (1UL << UVH_IPI_INT_SEND_SHFT) \|
	425	((apicid & 0x3f) << UVH_IPI_INT_APIC_ID_SHFT) \|
	426	(vector << UVH_IPI_INT_VECTOR_SHFT);
	427	uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
	428	}
	429
bc5d9940	430	#endif /* CONFIG_X86_64 */
7f1baa06	431	#endif /* _ASM_X86_UV_UV_HUB_H */