[deliverable/linux.git] / arch / x86 / include / asm / uv / uv_hub.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * SGI UV architectural definitions
 *
 * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
 */

#ifndef _ASM_X86_UV_UV_HUB_H
#define _ASM_X86_UV_UV_HUB_H

#include <linux/numa.h>
#include <linux/percpu.h>
#include <linux/timer.h>
#include <asm/types.h>
#include <asm/percpu.h>


/*
 * Addressing Terminology
 *
 *	M       - The low M bits of a physical address represent the offset
 *		  into the blade local memory. RAM memory on a blade is physically
 *		  contiguous (although various IO spaces may punch holes in
 *		  it)..
 *
 * 	N	- Number of bits in the node portion of a socket physical
 * 		  address.
 *
 * 	NASID   - network ID of a router, Mbrick or Cbrick. Nasid values of
 * 	 	  routers always have low bit of 1, C/MBricks have low bit
 * 		  equal to 0. Most addressing macros that target UV hub chips
 * 		  right shift the NASID by 1 to exclude the always-zero bit.
 * 		  NASIDs contain up to 15 bits.
 *
 *	GNODE   - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
 *		  of nasids.
 *
 * 	PNODE   - the low N bits of the GNODE. The PNODE is the most useful variant
 * 		  of the nasid for socket usage.
 *
 *
 *  NumaLink Global Physical Address Format:
 *  +--------------------------------+---------------------+
 *  |00..000|      GNODE             |      NodeOffset     |
 *  +--------------------------------+---------------------+
 *          |<-------53 - M bits --->|<--------M bits ----->
 *
 *	M - number of node offset bits (35 .. 40)
 *
 *
 *  Memory/UV-HUB Processor Socket Address Format:
 *  +----------------+---------------+---------------------+
 *  |00..000000000000|   PNODE       |      NodeOffset     |
 *  +----------------+---------------+---------------------+
 *                   <--- N bits --->|<--------M bits ----->
 *
 *	M - number of node offset bits (35 .. 40)
 *	N - number of PNODE bits (0 .. 10)
 *
 *		Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64).
 *		The actual values are configuration dependent and are set at
 *		boot time. M & N values are set by the hardware/BIOS at boot.
 *
 *
 * APICID format
 * 	NOTE!!!!!! This is the current format of the APICID. However, code
 * 	should assume that this will change in the future. Use functions
 * 	in this file for all APICID bit manipulations and conversion.
 *
 * 		1111110000000000
 * 		5432109876543210
 *		pppppppppplc0cch
 *		sssssssssss
 *
 *			p  = pnode bits
 *			l =  socket number on board
 *			c  = core
 *			h  = hyperthread
 *			s  = bits that are in the SOCKET_ID CSR
 *
 *	Note: Processor only supports 12 bits in the APICID register. The ACPI
 *	      tables hold all 16 bits. Software needs to be aware of this.
 *
 * 	      Unless otherwise specified, all references to APICID refer to
 * 	      the FULL value contained in ACPI tables, not the subset in the
 * 	      processor APICID register.
 */


/*
 * Maximum number of bricks in all partitions and in all coherency domains.
 * This is the total number of bricks accessible in the numalink fabric. It
 * includes all C & M bricks. Routers are NOT included.
 *
 * This value is also the value of the maximum number of non-router NASIDs
 * in the numalink fabric.
 *
 * NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused.
 */
#define UV_MAX_NUMALINK_BLADES	16384

/*
 * Maximum number of C/Mbricks within a software SSI (hardware may support
 * more).
 */
#define UV_MAX_SSI_BLADES	256

/*
 * The largest possible NASID of a C or M brick (+ 2)
 */
#define UV_MAX_NASID_VALUE	(UV_MAX_NUMALINK_NODES * 2)

/*
 * The following defines attributes of the HUB chip. These attributes are
 * frequently referenced and are kept in the per-cpu data areas of each cpu.
 * They are kept together in a struct to minimize cache misses.
 */
struct uv_hub_info_s {
	unsigned long	global_mmr_base;
	unsigned long	gpa_mask;
	unsigned long	gnode_upper;
	unsigned long	lowmem_remap_top;
	unsigned long	lowmem_remap_base;
	unsigned short	pnode;
	unsigned short	pnode_mask;
	unsigned short	coherency_domain_number;
	unsigned short	numa_blade_id;
	unsigned char	blade_processor_id;
	unsigned char	m_val;
	unsigned char	n_val;
};
DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
#define uv_hub_info 		(&__get_cpu_var(__uv_hub_info))
#define uv_cpu_hub_info(cpu)	(&per_cpu(__uv_hub_info, cpu))

/*
 * Local & Global MMR space macros.
 * 	Note: macros are intended to be used ONLY by inline functions
 * 	in this file - not by other kernel code.
 * 		n -  NASID (full 15-bit global nasid)
 * 		g -  GNODE (full 15-bit global nasid, right shifted 1)
 * 		p -  PNODE (local part of nsids, right shifted 1)
 */
#define UV_NASID_TO_PNODE(n)		(((n) >> 1) & uv_hub_info->pnode_mask)
#define UV_PNODE_TO_NASID(p)		(((p) << 1) | uv_hub_info->gnode_upper)

#define UV_LOCAL_MMR_BASE		0xf4000000UL
#define UV_GLOBAL_MMR32_BASE		0xf8000000UL
#define UV_GLOBAL_MMR64_BASE		(uv_hub_info->global_mmr_base)
#define UV_LOCAL_MMR_SIZE		(64UL * 1024 * 1024)
#define UV_GLOBAL_MMR32_SIZE		(64UL * 1024 * 1024)

#define UV_GLOBAL_MMR32_PNODE_SHIFT	15
#define UV_GLOBAL_MMR64_PNODE_SHIFT	26

#define UV_GLOBAL_MMR32_PNODE_BITS(p)	((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT))

#define UV_GLOBAL_MMR64_PNODE_BITS(p)					\
	((unsigned long)(p) << UV_GLOBAL_MMR64_PNODE_SHIFT)

#define UV_APIC_PNODE_SHIFT	6

/*
 * Macros for converting between kernel virtual addresses, socket local physical
 * addresses, and UV global physical addresses.
 * 	Note: use the standard __pa() & __va() macros for converting
 * 	      between socket virtual and socket physical addresses.
 */

/* socket phys RAM --> UV global physical address */
static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr)
{
	if (paddr < uv_hub_info->lowmem_remap_top)
		paddr += uv_hub_info->lowmem_remap_base;
	return paddr | uv_hub_info->gnode_upper;
}


/* socket virtual --> UV global physical address */
static inline unsigned long uv_gpa(void *v)
{
	return __pa(v) | uv_hub_info->gnode_upper;
}

/* socket virtual --> UV global physical address */
static inline void *uv_vgpa(void *v)
{
	return (void *)uv_gpa(v);
}

/* UV global physical address --> socket virtual */
static inline void *uv_va(unsigned long gpa)
{
	return __va(gpa & uv_hub_info->gpa_mask);
}

/* pnode, offset --> socket virtual */
static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset)
{
	return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset);
}


/*
 * Extract a PNODE from an APICID (full apicid, not processor subset)
 */
static inline int uv_apicid_to_pnode(int apicid)
{
	return (apicid >> UV_APIC_PNODE_SHIFT);
}

/*
 * Access global MMRs using the low memory MMR32 space. This region supports
 * faster MMR access but not all MMRs are accessible in this space.
 */
static inline unsigned long *uv_global_mmr32_address(int pnode,
				unsigned long offset)
{
	return __va(UV_GLOBAL_MMR32_BASE |
		       UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset);
}

static inline void uv_write_global_mmr32(int pnode, unsigned long offset,
				 unsigned long val)
{
	*uv_global_mmr32_address(pnode, offset) = val;
}

static inline unsigned long uv_read_global_mmr32(int pnode,
						 unsigned long offset)
{
	return *uv_global_mmr32_address(pnode, offset);
}

/*
 * Access Global MMR space using the MMR space located at the top of physical
 * memory.
 */
static inline unsigned long *uv_global_mmr64_address(int pnode,
				unsigned long offset)
{
	return __va(UV_GLOBAL_MMR64_BASE |
		    UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset);
}

static inline void uv_write_global_mmr64(int pnode, unsigned long offset,
				unsigned long val)
{
	*uv_global_mmr64_address(pnode, offset) = val;
}

static inline unsigned long uv_read_global_mmr64(int pnode,
						 unsigned long offset)
{
	return *uv_global_mmr64_address(pnode, offset);
}

/*
 * Access hub local MMRs. Faster than using global space but only local MMRs
 * are accessible.
 */
static inline unsigned long *uv_local_mmr_address(unsigned long offset)
{
	return __va(UV_LOCAL_MMR_BASE | offset);
}

static inline unsigned long uv_read_local_mmr(unsigned long offset)
{
	return *uv_local_mmr_address(offset);
}

static inline void uv_write_local_mmr(unsigned long offset, unsigned long val)
{
	*uv_local_mmr_address(offset) = val;
}

/*
 * Structures and definitions for converting between cpu, node, pnode, and blade
 * numbers.
 */
struct uv_blade_info {
	unsigned short	nr_possible_cpus;
	unsigned short	nr_online_cpus;
	unsigned short	pnode;
};
extern struct uv_blade_info *uv_blade_info;
extern short *uv_node_to_blade;
extern short *uv_cpu_to_blade;
extern short uv_possible_blades;

/* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */
static inline int uv_blade_processor_id(void)
{
	return uv_hub_info->blade_processor_id;
}

/* Blade number of current cpu. Numnbered 0 .. <#blades -1> */
static inline int uv_numa_blade_id(void)
{
	return uv_hub_info->numa_blade_id;
}

/* Convert a cpu number to the the UV blade number */
static inline int uv_cpu_to_blade_id(int cpu)
{
	return uv_cpu_to_blade[cpu];
}

/* Convert linux node number to the UV blade number */
static inline int uv_node_to_blade_id(int nid)
{
	return uv_node_to_blade[nid];
}

/* Convert a blade id to the PNODE of the blade */
static inline int uv_blade_to_pnode(int bid)
{
	return uv_blade_info[bid].pnode;
}

/* Determine the number of possible cpus on a blade */
static inline int uv_blade_nr_possible_cpus(int bid)
{
	return uv_blade_info[bid].nr_possible_cpus;
}

/* Determine the number of online cpus on a blade */
static inline int uv_blade_nr_online_cpus(int bid)
{
	return uv_blade_info[bid].nr_online_cpus;
}

/* Convert a cpu id to the PNODE of the blade containing the cpu */
static inline int uv_cpu_to_pnode(int cpu)
{
	return uv_blade_info[uv_cpu_to_blade_id(cpu)].pnode;
}

/* Convert a linux node number to the PNODE of the blade */
static inline int uv_node_to_pnode(int nid)
{
	return uv_blade_info[uv_node_to_blade_id(nid)].pnode;
}

/* Maximum possible number of blades */
static inline int uv_num_possible_blades(void)
{
	return uv_possible_blades;
}

#endif /* _ASM_X86_UV_UV_HUB_H */
Commit	Line	Data
952cf6d7 JS	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* SGI UV architectural definitions
	7	*
9f5314fb	8	* Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
952cf6d7 JS	9	*/
952cf6d7 JS	10
05e4d316 PA	11	#ifndef _ASM_X86_UV_UV_HUB_H
05e4d316 PA	12	#define _ASM_X86_UV_UV_HUB_H
952cf6d7 JS	13
	14	#include <linux/numa.h>
	15	#include <linux/percpu.h>
c08b6acc	16	#include <linux/timer.h>
952cf6d7 JS	17	#include <asm/types.h>
	18	#include <asm/percpu.h>
	19
	20
	21	/*
	22	* Addressing Terminology
	23	*
9f5314fb JS	24	* M - The low M bits of a physical address represent the offset
	25	* into the blade local memory. RAM memory on a blade is physically
	26	* contiguous (although various IO spaces may punch holes in
	27	* it)..
952cf6d7	28	*
9f5314fb JS	29	* N - Number of bits in the node portion of a socket physical
	30	* address.
	31	*
	32	* NASID - network ID of a router, Mbrick or Cbrick. Nasid values of
	33	* routers always have low bit of 1, C/MBricks have low bit
	34	* equal to 0. Most addressing macros that target UV hub chips
	35	* right shift the NASID by 1 to exclude the always-zero bit.
	36	* NASIDs contain up to 15 bits.
	37	*
	38	* GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
	39	* of nasids.
	40	*
	41	* PNODE - the low N bits of the GNODE. The PNODE is the most useful variant
	42	* of the nasid for socket usage.
	43	*
	44	*
	45	* NumaLink Global Physical Address Format:
	46	* +--------------------------------+---------------------+
	47	* \|00..000\| GNODE \| NodeOffset \|
	48	* +--------------------------------+---------------------+
	49	* \|<-------53 - M bits --->\|<--------M bits ----->
	50	*
	51	* M - number of node offset bits (35 .. 40)
952cf6d7 JS	52	*
	53	*
	54	* Memory/UV-HUB Processor Socket Address Format:
9f5314fb JS	55	* +----------------+---------------+---------------------+
	56	* \|00..000000000000\| PNODE \| NodeOffset \|
	57	* +----------------+---------------+---------------------+
	58	* <--- N bits --->\|<--------M bits ----->
952cf6d7	59	*
9f5314fb JS	60	* M - number of node offset bits (35 .. 40)
9f5314fb JS	61	* N - number of PNODE bits (0 .. 10)
952cf6d7 JS	62	*
	63	* Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64).
	64	* The actual values are configuration dependent and are set at
9f5314fb JS	65	* boot time. M & N values are set by the hardware/BIOS at boot.
9f5314fb JS	66	*
952cf6d7 JS	67	*
	68	* APICID format
	69	* NOTE!!!!!! This is the current format of the APICID. However, code
	70	* should assume that this will change in the future. Use functions
	71	* in this file for all APICID bit manipulations and conversion.
	72	*
	73	* 1111110000000000
	74	* 5432109876543210
9f5314fb	75	* pppppppppplc0cch
952cf6d7 JS	76	* sssssssssss
952cf6d7 JS	77	*
9f5314fb	78	* p = pnode bits
952cf6d7 JS	79	* l = socket number on board
	80	* c = core
	81	* h = hyperthread
9f5314fb	82	* s = bits that are in the SOCKET_ID CSR
952cf6d7 JS	83	*
	84	* Note: Processor only supports 12 bits in the APICID register. The ACPI
	85	* tables hold all 16 bits. Software needs to be aware of this.
	86	*
	87	* Unless otherwise specified, all references to APICID refer to
	88	* the FULL value contained in ACPI tables, not the subset in the
	89	* processor APICID register.
	90	*/
	91
	92
	93	/*
	94	* Maximum number of bricks in all partitions and in all coherency domains.
	95	* This is the total number of bricks accessible in the numalink fabric. It
	96	* includes all C & M bricks. Routers are NOT included.
	97	*
	98	* This value is also the value of the maximum number of non-router NASIDs
	99	* in the numalink fabric.
	100	*
9f5314fb	101	* NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused.
952cf6d7 JS	102	*/
	103	#define UV_MAX_NUMALINK_BLADES 16384
	104
	105	/*
	106	* Maximum number of C/Mbricks within a software SSI (hardware may support
	107	* more).
	108	*/
	109	#define UV_MAX_SSI_BLADES 256
	110
	111	/*
	112	* The largest possible NASID of a C or M brick (+ 2)
	113	*/
	114	#define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_NODES * 2)
	115
	116	/*
	117	* The following defines attributes of the HUB chip. These attributes are
	118	* frequently referenced and are kept in the per-cpu data areas of each cpu.
	119	* They are kept together in a struct to minimize cache misses.
	120	*/
	121	struct uv_hub_info_s {
	122	unsigned long global_mmr_base;
9f5314fb JS	123	unsigned long gpa_mask;
	124	unsigned long gnode_upper;
	125	unsigned long lowmem_remap_top;
	126	unsigned long lowmem_remap_base;
	127	unsigned short pnode;
	128	unsigned short pnode_mask;
952cf6d7 JS	129	unsigned short coherency_domain_number;
	130	unsigned short numa_blade_id;
	131	unsigned char blade_processor_id;
	132	unsigned char m_val;
	133	unsigned char n_val;
	134	};
	135	DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
	136	#define uv_hub_info (&__get_cpu_var(__uv_hub_info))
	137	#define uv_cpu_hub_info(cpu) (&per_cpu(__uv_hub_info, cpu))
	138
	139	/*
	140	* Local & Global MMR space macros.
	141	* Note: macros are intended to be used ONLY by inline functions
	142	* in this file - not by other kernel code.
9f5314fb JS	143	* n - NASID (full 15-bit global nasid)
	144	* g - GNODE (full 15-bit global nasid, right shifted 1)
	145	* p - PNODE (local part of nsids, right shifted 1)
952cf6d7	146	*/
9f5314fb JS	147	#define UV_NASID_TO_PNODE(n) (((n) >> 1) & uv_hub_info->pnode_mask)
9f5314fb JS	148	#define UV_PNODE_TO_NASID(p) (((p) << 1) \| uv_hub_info->gnode_upper)
952cf6d7 JS	149
	150	#define UV_LOCAL_MMR_BASE 0xf4000000UL
	151	#define UV_GLOBAL_MMR32_BASE 0xf8000000UL
	152	#define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base)
83f5d894 JS	153	#define UV_LOCAL_MMR_SIZE (64UL * 1024 * 1024)
83f5d894 JS	154	#define UV_GLOBAL_MMR32_SIZE (64UL * 1024 * 1024)
952cf6d7	155
9f5314fb JS	156	#define UV_GLOBAL_MMR32_PNODE_SHIFT 15
9f5314fb JS	157	#define UV_GLOBAL_MMR64_PNODE_SHIFT 26
952cf6d7	158
9f5314fb	159	#define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT))
952cf6d7	160
9f5314fb JS	161	#define UV_GLOBAL_MMR64_PNODE_BITS(p) \
	162	((unsigned long)(p) << UV_GLOBAL_MMR64_PNODE_SHIFT)
	163
	164	#define UV_APIC_PNODE_SHIFT 6
	165
	166	/*
	167	* Macros for converting between kernel virtual addresses, socket local physical
	168	* addresses, and UV global physical addresses.
	169	* Note: use the standard __pa() & __va() macros for converting
	170	* between socket virtual and socket physical addresses.
	171	*/
	172
	173	/* socket phys RAM --> UV global physical address */
	174	static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr)
	175	{
	176	if (paddr < uv_hub_info->lowmem_remap_top)
	177	paddr += uv_hub_info->lowmem_remap_base;
	178	return paddr \| uv_hub_info->gnode_upper;
	179	}
	180
	181
	182	/* socket virtual --> UV global physical address */
	183	static inline unsigned long uv_gpa(void *v)
	184	{
	185	return __pa(v) \| uv_hub_info->gnode_upper;
	186	}
	187
	188	/* socket virtual --> UV global physical address */
	189	static inline void uv_vgpa(void v)
	190	{
	191	return (void *)uv_gpa(v);
	192	}
	193
	194	/* UV global physical address --> socket virtual */
	195	static inline void *uv_va(unsigned long gpa)
	196	{
	197	return __va(gpa & uv_hub_info->gpa_mask);
	198	}
	199
	200	/* pnode, offset --> socket virtual */
	201	static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset)
	202	{
	203	return __va(((unsigned long)pnode << uv_hub_info->m_val) \| offset);
	204	}
952cf6d7	205
952cf6d7 JS	206
952cf6d7 JS	207	/*
9f5314fb	208	* Extract a PNODE from an APICID (full apicid, not processor subset)
952cf6d7	209	*/
9f5314fb	210	static inline int uv_apicid_to_pnode(int apicid)
952cf6d7	211	{
9f5314fb	212	return (apicid >> UV_APIC_PNODE_SHIFT);
952cf6d7 JS	213	}
	214
	215	/*
	216	* Access global MMRs using the low memory MMR32 space. This region supports
	217	* faster MMR access but not all MMRs are accessible in this space.
	218	*/
9f5314fb	219	static inline unsigned long *uv_global_mmr32_address(int pnode,
952cf6d7 JS	220	unsigned long offset)
	221	{
	222	return __va(UV_GLOBAL_MMR32_BASE \|
9f5314fb	223	UV_GLOBAL_MMR32_PNODE_BITS(pnode) \| offset);
952cf6d7 JS	224	}
952cf6d7 JS	225
9f5314fb	226	static inline void uv_write_global_mmr32(int pnode, unsigned long offset,
952cf6d7 JS	227	unsigned long val)
952cf6d7 JS	228	{
9f5314fb	229	*uv_global_mmr32_address(pnode, offset) = val;
952cf6d7 JS	230	}
952cf6d7 JS	231
9f5314fb	232	static inline unsigned long uv_read_global_mmr32(int pnode,
952cf6d7 JS	233	unsigned long offset)
952cf6d7 JS	234	{
9f5314fb	235	return *uv_global_mmr32_address(pnode, offset);
952cf6d7 JS	236	}
	237
	238	/*
	239	* Access Global MMR space using the MMR space located at the top of physical
	240	* memory.
	241	*/
9f5314fb	242	static inline unsigned long *uv_global_mmr64_address(int pnode,
952cf6d7 JS	243	unsigned long offset)
	244	{
	245	return __va(UV_GLOBAL_MMR64_BASE \|
9f5314fb	246	UV_GLOBAL_MMR64_PNODE_BITS(pnode) \| offset);
952cf6d7 JS	247	}
952cf6d7 JS	248
9f5314fb	249	static inline void uv_write_global_mmr64(int pnode, unsigned long offset,
952cf6d7 JS	250	unsigned long val)
952cf6d7 JS	251	{
9f5314fb	252	*uv_global_mmr64_address(pnode, offset) = val;
952cf6d7 JS	253	}
952cf6d7 JS	254
9f5314fb	255	static inline unsigned long uv_read_global_mmr64(int pnode,
952cf6d7 JS	256	unsigned long offset)
952cf6d7 JS	257	{
9f5314fb	258	return *uv_global_mmr64_address(pnode, offset);
952cf6d7 JS	259	}
	260
	261	/*
9f5314fb	262	* Access hub local MMRs. Faster than using global space but only local MMRs
952cf6d7 JS	263	* are accessible.
	264	*/
	265	static inline unsigned long *uv_local_mmr_address(unsigned long offset)
	266	{
	267	return __va(UV_LOCAL_MMR_BASE \| offset);
	268	}
	269
	270	static inline unsigned long uv_read_local_mmr(unsigned long offset)
	271	{
	272	return *uv_local_mmr_address(offset);
	273	}
	274
	275	static inline void uv_write_local_mmr(unsigned long offset, unsigned long val)
	276	{
	277	*uv_local_mmr_address(offset) = val;
	278	}
	279
8400def8	280	/*
9f5314fb	281	* Structures and definitions for converting between cpu, node, pnode, and blade
8400def8 JS	282	* numbers.
	283	*/
	284	struct uv_blade_info {
9f5314fb	285	unsigned short nr_possible_cpus;
8400def8	286	unsigned short nr_online_cpus;
9f5314fb	287	unsigned short pnode;
8400def8	288	};
9f5314fb	289	extern struct uv_blade_info *uv_blade_info;
8400def8 JS	290	extern short *uv_node_to_blade;
	291	extern short *uv_cpu_to_blade;
	292	extern short uv_possible_blades;
	293
	294	/* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */
	295	static inline int uv_blade_processor_id(void)
	296	{
	297	return uv_hub_info->blade_processor_id;
	298	}
	299
	300	/* Blade number of current cpu. Numnbered 0 .. <#blades -1> */
	301	static inline int uv_numa_blade_id(void)
	302	{
	303	return uv_hub_info->numa_blade_id;
	304	}
	305
	306	/* Convert a cpu number to the the UV blade number */
	307	static inline int uv_cpu_to_blade_id(int cpu)
	308	{
	309	return uv_cpu_to_blade[cpu];
	310	}
	311
	312	/* Convert linux node number to the UV blade number */
	313	static inline int uv_node_to_blade_id(int nid)
	314	{
	315	return uv_node_to_blade[nid];
	316	}
	317
9f5314fb JS	318	/* Convert a blade id to the PNODE of the blade */
9f5314fb JS	319	static inline int uv_blade_to_pnode(int bid)
8400def8	320	{
9f5314fb	321	return uv_blade_info[bid].pnode;
8400def8 JS	322	}
	323
	324	/* Determine the number of possible cpus on a blade */
	325	static inline int uv_blade_nr_possible_cpus(int bid)
	326	{
9f5314fb	327	return uv_blade_info[bid].nr_possible_cpus;
8400def8 JS	328	}
	329
	330	/* Determine the number of online cpus on a blade */
	331	static inline int uv_blade_nr_online_cpus(int bid)
	332	{
	333	return uv_blade_info[bid].nr_online_cpus;
	334	}
	335
9f5314fb JS	336	/* Convert a cpu id to the PNODE of the blade containing the cpu */
9f5314fb JS	337	static inline int uv_cpu_to_pnode(int cpu)
8400def8	338	{
9f5314fb	339	return uv_blade_info[uv_cpu_to_blade_id(cpu)].pnode;
8400def8 JS	340	}
8400def8 JS	341
9f5314fb JS	342	/* Convert a linux node number to the PNODE of the blade */
9f5314fb JS	343	static inline int uv_node_to_pnode(int nid)
8400def8	344	{
9f5314fb	345	return uv_blade_info[uv_node_to_blade_id(nid)].pnode;
8400def8 JS	346	}
	347
	348	/* Maximum possible number of blades */
	349	static inline int uv_num_possible_blades(void)
	350	{
	351	return uv_possible_blades;
	352	}
	353
05e4d316	354	#endif /* _ASM_X86_UV_UV_HUB_H */
952cf6d7	355